The "target_hart" and "hart_count" parameters of PLIC cold and
warm init functions are only used for sanity checks and not
required in PLIC initialization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Any platform feature that belongs to a hart, have already been moved to
hart features and are detected at run time. The remaining platform features
are identical to platform default features.
Use the platform default features instead of defining a separate copy of it.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
PMP & performance counters belong to a hart rather than a platform.
In addition to that, these features enable reading/writing from a
particular csr. Thus, they can be detected and set at runtime rather
than compile time.
Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
The OpenSBI generic platform works perfectly fine on the QEMU spike
machine and Spike emulator so let's remove dedicated Spike platform
from OpenSBI.
All Spike platform related documentation in OpenSBI will now suggest
using OpenSBI generic platform.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
The OpenSBI generic platform works perfectly fine on the QEMU virt
machine so let's remove dedicated QEMU virt machine platform from
OpenSBI.
All QEMU virt machine related documentation in OpenSBI will now
suggest using OpenSBI generic platform.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
We need to override the remote TLB flush range limit for SiFive FU540
so we add platform override to achieve this.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add generic FDT based platform support which provides platform
specific functionality based on the FDT passed by previous booting
stage.
By default, the generic FDT platform makes following assumptions:
1. platform FW_TEXT_START is 0x80000000
2. platform features are default
3. platform stack size is default
4. platform has no quirks or work-arounds
The above assumptions (except 1) can be overridden by adding special
platform callbacks which will be called based on the FDT root node
compatible string.
By default, we compile OpenSBI generic platform as follows:
$ make PLATFORM=generic
For a non-standard FW_TEXT_START, we can compile OpenSBI generic
platform as follows:
$ make PLATFORM=generic FW_TEXT_START=<non_standard_text_start>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The fdt_parse_clint() is quite generic and can be used for other
types of devices so we rename it to fdt_parse_compat_addr().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This patch factor-out SiFive test device related stuff into
it's own source file from qemu/virt platform. In future, we
can find SiFive test device address from device tree as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We can achieve shutdown, cold reboot, and warm reboot using just
one sbi_platform callback so we combine system_reboot() and
system_shutdown() callbacks into one system_reset() callback.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The default (usually last) PMP region provides S-mode access to
complete memory range not covered by other PMP regions.
Currently, the default PMP region is described as platform specific
PMP region which is not appropriate because all platforms need it
and default PMP region should be part of generic library.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
OpenPiton is designed to run on different FPGAs with different
configurations. Use the fdt parser to retrieve the required values
from device tree instead of using fixed values.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
FDT helper file contain both fdt fixup and parsing functions.
Split the fixup related functions to a separate file for a better code
organization.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
OpenPiton is a research platform from Princeton University [1].
"OpenPiton is the world's first open source, general purpose,
multithreaded manycore processor. It is a tiled manycore
framework scalable from one to 1/2 billion cores."
Add OpenSBI support for OpenPiton. As it is based on ariane core,
it reuses the platform code from arine project.
[1]. https://github.com/PrincetonUniversity/openpiton
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
All the common PLIC specific macros are already defined in plic.c.
Remove it from platform code. While at it, Fix the other coding style
issues.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
The FU540_ENABLED_HART_MASK compile time option was added for initial
bring-up on SiFive Unleashed. This option is redundant now because
disabled_hart_mask is already removed. Based on this rationale, we
remove FU540_ENABLED_HART_MASK compile time option.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
A platform can have discontinuous and/or sparse HART ids so we
cannot always assume a set of HARTs with continuous HART ids.
This patch adds support for discontinuous and sparse HART ids by
introducing HART index to HART id table. This table has platform
hart_count entries and it maps HART index to HART id.
The HART index to HART id table has only two restrictions:
1. HART index < sbi_platform hart_count
2. HART id < SBI_HARTMASK_MAX_BITS
Example1:
Let's say we have a platform with 2 HART ids 11 and 22, for such a
a platform:
hart_count = 2
hart_index2id[0] = 11
hart_index2id[1] = 22
Example2:
Let's say we have a platform with 5 HARTs ids 0, 1, 2, 3, and 4
but out of these HART with id 0 is not usable so for such a platform:
hart_count = 5
hart_index2id[0] = -1U
hart_index2id[1] = 1
hart_index2id[2] = 2
hart_index2id[3] = 3
hart_index2id[4] = 4
OR
hart_count = 4
hart_index2id[0] = 1
hart_index2id[1] = 2
hart_index2id[2] = 3
hart_index2id[3] = 4
With HART index to HART id table in place, the hart_disabled()
callback is now redundant so we remove it as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Platform andes/ae350, ariane-fpga, qemu/virt and sifive/fu540 codes
have been updated to call this general DT fix-up helper.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This replaces the FU540 specific cpu0 node "status" property fix-up
with the newly introduced generic fdt_cpu_fixup() helper.
Unlike previous logic, the helper routine does not test the "mmu-type"
property to determine which node we should fix up, instead it uses
sbi_platform_hart_disabled() API.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
As of today the upstream U-Boot & Linux kernel ships a device tree
that already has "stdout-path" properly set in the "/chosen" node.
This is the same with the QEMU 'sifive_u' machine. Hence the codes
to fix up the "stdout-path" in OpenSBI is not necessary.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This calls fdt_reserved_memory_fixup() helper in the platform's
final_init() routine.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This calls fdt_reserved_memory_fixup() helper in the platform's
final_init() routine.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This calls fdt_reserved_memory_fixup() helper in the platform's
final_init() routine.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This calls fdt_reserved_memory_fixup() helper in the platform's
final_init() routine.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Now that we have a dedicated fdt_helper.c file for DT releated
helper routines, move plic_fdt_fixup() codes from plic.c to
fdt_helper.c and rename it to fdt_plic_fixup() at the same time,
to keep name consistency in the same file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Adjust the order of include header files in alphabetical order in
platform codes. Also remove unnecessary inclusions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
As of today all platforms use 8KB of per-HART stack hence there is
no need for each platform to define its own macro or use the magic
number. Create one macro for all platforms. Platform still can use
its own version if needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
The template platform codes should set per-HART stack size to 8KB
to avoid possible mistakes of future platform ports.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Recent commit
4a603eb ("platform: kendryte/k210: Set per-HART stack size to 8KB")
forgot to update ariane-fpga codes, and the following commit
678c3c3 ("include: sbi_scratch: Set per-HART scratch size to 4KB")
changed the per-HART scratch size to 4KB, which potentially breaks
ariane-fpga platform.
This patch set per-HART stack size of ariane-fpga to 8KB for consistency.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
The sbi_current_hartid() being a regular function is quite
expensive because for callers it is a function call instead
of a direct CSR read. This patch converts sbi_current_hartid()
into a macro in riscv_asm.h.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The disabled_hard_mask in sbi_platform is only 64bits wide so we
cannot disable a HART with HARTID > 63. To tackle this, we remove
disabled_hart_mask and replace it with hart_disabled() platform
callback.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
All platform except kendryte/k210 use 8KB of per-HART stack hence
this patch set per-HART stack size of kendryte/k210 to 8KB for
consistency.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
There has already been a commit to master which added 32-bit specific
fdt/payload addresses for the sifive/fu540 platform [0]. This commit
introduces another change for using sifive/fu540 as a 32-bit platform.
On 32-bit platforms, cores with the SV32 MMU type should not be
disabled. For this reason, this commit also allows using this MMU type
on the sifive/fu540 platform.
Alternatively it would also be possible to only allow SV39 and SV48 if
`__riscv_xlen == 64` and SV32 if `__riscv_xlen == 32`. Removing the
check entirely would also be an option.
[0]: 66fb729a1e
Signed-off-by: Sören Tempel <tempel@uni-bremen.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
For testing 32-bit SiFive specific drivers with QEMU riscv32, add
32-bit specific FW_JUMP_FDT_ADDR and FW_PAYLOAD_OFFSET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This patch removes stale options from config.mk files of
Ariane FPGA and QEMU virt platform support.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
With QEMU v4.2 RISC-V changes to improve the emulation fidelity
of 'sifive_u' machine, OpenSBI v0.4 / U-Boot v2019.10 / Linux
kernel v5.3 images built for the SiFive HiFive Unleashed board
can be used out of the box without any special hack. Hence there
is no need for us to continue supporting such a special target in
OpenSBI. Going forward, sifive/fu540 platform can be used on both
real hardware and QEMU 'sifive_u' machine.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
It was reported that tlb range flush is not working on fu540.
Only tlb full flush seems to work on fu540 probably due to some
hardware errata.
Set the tlb flush limit to zero so that all tlb flush requests
are converted to full flush.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
If a platform requires to perform a tlb full flush, they should set
the tlb_range_flush_limit value to zero. However, corresponding platform
API ignore the value and continue to return the default value.
Add a platform ops to retrieve platform specific tlb range flush limit.
The platform variable becomes redundant in presence of the platform ops.
Take this opportunity to remove the variable as well.
The default is still set to smallest page size in RISC-V (4KB), as there
is no way to figure out a best value for all platforms. Individual platform
should set it to the optimal value for their platform.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Since all harts share the same plic/clint address now, setting
them during cold boot is just fine.
Signed-off-by: Liu Yibin <yibin_liu@c-sky.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Since all harts share the same L2 cache now, there's
no need to Enable L2 cache in warm boot.
Signed-off-by: Liu Yibin <yibin_liu@c-sky.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
