Nick Hu
1514a32730
lib: utils/hsm: Add SiFive TMC0 driver
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The SiFive TMC0 controls the tile power domains on SiFive platform. The
CPU enters the low power state via the `CEASE` instruction after
configuring the TMC0. Any devices that inside the tile power domain will
be power gated, including the private cache. Therefore flushing the
private cache before entering the low power state.
Co-developed-by: Vincent Chen <vincent.chen@sifive.com >
Signed-off-by: Vincent Chen <vincent.chen@sifive.com >
Reviewed-by: Cyan Yang <cyan.yang@sifive.com >
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-10-28 11:28:03 +05:30
Xianbin Zhu
fb70fe8b98
platform: spacemit: Add HSM driver
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Add code to bring up all 8 cores during OpenSBI initialization so
that the Linux kernel can detect and use all cores properly.
Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com >
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com >
Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-10-20 10:29:50 +05:30
Subrahmanya Lingappa
33ee9b8240
lib: utils/hsm: Add RPMI HSM driver
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The RPMI HSM service group provides set of routine to query and control
power states of a Hart. Add RPMI based Hart State Management (HSM) driver.
Signed-off-by: Subrahmanya Lingappa <slingappa@ventanamicro.com >
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
2024-12-06 09:26:43 +05:30
Anup Patel
ff4769bf08
lib: utils: Add simple FDT based HSM driver framework
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The generic platform can have multiple HSM drivers so add a simple
FDT based HSM driver framework.
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
2024-12-06 09:26:40 +05:30
