3 Commits

Include renames

Author	SHA1	Message	Date
Nick HuandAnup Patel	1514a32730	lib: utils/hsm: Add SiFive TMC0 driver ... The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>	2025-10-28 11:28:03 +05:30
Samuel HollandandAnup Patel	434add551c	lib: utils: Initialize miscellaneous drivers in one pass ... For driver subsystems that are not tightly integrated into the OpenSBI init sequence, it is not important that the drivers are initialized in any particular order. By putting all of these drivers in one array, they can all be initialized with a single pass through the devicetree. This saves about 10 ms of boot time on HiFive Unmatched. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2025-02-12 21:39:25 +05:30
Anup PatelandAnup Patel	ff4769bf08	lib: utils: Add simple FDT based HSM driver framework ... The generic platform can have multiple HSM drivers so add a simple FDT based HSM driver framework. Signed-off-by: Anup Patel <apatel@ventanamicro.com>	2024-12-06 09:26:40 +05:30