3 Commits

Include renames

Author	SHA1	Message	Date
Nick HuandAnup Patel	37b72cb575	lib: utils/suspend: Add SiFive SMC0 driver ... The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>	2025-10-28 11:28:10 +05:30
Subrahmanya LingappaandAnup Patel	13f55f33a1	lib: utils/suspend: Add RPMI system suspend driver ... Add RPMI based system suspend driver. To test this, execute the follwoing in Linux: $ echo mem > /sys/power/state To wake up, execute the following command on qemu monitor terminal: (qemu) system_wakeup Signed-off-by: Subrahmanya Lingappa <slingappa@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>	2024-12-06 09:26:32 +05:30
Anup PatelandAnup Patel	3676324b0e	lib: utils: Add simple FDT based system suspend driver framework ... The generic platform can have multiple system suspend drivers so add a simple FDT based system suspend driver framework. Signed-off-by: Anup Patel <apatel@ventanamicro.com>	2024-12-06 09:26:29 +05:30