Vladimir Kondratiev
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52ac3de50c
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platform: generic: mips p8700: faster core boot
When powering up cores, wait for power up to complete
using tight loop. This saves 10ms delay observed for every core
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-6-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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2026-02-25 18:49:03 +05:30 |
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Vladimir Kondratiev
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6545b78bcd
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platform: generic: mips p8700: fix powering up other cluster
While powering up cluster, only indication is bit in cluster
power control.
It used to wait for CORE0 in that cluster reach U5 state
(non-coherent execution), this won't happen when only CM
powered up without booting any core
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-5-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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2026-02-25 18:49:03 +05:30 |
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Vladimir Kondratiev
|
698ea046e2
|
platform: generic: mips p8700: reserve memory for M-mode peripherals
Reserve memory upfront in large well aligned chunks,
to avoid problem with PMP granularity that is
64Kbytes for the p8700 CPU
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-4-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
|
2026-02-25 18:49:03 +05:30 |
|
Anup Patel
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55296fd27c
|
lib: Allow custom CSRs in csr_read_num() and csr_write_num()
Some of the platforms use platform specific CSR access functions for
configuring implementation specific CSRs (such as PMA registers).
Extend the common csr_read_num() and csr_write_num() to allow custom
CSRs so that platform specific CSR access functions are not needed.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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2025-10-21 19:34:09 +05:30 |
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Chao-ying Fu
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1ffbd063c4
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generic: mips: support harts to boot from mips_warm_boot
We program reset base for harts (other than hart 0) to boot at
mips_warm_boot that jumps to _start_warm. This helps to skip some code
sequence to speed up.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250723204010.9927-1-cfu@mips.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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2025-08-28 11:00:16 +05:30 |
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Chao-ying Fu
|
13abda5169
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lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()
Allow platforms to implement platform specific PMP setup and
PMP disable functions which are called before actual PMP CSRs
are configured.
Also, implement pmp_set() and pmp_disable() for MIPS P8700.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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2025-06-17 09:34:01 +05:30 |
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Chao-ying Fu
|
66ab965e54
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platform: generic: mips: add P8700
Extend generic platform to support MIPS P8700.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250522212141.3198-2-cfu@mips.com
Signed-off-by: Anup Patel <anup@brainfault.org>
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2025-06-14 21:44:11 +05:30 |
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