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4c5d9d9f93c77805dbc023cdef6a68c039b87970
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3 Commits
Author SHA1 Message Date
Ben Zong-You Xie 4c5d9d9f93 lib: utils/andes: add the SMU and LLC registers to the root domain 
When a hart implements Smepmp, S-mode and U-mode cannot reach either
device unless its region is shared explicitly. Suspend and resume then
take an access violation as soon as the supervisor touches the SMU or
the LLC.

Share both regions, and take their sizes from the DT nodes rather than
ignoring them.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260728081041.2724668-3-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
 2026-09-01 10:46:23 +05:30
Ben Zong-You Xie 344428d832 lib: utils/cache: fix andes_llcache_enable() return value 
The driver returned 1 on success where callers expect 0, so the suspend
to RAM aborted right after disabling the LLC and before flushing it.

Fixes: 82b0961821 ("lib: utils/cache: add Andes last level cache controller")
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260728081041.2724668-2-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
 2026-09-01 10:46:23 +05:30
Ben Zong-You Xie 82b0961821 lib: utils/cache: add Andes last level cache controller 
Introduce a FDT-based driver for the Andes Last Level Cache (LLC)
controller to support cache maintenance operations.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
 2026-02-11 12:13:01 +05:30