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Merge pull request #4 from riscv/avpatel/master

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Remove PLAT_<xyz> defines from platform and firmwares
This commit is contained in:
Atish Patra
2018-12-22 10:02:52 -08:00
committed by GitHub
parent 51d3964f07 4e8d078613
commit fef12701fd
13 changed files with 94 additions and 80 deletions
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2
README.md
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@@ -59,7 +59,7 @@ OR
`make PLATFORM=<platform_subdir> I=<install_directory> install`
In addition, we can also specify platform specific command-line
options to top-level make (such as `PLAT_<xyz>` or `FW_<abc>`)
options to top-level make (such as `PLATFORM_<xyz>` or `FW_<abc>`)
which are described under `docs/platform/<platform_name>.md` OR
`docs/firmware/<firmware_name>.md`.

63
firmware/fw_common.S
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@@ -122,18 +122,29 @@ _start_warm:
csrw mie, zero
csrw mip, zero
/* set MSIE bit to receive IPI */
/* Set MSIE bit to receive IPI */
li a2, MIP_MSIP
csrw mie, a2
/* Preload per-HART details
* s6 -> HART ID
* s7 -> HART Count
* s8 -> HART Stack Size
*/
csrr s6, mhartid
la a4, platform
lwu s7, RISCV_PLATFORM_HART_COUNT_OFFSET(a4)
lwu s8, RISCV_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
/* HART ID should be within expected limit */
csrr a6, mhartid
li a5, PLAT_HART_COUNT
bge a6, a5, _start_hang
csrr s6, mhartid
bge s6, s7, _start_hang
/* Setup scratch space */
li a5, PLAT_HART_STACK_SIZE
la tp, _stack_end
mul a5, a5, a6
la tp, _fw_end
mul a5, s7, s8
add tp, tp, a5
mul a5, s8, s6
sub tp, tp, a5
li a5, RISCV_SCRATCH_SIZE
sub tp, tp, a5
@@ -143,6 +154,8 @@ _start_warm:
REG_S zero, RISCV_SCRATCH_TMP0_OFFSET(tp)
la a4, _fw_start
la a5, _fw_end
mul t0, s7, s8
add a5, a5, t0
sub a5, a5, a4
REG_S a4, RISCV_SCRATCH_FW_START_OFFSET(tp)
REG_S a5, RISCV_SCRATCH_FW_SIZE_OFFSET(tp)
@@ -180,18 +193,30 @@ _start_warm:
.section .entry, "ax", %progbits
.globl _hartid_to_scratch
_hartid_to_scratch:
add sp, sp, -(2 * __SIZEOF_POINTER__)
REG_S a1, (sp)
REG_S a2, (__SIZEOF_POINTER__)(sp)
li a1, PLAT_HART_STACK_SIZE
la a2, _stack_end
mul a1, a1, a0
sub a2, a2, a1
li a1, RISCV_SCRATCH_SIZE
sub a0, a2, a1
REG_L a1, (sp)
REG_L a2, (__SIZEOF_POINTER__)(sp)
add sp, sp, (2 * __SIZEOF_POINTER__)
add sp, sp, -(3 * __SIZEOF_POINTER__)
REG_S s0, (sp)
REG_S s1, (__SIZEOF_POINTER__)(sp)
REG_S s2, (__SIZEOF_POINTER__ * 2)(sp)
/*
* a0 -> HART ID (passed by caller)
* s0 -> HART Stack Size
* s1 -> HART Stack End
* s2 -> Temporary
*/
la s2, platform
lwu s0, RISCV_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
lwu s2, RISCV_PLATFORM_HART_COUNT_OFFSET(s2)
mul s2, s2, s0
la s1, _fw_end
add s1, s1, s2
mul s2, s0, a0
sub s1, s1, s2
li s2, RISCV_SCRATCH_SIZE
sub a0, s1, s2
REG_L s0, (sp)
REG_L s1, (__SIZEOF_POINTER__)(sp)
REG_L s2, (__SIZEOF_POINTER__ * 2)(sp)
add sp, sp, (3 * __SIZEOF_POINTER__)
ret
.align 3

12
firmware/fw_common.ldS
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@@ -61,18 +61,6 @@
. = ALIGN(0x1000); /* Ensure next section is page aligned */
.stack :
{
PROVIDE(_stack_start = .);
*(.stack)
*(.stack.*)
. = . + (PLAT_HART_STACK_SIZE * PLAT_HART_COUNT);
. = ALIGN(8);
PROVIDE(_stack_end = .);
}
. = ALIGN(0x1000); /* Ensure next section is page aligned */
.bss :
{
PROVIDE(_bss_start = .);

5
include/sbi/riscv_asm.h
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@@ -81,6 +81,11 @@
#define RISCV_SCRATCH_IPI_TYPE_OFFSET (9 * __SIZEOF_POINTER__)
#define RISCV_SCRATCH_SIZE 256
#define RISCV_PLATFORM_NAME_OFFSET (0x0)
#define RISCV_PLATFORM_FEATURES_OFFSET (0x40)
#define RISCV_PLATFORM_HART_COUNT_OFFSET (0x48)
#define RISCV_PLATFORM_HART_STACK_SIZE_OFFSET (0x4c)
#define RISCV_TRAP_REGS_zero 0
#define RISCV_TRAP_REGS_ra 1
#define RISCV_TRAP_REGS_sp 2

6
platform/kendryte/k210/config.mk
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@@ -7,12 +7,8 @@
# SPDX-License-Identifier: BSD-2-Clause
#
# Essential defines required by SBI platform
platform-cppflags-y = -DPLAT_NAME="Kendryte K210"
platform-cppflags-y+= -DPLAT_HART_COUNT=2
platform-cppflags-y+= -DPLAT_HART_STACK_SIZE=4096
# Compiler flags
platform-cppflags-y =
platform-cflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-asflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-ldflags-y =

12
platform/kendryte/k210/platform.c
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@@ -38,7 +38,7 @@ static char k210_console_getc(void)
static int k210_cold_irqchip_init(void)
{
return plic_cold_irqchip_init(PLIC_BASE_ADDR, PLIC_NUM_SOURCES,
PLAT_HART_COUNT);
K210_HART_COUNT);
}
static int k210_warm_irqchip_init(u32 core_id)
@@ -50,12 +50,12 @@ static int k210_warm_irqchip_init(u32 core_id)
static int k210_cold_ipi_init(void)
{
return clint_cold_ipi_init(CLINT_BASE_ADDR, PLAT_HART_COUNT);
return clint_cold_ipi_init(CLINT_BASE_ADDR, K210_HART_COUNT);
}
static int k210_cold_timer_init(void)
{
return clint_cold_timer_init(CLINT_BASE_ADDR, PLAT_HART_COUNT);
return clint_cold_timer_init(CLINT_BASE_ADDR, K210_HART_COUNT);
}
static int k210_system_reboot(u32 type)
@@ -76,11 +76,11 @@ static int k210_system_shutdown(u32 type)
struct sbi_platform platform = {
.name = STRINGIFY(PLAT_NAME),
.name = "Kendryte K210",
.features = SBI_PLATFORM_HAS_MMIO_TIMER_VALUE,
.hart_count = PLAT_HART_COUNT,
.hart_stack_size = PLAT_HART_STACK_SIZE,
.hart_count = K210_HART_COUNT,
.hart_stack_size = K210_HART_STACK_SIZE,
.disabled_hart_mask = 0,
.console_init = k210_console_init,

5
platform/kendryte/k210/platform.h
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@@ -18,12 +18,15 @@
#include <sbi/riscv_asm.h>
#define K210_HART_COUNT 2
#define K210_HART_STACK_SIZE 4096
/* Register base address */
/* Under Coreplex */
#define CLINT_BASE_ADDR (0x02000000U)
#define PLIC_BASE_ADDR (0x0C000000U)
#define PLIC_NUM_CORES (PLAT_HART_COUNT)
#define PLIC_NUM_CORES (K210_HART_COUNT)
/* Under TileLink */
#define GPIOHS_BASE_ADDR (0x38001000U)

6
platform/qemu/sifive_u/config.mk
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@@ -7,12 +7,8 @@
# SPDX-License-Identifier: BSD-2-Clause
#
# Essential defines required by SBI platform
platform-cppflags-y = -DPLAT_NAME="QEMU SiFive Unleashed"
platform-cppflags-y+= -DPLAT_HART_COUNT=1
platform-cppflags-y+= -DPLAT_HART_STACK_SIZE=8192
# Compiler flags
platform-cppflags-y =
platform-cflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-asflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-ldflags-y =

17
platform/qemu/sifive_u/platform.c
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@@ -14,6 +14,9 @@
#include <plat/serial/sifive-uart.h>
#include <plat/sys/clint.h>
#define SIFIVE_U_HART_COUNT 1
#define SIFIVE_U_HART_STACK_SIZE 8192
#define SIFIVE_U_SYS_CLK 1000000000
#define SIFIVE_U_PERIPH_CLK (SIFIVE_U_SYS_CLK / 2)
@@ -31,7 +34,7 @@ static int sifive_u_cold_final_init(void)
u32 i;
void *fdt = sbi_scratch_thishart_arg1_ptr();
for (i = 0; i < PLAT_HART_COUNT; i++)
for (i = 0; i < SIFIVE_U_HART_COUNT; i++)
plic_fdt_fixup(fdt, "riscv,plic0", 2 * i);
return 0;
@@ -71,7 +74,7 @@ static int sifive_u_cold_irqchip_init(void)
{
return plic_cold_irqchip_init(SIFIVE_U_PLIC_ADDR,
SIFIVE_U_PLIC_NUM_SOURCES,
PLAT_HART_COUNT);
SIFIVE_U_HART_COUNT);
}
static int sifive_u_warm_irqchip_init(u32 target_hart)
@@ -84,13 +87,13 @@ static int sifive_u_warm_irqchip_init(u32 target_hart)
static int sifive_u_cold_ipi_init(void)
{
return clint_cold_ipi_init(SIFIVE_U_CLINT_ADDR,
PLAT_HART_COUNT);
SIFIVE_U_HART_COUNT);
}
static int sifive_u_cold_timer_init(void)
{
return clint_cold_timer_init(SIFIVE_U_CLINT_ADDR,
PLAT_HART_COUNT);
SIFIVE_U_HART_COUNT);
}
static int sifive_u_system_down(u32 type)
@@ -100,10 +103,10 @@ static int sifive_u_system_down(u32 type)
}
struct sbi_platform platform = {
.name = STRINGIFY(PLAT_NAME),
.name = "QEMU SiFive Unleashed",
.features = SBI_PLATFORM_DEFAULT_FEATURES,
.hart_count = PLAT_HART_COUNT,
.hart_stack_size = PLAT_HART_STACK_SIZE,
.hart_count = SIFIVE_U_HART_COUNT,
.hart_stack_size = SIFIVE_U_HART_STACK_SIZE,
.disabled_hart_mask = 0,
.pmp_region_count = sifive_u_pmp_region_count,
.pmp_region_info = sifive_u_pmp_region_info,

6
platform/qemu/virt/config.mk
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@@ -7,12 +7,8 @@
# SPDX-License-Identifier: BSD-2-Clause
#
# Essential defines required by SBI platform
platform-cppflags-y = -DPLAT_NAME="QEMU Virt Machine"
platform-cppflags-y+= -DPLAT_HART_COUNT=8
platform-cppflags-y+= -DPLAT_HART_STACK_SIZE=8192
# Compiler flags
platform-cppflags-y =
platform-cflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-asflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-ldflags-y =

17
platform/qemu/virt/platform.c
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@@ -14,6 +14,9 @@
#include <plat/serial/uart8250.h>
#include <plat/sys/clint.h>
#define VIRT_HART_COUNT 8
#define VIRT_HART_STACK_SIZE 8192
#define VIRT_TEST_ADDR 0x100000
#define VIRT_CLINT_ADDR 0x2000000
@@ -31,7 +34,7 @@ static int virt_cold_final_init(void)
u32 i;
void *fdt = sbi_scratch_thishart_arg1_ptr();
for (i = 0; i < PLAT_HART_COUNT; i++)
for (i = 0; i < VIRT_HART_COUNT; i++)
plic_fdt_fixup(fdt, "riscv,plic0", 2 * i);
return 0;
@@ -72,7 +75,7 @@ static int virt_cold_irqchip_init(void)
{
return plic_cold_irqchip_init(VIRT_PLIC_ADDR,
VIRT_PLIC_NUM_SOURCES,
PLAT_HART_COUNT);
VIRT_HART_COUNT);
}
static int virt_warm_irqchip_init(u32 target_hart)
@@ -85,13 +88,13 @@ static int virt_warm_irqchip_init(u32 target_hart)
static int virt_cold_ipi_init(void)
{
return clint_cold_ipi_init(VIRT_CLINT_ADDR,
PLAT_HART_COUNT);
VIRT_HART_COUNT);
}
static int virt_cold_timer_init(void)
{
return clint_cold_timer_init(VIRT_CLINT_ADDR,
PLAT_HART_COUNT);
VIRT_HART_COUNT);
}
static int virt_system_down(u32 type)
@@ -101,10 +104,10 @@ static int virt_system_down(u32 type)
}
struct sbi_platform platform = {
.name = STRINGIFY(PLAT_NAME),
.name = "QEMU Virt Machine",
.features = SBI_PLATFORM_DEFAULT_FEATURES,
.hart_count = PLAT_HART_COUNT,
.hart_stack_size = PLAT_HART_STACK_SIZE,
.hart_count = VIRT_HART_COUNT,
.hart_stack_size = VIRT_HART_STACK_SIZE,
.disabled_hart_mask = 0,
.pmp_region_count = virt_pmp_region_count,
.pmp_region_info = virt_pmp_region_info,

6
platform/sifive/hifive_u540/config.mk
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@@ -7,12 +7,8 @@
# SPDX-License-Identifier: BSD-2-Clause
#
# Essential defines required by SBI platform
platform-cppflags-y = -DPLAT_NAME="SiFive HiFive U540"
platform-cppflags-y+= -DPLAT_HART_COUNT=5
platform-cppflags-y+= -DPLAT_HART_STACK_SIZE=8192
# Compiler flags
platform-cppflags-y =
platform-cflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-asflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany
platform-ldflags-y =

17
platform/sifive/hifive_u540/platform.c
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@@ -15,6 +15,9 @@
#include <plat/serial/sifive-uart.h>
#include <plat/sys/clint.h>
#define SIFIVE_U_HART_COUNT 5
#define SIFIVE_U_HART_STACK_SIZE 8192
#define SIFIVE_U_SYS_CLK 1000000000
#define SIFIVE_U_CLINT_ADDR 0x2000000
@@ -41,7 +44,7 @@ static int sifive_u_cold_final_init(void)
void *fdt = sbi_scratch_thishart_arg1_ptr();
plic_fdt_fixup(fdt, "riscv,plic0", 0);
for (i = 1; i < PLAT_HART_COUNT; i++)
for (i = 1; i < SIFIVE_U_HART_COUNT; i++)
plic_fdt_fixup(fdt, "riscv,plic0", 2 * i - 1);
return 0;
@@ -91,7 +94,7 @@ static int sifive_u_cold_irqchip_init(void)
{
return plic_cold_irqchip_init(SIFIVE_U_PLIC_ADDR,
SIFIVE_U_PLIC_NUM_SOURCES,
PLAT_HART_COUNT);
SIFIVE_U_HART_COUNT);
}
static int sifive_u_warm_irqchip_init(u32 target_hart)
@@ -104,13 +107,13 @@ static int sifive_u_warm_irqchip_init(u32 target_hart)
static int sifive_u_cold_ipi_init(void)
{
return clint_cold_ipi_init(SIFIVE_U_CLINT_ADDR,
PLAT_HART_COUNT);
SIFIVE_U_HART_COUNT);
}
static int sifive_u_cold_timer_init(void)
{
return clint_cold_timer_init(SIFIVE_U_CLINT_ADDR,
PLAT_HART_COUNT);
SIFIVE_U_HART_COUNT);
}
static int sifive_u_system_down(u32 type)
@@ -120,10 +123,10 @@ static int sifive_u_system_down(u32 type)
}
struct sbi_platform platform = {
.name = STRINGIFY(PLAT_NAME),
.name = "SiFive HiFive U540",
.features = SBI_PLATFORM_DEFAULT_FEATURES,
.hart_count = PLAT_HART_COUNT,
.hart_stack_size = PLAT_HART_STACK_SIZE,
.hart_count = SIFIVE_U_HART_COUNT,
.hart_stack_size = SIFIVE_U_HART_STACK_SIZE,
.disabled_hart_mask = ~(1 << SIFIVE_U_HARITD_ENABLED),
.pmp_region_count = sifive_u_pmp_region_count,
.pmp_region_info = sifive_u_pmp_region_info,