Mirrors/opensbi
1
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2025-08-24 23:41:23 +01:00
Code Issues Packages Projects Releases Wiki Activity

lib: sbi: Detect mcountinihibit support at runtime

Browse Source 
RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows
software to stop any counter from incrementing. The SBI PMU extension
depends on this CSR support in hardware.

Define mcountinhibit as a hart specific feature and detect it at runtime.

Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Atish Patra
2021-07-10 09:18:03 -07:00
committed by Anup Patel
parent 3e8b31aca9
commit fde28fadc2
2 changed files with 14 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/sbi/sbi_hart.h
View File

@@ -18,8 +18,10 @@ enum sbi_hart_features {
SBI_HART_HAS_SCOUNTEREN = (1 << 0),
/** Hart has M-mode counter enable */
SBI_HART_HAS_MCOUNTEREN = (1 << 1),
/** Hart has counter inhibit CSR */
SBI_HART_HAS_MCOUNTINHIBIT = (1 << 2),
/** HART has timer csr implementation in hardware */
SBI_HART_HAS_TIME = (1 << 2),
SBI_HART_HAS_TIME = (1 << 3),
/** Last index of Hart features*/
SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME,