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https://github.com/riscv-software-src/opensbi.git
synced 2026-05-23 14:21:32 +01:00
platform: Remove kendryte/k210 platform
The kendryte/k210 platform does not have MMU support in S-mode hence only NOMMU kernel which runs in M-mode can be used on this platform. As of now, there is no clear use-case of supporting OpenSBI for kendryte/k210 platform. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260409045310.2045739-1-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
@@ -402,6 +402,5 @@ make I=<install_directory> install_docs
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[Firmware Documentation]: docs/firmware/fw.md
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[Domain Support]: docs/domain_support.md
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[Doxygen manual]: http://www.doxygen.nl/manual/index.html
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[Kendryte standalone SDK]: https://github.com/kendryte/kendryte-standalone-sdk
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[third party notices]: ThirdPartyNotices.md
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[reproducible builds]: https://reproducible-builds.org
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@@ -18,9 +18,6 @@ OpenSBI currently supports the following virtual and hardware platforms:
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machine. More details on this platform can be found in the file
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*[sifive_fu540.md]*.
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* **Kendryte K210 SoC**: Platform support for the Kendryte K210 SoC used on
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boards such as the Kendryte KD233 or the Sipeed MAIX Dock.
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* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350). More
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details on this platform can be found in the file *[andes-ae350.md]*.
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@@ -1,10 +0,0 @@
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# SPDX-License-Identifier: BSD-2-Clause
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config PLATFORM_KENDRYTE_K210
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bool
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select FDT
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select IPI_MSWI
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select IRQCHIP_PLIC
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select SERIAL_SIFIVE
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select TIMER_MTIMER
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default y
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@@ -1,70 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "kendryte,k210";
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chosen {
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bootargs = "console=hvc0 earlycon=sbi";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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clock-frequency = <390000000>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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mmu-type = "none";
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reg = <0>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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clock-frequency = <390000000>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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mmu-type = "none";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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memory@80000000 {
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/* Bank 0: 4 MB, Bank 1: 2 MB, AI chip SRAM: 2MB */
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x00800000>;
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};
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plic0: interrupt-controller@C000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended =
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<&cpu0_intc 11 &cpu0_intc 9
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&cpu1_intc 11 &cpu1_intc 9>;
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reg = <0x0 0xc000000 0x0 0x4000000>;
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};
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};
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@@ -1,25 +0,0 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2019 Western Digital Corporation or its affiliates.
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#
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# Authors:
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# Damien Le Moal <damien.lemoal@wdc.com>
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#
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# Compiler flags
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platform-cppflags-y =
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platform-cflags-y =
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platform-asflags-y =
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platform-ldflags-y =
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# Objects to build
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platform-objs-y += platform.o
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platform-objs-y += k210.o
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platform-varprefix-k210.o = dt_k210
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platform-padding-k210.o = 2048
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# Blobs to build
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FW_PAYLOAD=y
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FW_PAYLOAD_ALIGN=0x1000
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@@ -1,176 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_system.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/ipi/aclint_mswi.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/sifive-uart.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#include "platform.h"
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extern const char dt_k210_start[];
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unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
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unsigned long arg2, unsigned long arg3,
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unsigned long arg4)
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{
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return (unsigned long)&dt_k210_start[0];
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}
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static struct plic_data plic = {
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.unique_id = 0,
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.addr = K210_PLIC_BASE_ADDR,
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.size = K210_PLIC_BASE_SIZE,
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.num_src = K210_PLIC_NUM_SOURCES,
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.context_map = {
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[0] = { 0, 1 },
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[1] = { 2, 3 },
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},
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};
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static struct aclint_mswi_data mswi = {
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.addr = K210_ACLINT_MSWI_ADDR,
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.size = ACLINT_MSWI_SIZE,
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.first_hartid = 0,
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.hart_count = K210_HART_COUNT,
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};
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static struct aclint_mtimer_data mtimer = {
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.mtime_freq = K210_ACLINT_MTIMER_FREQ,
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.mtime_addr = K210_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIME_OFFSET,
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.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
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.mtimecmp_addr = K210_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIMECMP_OFFSET,
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.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
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.first_hartid = 0,
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.hart_count = K210_HART_COUNT,
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.has_64bit_mmio = true,
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};
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static u32 k210_get_clk_freq(void)
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{
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u32 clksel0, pll0;
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u64 pll0_freq, clkr0, clkf0, clkod0, div;
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/*
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* If the clock selector is not set, use the base frequency.
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* Otherwise, use PLL0 frequency with a frequency divisor.
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*/
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clksel0 = k210_read_sysreg(K210_CLKSEL0);
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if (!(clksel0 & 0x1))
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return K210_CLK0_FREQ;
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/*
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* Get PLL0 frequency:
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* freq = base frequency * clkf0 / (clkr0 * clkod0)
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*/
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pll0 = k210_read_sysreg(K210_PLL0);
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clkr0 = 1 + (pll0 & 0x0000000f);
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clkf0 = 1 + ((pll0 & 0x000003f0) >> 4);
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clkod0 = 1 + ((pll0 & 0x00003c00) >> 10);
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pll0_freq = clkf0 * K210_CLK0_FREQ / (clkr0 * clkod0);
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/* Get the frequency divisor from the clock selector */
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div = 2ULL << ((clksel0 & 0x00000006) >> 1);
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return pll0_freq / div;
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}
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static int k210_system_reset_check(u32 type, u32 reason)
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{
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return 1;
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}
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static void k210_system_reset(u32 type, u32 reason)
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{
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u32 val;
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val = k210_read_sysreg(K210_RESET);
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val |= K210_RESET_MASK;
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k210_write_sysreg(val, K210_RESET);
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while (1);
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}
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static struct sbi_system_reset_device k210_reset = {
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.name = "kendryte_k210_reset",
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.system_reset_check = k210_system_reset_check,
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.system_reset = k210_system_reset
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};
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static int k210_early_init(bool cold_boot)
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{
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int rc;
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if (!cold_boot)
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return 0;
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sbi_system_reset_add_device(&k210_reset);
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rc = sifive_uart_init(K210_UART_BASE_ADDR, k210_get_clk_freq(),
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K210_UART_BAUDRATE);
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if (rc)
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return rc;
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return aclint_mswi_cold_init(&mswi);
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}
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static int k210_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = fdt_get_address_rw();
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fdt_cpu_fixup(fdt);
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fdt_fixups(fdt);
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return 0;
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}
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static int k210_irqchip_init(void)
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{
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return plic_cold_irqchip_init(&plic);
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}
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static int k210_timer_init(void)
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{
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return aclint_mtimer_cold_init(&mtimer, NULL);
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}
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const struct sbi_platform_operations platform_ops = {
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.early_init = k210_early_init,
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.final_init = k210_final_init,
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.irqchip_init = k210_irqchip_init,
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.timer_init = k210_timer_init,
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "Kendryte K210",
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.features = 0,
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.hart_count = K210_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.heap_size =
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SBI_PLATFORM_DEFAULT_HEAP_SIZE(K210_HART_COUNT),
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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@@ -1,50 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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#ifndef _K210_PLATFORM_H_
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#define _K210_PLATFORM_H_
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#include <sbi/riscv_io.h>
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#define K210_HART_COUNT 2
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#define K210_UART_BAUDRATE 115200
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#define K210_ACLINT_MTIMER_FREQ 7800000
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#define K210_CLK0_FREQ 26000000UL
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#define K210_PLIC_NUM_SOURCES 65
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/* Registers base address */
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#define K210_SYSCTL_BASE_ADDR 0x50440000ULL
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#define K210_UART_BASE_ADDR 0x38000000ULL
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#define K210_CLINT_BASE_ADDR 0x02000000ULL
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#define K210_ACLINT_MSWI_ADDR \
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(K210_CLINT_BASE_ADDR + CLINT_MSWI_OFFSET)
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#define K210_ACLINT_MTIMER_ADDR \
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(K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET)
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#define K210_PLIC_BASE_ADDR 0x0C000000ULL
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#define K210_PLIC_BASE_SIZE (0x200000ULL + (K210_HART_COUNT * 0x1000))
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/* Registers */
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#define K210_PLL0 0x08
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#define K210_CLKSEL0 0x20
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#define K210_RESET 0x30
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/* Register bit masks */
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#define K210_RESET_MASK 0x01
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static inline u32 k210_read_sysreg(u32 reg)
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{
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return readl((volatile void *)(K210_SYSCTL_BASE_ADDR + reg));
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}
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static inline void k210_write_sysreg(u32 val, u32 reg)
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{
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writel(val, (volatile void *)(K210_SYSCTL_BASE_ADDR + reg));
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}
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#endif /* _K210_PLATFORM_H_ */
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@@ -100,7 +100,6 @@ build_opensbi() {
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64)
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# Setup 64-bit platform list
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BUILD_PLATFORM_SUBDIR+=("nuclei/ux600")
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BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
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BUILD_PLATFORM_SUBDIR+=("generic")
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;;
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*)
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