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platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
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committed by
Anup Patel

parent
bf40e07f6f
commit
eeab500a65
@@ -5,6 +5,7 @@
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*/
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#include <andes/andes45_pma.h>
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#include <andes/andes_sbi.h>
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#include <platform_override.h>
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#include <sbi/sbi_domain.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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@@ -55,4 +56,5 @@ const struct platform_override renesas_rzfive = {
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.match_table = renesas_rzfive_match,
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.early_init = renesas_rzfive_early_init,
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.final_init = renesas_rzfive_final_init,
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.vendor_ext_provider = andes_sbi_vendor_ext_provider,
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};
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