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platform: generic: mips p8700: cache geometry detection
P8700 has a read-only cache configuration registers. Provide a CPU specific function to extract cache information. Use this information in the eyeq7h board for informational message Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-14-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
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committed by
Anup Patel
parent
8935f79c95
commit
df7bbe7c2e
@@ -123,6 +123,51 @@ int mips_p8700_hart_stop()
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return 0;
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}
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void mips_p8700_cache_info(struct p8700_cache_info *l1d, struct p8700_cache_info *l1i,
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struct p8700_cache_info *l2)
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{
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u32 mipsconfig1 = csr_read(CSR_MIPSCONFIG1);
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if (l1d) {
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u32 da = EXTRACT_FIELD(mipsconfig1, MIPSCONFIG1_DA);
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u32 dl = EXTRACT_FIELD(mipsconfig1, MIPSCONFIG1_DL);
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u32 ds = EXTRACT_FIELD(mipsconfig1, MIPSCONFIG1_DS);
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l1d->line = dl ? 1 << (dl + 1) : 0;
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l1d->assoc_ways = da +1;
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l1d->sets = ds == 7 ? 32 : 1 << (ds + 6);
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}
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if (l1i) {
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u32 ia = EXTRACT_FIELD(mipsconfig1, MIPSCONFIG1_IA);
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u32 il = EXTRACT_FIELD(mipsconfig1, MIPSCONFIG1_IL);
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u32 is = EXTRACT_FIELD(mipsconfig1, MIPSCONFIG1_IS);
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l1i->line = il ? 1 << (il + 1) : 0;
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l1i->assoc_ways = ia +1;
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l1i->sets = is == 7 ? 32 : 1 << (is + 6);
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}
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if (l2) {
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if (mipsconfig1 & MIPSCONFIG1_L2C) {
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void *cm_base = (void *)p8700_cm_info->gcr_base[0];
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u32 l2_config = readl(cm_base + GCR_L2_CONFIG);
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if (l2_config & GCR_L2_REG_EXISTS) {
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u32 l2a = EXTRACT_FIELD(l2_config, GCR_L2_ASSOC);
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u32 l2l = EXTRACT_FIELD(l2_config, GCR_L2_LINE_SIZE);
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u32 l2s = EXTRACT_FIELD(l2_config, GCR_L2_SET_SIZE);
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l2->assoc_ways = l2a + 1;
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l2->line = 1 << (l2l + 1);
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l2->sets = 1 << (l2s + 6);
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return;
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}
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}
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l2->line = 0;
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l2->assoc_ways = 0;
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l2->sets = 0;
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}
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}
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int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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const struct p8700_cm_info *data = match->data;
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