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https://github.com/riscv-software-src/opensbi.git
synced 2026-05-23 14:21:32 +01:00
lib: sbi_irqchip: Allow setting hardware interrupt affinity
The irqchip drivers can provide mechanism to set interrupt affinity so add hwirq_set_affinity() callback for irqchip drivers and use it to implement sbi_irqchip_set_affinity() which can be used by other drivers. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260423052339.356900-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
@@ -60,6 +60,10 @@ struct sbi_irqchip_device {
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/** End of hardware interrupt of this irqchip */
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void (*hwirq_eoi)(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Set hardware interrupt affinity */
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int (*hwirq_set_affinity)(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 hart_index);
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/** Mask a hardware interrupt of this irqchip */
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void (*hwirq_mask)(struct sbi_irqchip_device *chip, u32 hwirq);
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@@ -98,6 +102,13 @@ int sbi_irqchip_raw_handler_default(struct sbi_irqchip_device *chip, u32 hwirq);
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int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,
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int (*raw_hndl)(struct sbi_irqchip_device *, u32));
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/** Get hardware interrupt affinity */
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int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 *out_hart_index);
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/** Set hardware interrupt affinity */
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int sbi_irqchip_set_affinity(struct sbi_irqchip_device *chip, u32 hwirq, u32 hart_index);
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/** Register a hardware interrupt handler */
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int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,
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u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,
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+122
-1
@@ -7,7 +7,9 @@
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_heap.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_irqchip.h>
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_platform.h>
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@@ -17,6 +19,9 @@
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struct sbi_irqchip_hwirq_data {
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/** raw hardware interrupt handler */
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int (*raw_handler)(struct sbi_irqchip_device *chip, u32 hwirq);
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/** target hart index */
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u32 hart_index;
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};
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/** Internal irqchip interrupt handler */
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@@ -136,6 +141,78 @@ int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,
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return 0;
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}
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int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 *out_hart_index)
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{
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if (!chip || chip->num_hwirq <= hwirq)
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return SBI_EINVAL;
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/*
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* If no handler registered for hwirq then hwirq
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* is not being used so return failure
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*/
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if (!sbi_irqchip_find_handler(chip, hwirq))
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return SBI_ENOTSUPP;
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*out_hart_index = chip->hwirqs[hwirq].hart_index;
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return 0;
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}
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int sbi_irqchip_set_affinity(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 hart_index)
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{
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struct sbi_irqchip_hwirq_data *data;
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int rc;
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if (!chip || chip->num_hwirq <= hwirq || sbi_hart_count() <= hart_index)
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return SBI_EINVAL;
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/*
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* If no handler registered for hwirq then hwirq
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* is not being used so return failure
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*/
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if (!sbi_irqchip_find_handler(chip, hwirq))
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return SBI_ENOTSUPP;
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data = &chip->hwirqs[hwirq];
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if (data->hart_index != hart_index) {
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if (chip->hwirq_set_affinity) {
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rc = chip->hwirq_set_affinity(chip, hwirq, hart_index);
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if (rc)
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return rc;
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}
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data->hart_index = hart_index;
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}
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return 0;
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}
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static int __sbi_irqchip_handler_set_affinity(struct sbi_irqchip_device *chip,
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struct sbi_irqchip_handler *h,
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u32 compare_hart_index,
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u32 hart_index)
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{
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u32 i, current_hart_index;
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int rc;
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for (i = 0; i < h->num_hwirq; i++) {
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rc = sbi_irqchip_get_affinity(chip, h->first_hwirq + i,
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¤t_hart_index);
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if (rc)
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return rc;
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if (compare_hart_index != -1U &&
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current_hart_index != compare_hart_index)
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continue;
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rc = sbi_irqchip_set_affinity(chip, h->first_hwirq + i, hart_index);
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if (rc)
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return rc;
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}
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return 0;
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}
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static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,
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u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,
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int (*callback)(u32 hwirq, void *priv), void *priv)
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@@ -185,6 +262,17 @@ static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,
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}
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}
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rc = __sbi_irqchip_handler_set_affinity(chip, h, -1U, current_hartindex());
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if (rc) {
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if (chip->hwirq_cleanup) {
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for (i = 0; i < h->num_hwirq; i++)
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chip->hwirq_cleanup(chip, h->first_hwirq + i);
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}
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sbi_list_del(&h->node);
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sbi_free(h);
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return rc;
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}
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if (chip->hwirq_unmask) {
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for (i = 0; i < h->num_hwirq; i++)
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chip->hwirq_unmask(chip, h->first_hwirq + i);
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@@ -294,8 +382,10 @@ int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)
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chip->hwirqs = sbi_zalloc(sizeof(*chip->hwirqs) * chip->num_hwirq);
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if (!chip->hwirqs)
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return SBI_ENOMEM;
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for (i = 0; i < chip->num_hwirq; i++)
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for (i = 0; i < chip->num_hwirq; i++) {
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sbi_irqchip_set_raw_handler(chip, i, sbi_irqchip_raw_handler_default);
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chip->hwirqs[i].hart_index = -1U;
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}
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SBI_INIT_LIST_HEAD(&chip->handler_list);
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@@ -340,6 +430,37 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
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void sbi_irqchip_exit(struct sbi_scratch *scratch)
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{
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struct sbi_irqchip_hart_data *hd;
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struct sbi_irqchip_device *chip;
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struct sbi_irqchip_handler *h;
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u32 migrate_hidx = -1U;
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bool migrate = false;
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int rc;
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sbi_for_each_hartindex(i) {
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if (i == current_hartindex())
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continue;
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if (__sbi_hsm_hart_get_state(i) == SBI_HSM_STATE_STOPPED ||
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__sbi_hsm_hart_get_state(i) == SBI_HSM_STATE_STOP_PENDING)
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continue;
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migrate_hidx = i;
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migrate = true;
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break;
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}
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if (!migrate)
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goto skip_migrate;
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sbi_list_for_each_entry(chip, &irqchip_list, node) {
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sbi_list_for_each_entry(h, &chip->handler_list, node) {
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rc = __sbi_irqchip_handler_set_affinity(chip, h,
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current_hartindex(),
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migrate_hidx);
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if (rc) {
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sbi_printf("%s: chip 0x%x handler 0x%x set affinity (err %d)\n",
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__func__, chip->id, h->first_hwirq, rc);
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}
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}
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}
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skip_migrate:
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (hd && hd->chip && hd->chip->process_hwirqs)
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