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platform: andes/ae350: Remove enabling cache from an350_final_init

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The boot-time cache operations have been handled by U-boot SPL, so we
can drop duplicate code.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yu Chien Peter Lin
2022-10-14 08:32:43 +08:00
committed by Anup Patel
parent dcdaf30274
commit bd7ef41398
1 changed files with 0 additions and 19 deletions
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19
platform/andes/ae350/platform.c
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@@ -34,25 +34,6 @@ static int ae350_final_init(bool cold_boot)
{ {
void *fdt; void *fdt;
/* enable L1 cache */
uintptr_t mcache_ctl_val = csr_read(CSR_MCACHECTL);
if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
csr_write(CSR_MCACHECTL, mcache_ctl_val);
/* enable L2 cache */
uint32_t *l2c_ctl_base = (void *)AE350_L2C_ADDR + V5_L2C_CTL_OFFSET;
uint32_t l2c_ctl_val = *l2c_ctl_base;
if (!(l2c_ctl_val & V5_L2C_CTL_ENABLE_MASK))
l2c_ctl_val |= V5_L2C_CTL_ENABLE_MASK;
*l2c_ctl_base = l2c_ctl_val;
if (!cold_boot) if (!cold_boot)
return 0; return 0;