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lib: Use proper add opcode on RV32 with Zalrsc

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The addw opcode is only defined in RV64, which produces 32-bit results.
On RV32, the default add opcode already produces 32-bit results.

Fixes: 995f226f3f ("lib: Emit lr and sc instructions based on -march flags")
Signed-off-by: Marti Alonso <martialonso11@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Marti Alonso
2026-03-01 20:54:21 +00:00
committed by Anup Patel
parent ef1ee40e7d
commit b5348006e9
3 changed files with 7 additions and 2 deletions
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lib/sbi/riscv_atomic.c
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@@ -48,7 +48,7 @@ long atomic_add_return(atomic_t *atom, long value)
long ret, temp;
#if __SIZEOF_LONG__ == 4
__asm__ __volatile__("1:lr.w.aqrl %1,%0\n"
" addw %2,%1,%3\n"
" add %2,%1,%3\n"
" sc.w.aqrl %2,%2,%0\n"
" bnez %2,1b"
: "+A"(atom->counter), "=&r"(ret), "=&r"(temp)