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lib: Use proper add opcode on RV32 with Zalrsc

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The addw opcode is only defined in RV64, which produces 32-bit results.
On RV32, the default add opcode already produces 32-bit results.

Fixes: 995f226f3f ("lib: Emit lr and sc instructions based on -march flags")
Signed-off-by: Marti Alonso <martialonso11@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Marti Alonso
2026-03-01 20:54:21 +00:00
committed by Anup Patel
parent ef1ee40e7d
commit b5348006e9
3 changed files with 7 additions and 2 deletions
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3
firmware/payloads/test_head.S
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@@ -22,6 +22,7 @@
#define REG_L __REG_SEL(ld, lw)
#define REG_S __REG_SEL(sd, sw)
#define REG_ADDW __REG_SEL(addw, add)
.section .entry, "ax", %progbits
.align 3
@@ -35,7 +36,7 @@ _start:
#elif defined(__riscv_zalrsc)
_sc_fail:
lr.w t0, (a3)
addw t1, t0, a2
REG_ADDW t1, t0, a2
sc.w t1, t1, (a3)
bnez t1, _sc_fail
move a3, t0