Mirrors/opensbi
7
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2025-08-25 15:51:41 +01:00
Code Issues Packages Projects Releases Wiki Activity

lib: sbi_pmu: Update sbi_pmu dev ops

Browse Source 
Update fw_event_validate_code, fw_counter_match_code and fw_counter_start
ops which used a 32 bit event code to use the 64 bit event data instead.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Mayuresh Chitale
2023-03-09 18:43:55 +05:30
committed by Anup Patel
parent 548e4b4b28
commit b51ddffcc0
2 changed files with 21 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
include/sbi/sbi_pmu.h
View File

@@ -30,16 +30,15 @@ struct sbi_pmu_device {
/** /**
* Validate event code of custom firmware event * Validate event code of custom firmware event
* Note: SBI_PMU_FW_MAX <= event_idx_code
*/ */
int (*fw_event_validate_code)(uint32_t event_idx_code); int (*fw_event_validate_encoding)(uint64_t event_data);
/** /**
* Match custom firmware counter with custom firmware event * Match custom firmware counter with custom firmware event
* Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
*/ */
bool (*fw_counter_match_code)(uint32_t counter_index, bool (*fw_counter_match_encoding)(uint32_t counter_index,
uint32_t event_idx_code); uint64_t event_data);
/** /**
* Fetch the max width of this counter in number of bits. * Fetch the max width of this counter in number of bits.
@@ -58,7 +57,7 @@ struct sbi_pmu_device {
* Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
*/ */
int (*fw_counter_start)(uint32_t counter_index, int (*fw_counter_start)(uint32_t counter_index,
uint32_t event_idx_code, uint64_t event_data,
uint64_t init_val, bool init_val_update); uint64_t init_val, bool init_val_update);
/** /**

30
lib/sbi/sbi_pmu.c
View File

@@ -110,7 +110,7 @@ static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt,
return false; return false;
} }
static int pmu_event_validate(unsigned long event_idx) static int pmu_event_validate(unsigned long event_idx, uint64_t edata)
{ {
uint32_t event_idx_type = get_cidx_type(event_idx); uint32_t event_idx_type = get_cidx_type(event_idx);
uint32_t event_idx_code = get_cidx_code(event_idx); uint32_t event_idx_code = get_cidx_code(event_idx);
@@ -123,8 +123,8 @@ static int pmu_event_validate(unsigned long event_idx)
break; break;
case SBI_PMU_EVENT_TYPE_FW: case SBI_PMU_EVENT_TYPE_FW:
if (SBI_PMU_FW_MAX <= event_idx_code && if (SBI_PMU_FW_MAX <= event_idx_code &&
pmu_dev && pmu_dev->fw_event_validate_code) pmu_dev && pmu_dev->fw_event_validate_encoding)
return pmu_dev->fw_event_validate_code(event_idx_code); return pmu_dev->fw_event_validate_encoding(edata);
else else
event_idx_code_max = SBI_PMU_FW_MAX; event_idx_code_max = SBI_PMU_FW_MAX;
break; break;
@@ -361,7 +361,8 @@ int sbi_pmu_irq_bit(void)
} }
static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
uint64_t ival, bool ival_update) uint64_t event_data, uint64_t ival,
bool ival_update)
{ {
int ret; int ret;
u32 hartid = current_hartid(); u32 hartid = current_hartid();
@@ -369,7 +370,7 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
if (SBI_PMU_FW_MAX <= event_code && if (SBI_PMU_FW_MAX <= event_code &&
pmu_dev && pmu_dev->fw_counter_start) { pmu_dev && pmu_dev->fw_counter_start) {
ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs, ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs,
event_code, event_data,
ival, ival_update); ival, ival_update);
if (ret) if (ret)
return ret; return ret;
@@ -390,6 +391,7 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
int ret = SBI_EINVAL; int ret = SBI_EINVAL;
bool bUpdate = false; bool bUpdate = false;
int i, cidx; int i, cidx;
uint64_t edata = 0;
if ((cbase + sbi_fls(cmask)) >= total_ctrs) if ((cbase + sbi_fls(cmask)) >= total_ctrs)
return ret; return ret;
@@ -404,7 +406,8 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
/* Continue the start operation for other counters */ /* Continue the start operation for other counters */
continue; continue;
else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW)
ret = pmu_ctr_start_fw(cidx, event_code, ival, bUpdate); ret = pmu_ctr_start_fw(cidx, event_code, edata, ival,
bUpdate);
else else
ret = pmu_ctr_start_hw(cidx, ival, bUpdate); ret = pmu_ctr_start_hw(cidx, ival, bUpdate);
} }
@@ -644,7 +647,7 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo
* check. * check.
*/ */
static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask,
uint32_t event_code, u32 hartid) uint32_t event_code, u32 hartid, uint64_t edata)
{ {
int i, cidx; int i, cidx;
@@ -655,9 +658,9 @@ static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask,
if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID) if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID)
continue; continue;
if (SBI_PMU_FW_MAX <= event_code && if (SBI_PMU_FW_MAX <= event_code &&
pmu_dev && pmu_dev->fw_counter_match_code) { pmu_dev && pmu_dev->fw_counter_match_encoding) {
if (!pmu_dev->fw_counter_match_code(cidx - num_hw_ctrs, if (!pmu_dev->fw_counter_match_encoding(cidx - num_hw_ctrs,
event_code)) edata))
continue; continue;
} }
@@ -679,7 +682,7 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs) if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs)
return SBI_EINVAL; return SBI_EINVAL;
event_type = pmu_event_validate(event_idx); event_type = pmu_event_validate(event_idx, event_data);
if (event_type < 0) if (event_type < 0)
return SBI_EINVAL; return SBI_EINVAL;
event_code = get_cidx_code(event_idx); event_code = get_cidx_code(event_idx);
@@ -697,7 +700,8 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
if (event_type == SBI_PMU_EVENT_TYPE_FW) { if (event_type == SBI_PMU_EVENT_TYPE_FW) {
/* Any firmware counter can be used track any firmware event */ /* Any firmware counter can be used track any firmware event */
ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code, hartid); ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code,
hartid, event_data);
} else { } else {
ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx, ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx,
event_data); event_data);
@@ -720,7 +724,7 @@ skip_match:
if (SBI_PMU_FW_MAX <= event_code && if (SBI_PMU_FW_MAX <= event_code &&
pmu_dev && pmu_dev->fw_counter_start) { pmu_dev && pmu_dev->fw_counter_start) {
ret = pmu_dev->fw_counter_start( ret = pmu_dev->fw_counter_start(
ctr_idx - num_hw_ctrs, event_code, ctr_idx - num_hw_ctrs, event_data,
fw_counters_data[hartid][ctr_idx - num_hw_ctrs], fw_counters_data[hartid][ctr_idx - num_hw_ctrs],
true); true);
if (ret) if (ret)