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platform: generic: mips eyeq7h: fix boot with JTAG

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When JTAG is connected, internal logic leads to the bit
MIPS_CTL0_DBG_RST_DASRT (for the debug unit) stay high and
this prevents normal cluster power-up.

Force proper power-on reset value prior to power-up sequence.
Hold this value for about 10 usec

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Link: https://lore.kernel.org/r/20260618103713.2588984-1-vladimir.kondratiev@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Vladimir Kondratiev
2026-06-18 13:37:13 +03:00
committed by Anup Patel
parent a8be5e9478
commit a2077d44cc
1 changed files with 7 additions and 1 deletions
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platform/generic/mips/eyeq7h.c
+7 -1
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@@ -73,7 +73,13 @@ static void eyeq7h_powerup_olb(u32 hartid)
/* Get the MIPS_CM_CTL0 address */ /* Get the MIPS_CM_CTL0 address */
cmd = (volatile void *)(MIPS_OLB_ADDR[cl] + MIPS_CM_CTL0); cmd = (volatile void *)(MIPS_OLB_ADDR[cl] + MIPS_CM_CTL0);
temp = readl(cmd); /* set reset value. Value may be wrong after JTAG debug session */
temp = MIPS_CTL0_CACHE_HW_INIT_INHIBIT |
INSERT_FIELD(0, MIPS_CTL0_DBU_COLD_PWR_UP, 2) |
MIPS_CTL0_DBU_PWR_UP | MIPS_CTL0_CM_PWR_UP;
writel(temp, cmd);
wmb();
sbi_timer_udelay(10);
/* Enable HW cache init */ /* Enable HW cache init */
temp = temp & ~MIPS_CTL0_CACHE_HW_INIT_INHIBIT; temp = temp & ~MIPS_CTL0_CACHE_HW_INIT_INHIBIT;
/* deassert reset */ /* deassert reset */