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lib: utils/hsm: factor out ATCSMU code into an HSM driver

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Refactor ATCSMU (System Management Unit) support by moving it from a
system utility into a dedicated FDT-based HSM driver.

Key changes include:

- Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver
- Moving hart start and stop operations on AE350 platform into the new
  HSM driver
- Converting the assembly-based functions in sleep.S to C code for the
  readability
- Updating the ATCWDT200 driver

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Ben Zong-You Xie
2025-12-29 15:19:10 +08:00
committed by Anup Patel
parent 74434f2558
commit 9ffacc8ae1
16 changed files with 302 additions and 348 deletions
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112
platform/generic/andes/ae350.c
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@@ -1,121 +1,25 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2022 Andes Technology Corporation
*
* Authors:
* Yu Chien Peter Lin <peterlin@andestech.com>
* Copyright (c) 2025 Andes Technology Corporation
*/
#include <platform_override.h>
#include <andes/andes_pmu.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/sys/atcsmu.h>
#include <sbi/riscv_asm.h>
#include <sbi/sbi_bitops.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_hsm.h>
#include <sbi/sbi_ipi.h>
#include <sbi/sbi_init.h>
#include <andes/andes.h>
#include <andes/andes_pmu.h>
#include <andes/andes_sbi.h>
#include <platform_override.h>
#include <sbi_utils/fdt/fdt_helper.h>
static struct smu_data smu = { 0 };
extern void __ae350_enable_coherency_warmboot(void);
extern void __ae350_disable_coherency(void);
extern void _start_warm(void);
static int ae350_hart_start(u32 hartid, ulong saddr)
void ae350_enable_coherency_warmboot(void)
{
u32 hartindex = sbi_hartid_to_hartindex(hartid);
/*
* Don't send wakeup command when:
* 1) boot-time
* 2) the target hart is non-sleepable 25-series hart0
*/
if (!sbi_init_count(hartindex) || (is_andes(25) && hartid == 0))
return sbi_ipi_raw_send(hartindex, false);
/* Write wakeup command to the sleep hart */
smu_set_command(&smu, WAKEUP_CMD, hartid);
return 0;
}
static int ae350_hart_stop(void)
{
int rc;
u32 hartid = current_hartid();
/**
* For Andes AX25MP, the hart0 shares power domain with
* L2-cache, instead of turning it off, it should fall
* through and jump to warmboot_addr.
*/
if (is_andes(25) && hartid == 0)
return SBI_ENOTSUPP;
if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
return SBI_ENOTSUPP;
/**
* disable all events, the current hart will be
* woken up from reset vector when other hart
* writes its PCS (power control slot) control
* register
*/
smu_set_wakeup_events(&smu, 0x0, hartid);
smu_set_command(&smu, DEEP_SLEEP_CMD, hartid);
rc = smu_set_reset_vector(&smu,
(ulong)__ae350_enable_coherency_warmboot,
hartid);
if (rc)
goto fail;
__ae350_disable_coherency();
wfi();
fail:
/* It should never reach here */
sbi_hart_hang();
return 0;
}
static const struct sbi_hsm_device andes_smu = {
.name = "andes_smu",
.hart_start = ae350_hart_start,
.hart_stop = ae350_hart_stop,
};
static void ae350_hsm_device_init(const void *fdt)
{
int rc;
rc = fdt_parse_compat_addr(fdt, (uint64_t *)&smu.addr,
"andestech,atcsmu");
if (!rc) {
sbi_hsm_set_device(&andes_smu);
}
}
static int ae350_final_init(bool cold_boot)
{
if (cold_boot) {
const void *fdt = fdt_get_address();
ae350_hsm_device_init(fdt);
}
return generic_final_init(cold_boot);
ae350_enable_coherency();
_start_warm();
}
static int ae350_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
{
generic_platform_ops.final_init = ae350_final_init;
generic_platform_ops.extensions_init = andes_pmu_extensions_init;
generic_platform_ops.pmu_init = andes_pmu_init;
generic_platform_ops.vendor_ext_provider = andes_sbi_vendor_ext_provider;