lib: sbi: Set the scratch allocation to alignment to cacheline size

Set the scratch allocation alignment to cacheline size specified by
riscv,cbom-block-size in the DTS file to avoid two atomic variables
from the same cache line causing livelock on some platforms. If the
cacheline is not specified, we set it a default value.

Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Raj Vishwanathan
2025-04-23 15:50:45 -07:00
committed by Anup Patel
parent 4d0128ec58
commit 99aabc6b84
5 changed files with 63 additions and 2 deletions

View File

@@ -246,6 +246,30 @@ int fdt_parse_hart_id(const void *fdt, int cpu_offset, u32 *hartid)
return 0;
}
int fdt_parse_cbom_block_size(const void *fdt, int cpu_offset, unsigned long *cbom_block_size)
{
int len;
const void *prop;
const fdt32_t *val;
if (!fdt || cpu_offset < 0)
return SBI_EINVAL;
prop = fdt_getprop(fdt, cpu_offset, "device_type", &len);
if (!prop || !len)
return SBI_EINVAL;
if (strncmp (prop, "cpu", strlen ("cpu")))
return SBI_EINVAL;
val = fdt_getprop(fdt, cpu_offset, "riscv,cbom-block-size", &len);
if (!val || len < sizeof(fdt32_t))
return SBI_EINVAL;
if (cbom_block_size)
*cbom_block_size = fdt32_to_cpu(*val);
return 0;
}
int fdt_parse_max_enabled_hart_id(const void *fdt, u32 *max_hartid)
{
u32 hartid;