Mirrors/opensbi
5
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2025-08-30 09:56:33 +01:00
Code Issues Packages Projects Releases Wiki Activity

platform: generic: thead: separate implement of T-HEAD c9xx pmu

Browse Source 
Separate the implement of T-HEAD c9xx pmu to allow any platform with
c9xx cores can use it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Inochi Amaoto
2023-10-07 11:06:29 +08:00
committed by Anup Patel
parent c1a6987447
commit 8e941e7fe3
6 changed files with 87 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
platform/generic/allwinner/sun20i-d1.c
View File

@@ -6,6 +6,7 @@
#include <platform_override.h>
#include <thead/c9xx_encoding.h>
#include <thead/c9xx_pmu.h>
#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_bitops.h>
@@ -223,58 +224,10 @@ static int sun20i_d1_fdt_fixup(void *fdt, const struct fdt_match *match)
return fdt_add_cpu_idle_states(fdt, sun20i_d1_cpu_idle_states);
}
static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
{
if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
return;
/**
* Clear out the OF bit so that next interrupt can be enabled.
* This should be done before starting interrupt to avoid unexcepted
* overflow interrupt.
*/
csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
/**
* This register is described in C9xx document as the control register
* for enabling writes to the superuser state counter. However, if the
* corresponding bit is not set to 1, scounterof will always read as 0
* when the counter register overflows.
*/
csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
/**
* SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
* while the C9XX has designated enable bits.
* So enable per-counter interrupt on C9xx here.
*/
csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
}
static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
{
/**
* There is no need to clear the bit of mcounterwen, it will expire
* after setting the csr mcountinhibit.
*/
csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
}
static int thead_c9xx_pmu_irq_bit(void)
{
return THEAD_C9XX_MIP_MOIP;
}
const struct sbi_pmu_device thead_c9xx_pmu_device = {
.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
};
static int sun20i_d1_extensions_init(const struct fdt_match *match,
struct sbi_hart_features *hfeatures)
{
sbi_pmu_set_device(&thead_c9xx_pmu_device);
thead_c9xx_register_pmu_device();
/* auto-detection doesn't work on t-head c9xx cores */
/* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */