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treewide: Use conventional names for 32-bit and 64-bit
There are several places in the source tree that have: 32bit, 32 bit, 64bit, 64 bit Fix by using the conventional names with a hyphen. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Anup Patel <anup.patel@wdc.com>
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@@ -37,7 +37,7 @@
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/* Under TileLink */
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#define GPIOHS_BASE_ADDR (0x38001000U)
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/* Under AXI 64 bit */
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/* Under AXI 64-bit */
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#define RAM_BASE_ADDR (0x80000000U)
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#define RAM_SIZE (6 * 1024 * 1024U)
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@@ -59,10 +59,10 @@
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#define ROM_BASE_ADDR (0x88000000U)
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#define ROM_SIZE (128 * 1024U)
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/* Under AHB 32 bit */
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/* Under AHB 32-bit */
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#define DMAC_BASE_ADDR (0x50000000U)
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/* Under APB1 32 bit */
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/* Under APB1 32-bit */
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#define GPIO_BASE_ADDR (0x50200000U)
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#define UART1_BASE_ADDR (0x50210000U)
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#define UART2_BASE_ADDR (0x50220000U)
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@@ -80,7 +80,7 @@
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#define TIMER1_BASE_ADDR (0x502E0000U)
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#define TIMER2_BASE_ADDR (0x502F0000U)
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/* Under APB2 32 bit */
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/* Under APB2 32-bit */
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#define WDT0_BASE_ADDR (0x50400000U)
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#define WDT1_BASE_ADDR (0x50410000U)
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#define OTP_BASE_ADDR (0x50420000U)
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@@ -89,7 +89,7 @@
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#define AES_BASE_ADDR (0x50450000U)
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#define RTC_BASE_ADDR (0x50460000U)
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/* Under APB3 32 bit */
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/* Under APB3 32-bit */
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#define SPI0_BASE_ADDR (0x52000000U)
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#define SPI1_BASE_ADDR (0x53000000U)
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#define SPI3_BASE_ADDR (0x54000000U)
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