mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-25 15:51:41 +01:00
include: Remove ilen member of struct unpriv_trap
We simplify struct unpriv_trap by removing ilen member. This can be achieved by ensuring that at all unpriv load/store instructions are 4 bytes long using GCC assembler option. Additionally, this also reduces few instructions from unpriv load/store functions. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
@@ -15,7 +15,6 @@
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struct sbi_scratch;
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struct sbi_scratch;
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struct unpriv_trap {
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struct unpriv_trap {
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unsigned long ilen;
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unsigned long cause;
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unsigned long cause;
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unsigned long tval;
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unsigned long tval;
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};
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};
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@@ -13,20 +13,22 @@
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_scratch.h>
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#define DEFINE_UNPRIVILEGED_LOAD_FUNCTION(type, insn, insnlen) \
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#define DEFINE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \
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type load_##type(const type *addr, \
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type load_##type(const type *addr, \
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struct sbi_scratch *scratch, \
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struct sbi_scratch *scratch, \
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struct unpriv_trap *trap) \
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struct unpriv_trap *trap) \
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{ \
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{ \
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register ulong __mstatus asm("a2"); \
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register ulong __mstatus asm("a2"); \
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type val = 0; \
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type val = 0; \
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trap->ilen = insnlen; \
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trap->cause = 0; \
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trap->cause = 0; \
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trap->tval = 0; \
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trap->tval = 0; \
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sbi_hart_set_trap_info(scratch, trap); \
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sbi_hart_set_trap_info(scratch, trap); \
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asm volatile( \
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asm volatile( \
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"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
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"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
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".option push\n" \
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".option norvc\n" \
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#insn " %1, %2\n" \
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#insn " %1, %2\n" \
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".option pop\n" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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: "+&r"(__mstatus), "=&r"(val) \
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: "+&r"(__mstatus), "=&r"(val) \
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: "m"(*addr), "r"(MSTATUS_MPRV)); \
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: "m"(*addr), "r"(MSTATUS_MPRV)); \
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@@ -34,41 +36,43 @@
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return val; \
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return val; \
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}
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}
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#define DEFINE_UNPRIVILEGED_STORE_FUNCTION(type, insn, insnlen) \
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#define DEFINE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \
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void store_##type(type *addr, type val, \
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void store_##type(type *addr, type val, \
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struct sbi_scratch *scratch, \
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struct sbi_scratch *scratch, \
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struct unpriv_trap *trap) \
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struct unpriv_trap *trap) \
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{ \
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{ \
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register ulong __mstatus asm("a3"); \
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register ulong __mstatus asm("a3"); \
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trap->ilen = insnlen; \
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trap->cause = 0; \
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trap->cause = 0; \
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trap->tval = 0; \
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trap->tval = 0; \
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sbi_hart_set_trap_info(scratch, trap); \
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sbi_hart_set_trap_info(scratch, trap); \
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asm volatile( \
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asm volatile( \
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"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
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"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
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".option push\n" \
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".option norvc\n" \
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#insn " %1, %2\n" \
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#insn " %1, %2\n" \
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".option pop\n" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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: "+&r"(__mstatus) \
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: "+&r"(__mstatus) \
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: "r"(val), "m"(*addr), "r"(MSTATUS_MPRV)); \
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: "r"(val), "m"(*addr), "r"(MSTATUS_MPRV)); \
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sbi_hart_set_trap_info(scratch, NULL); \
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sbi_hart_set_trap_info(scratch, NULL); \
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}
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}
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u8, sb, 4)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u16, sh, 4)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u32, sw, 2)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
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#if __riscv_xlen == 64
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#if __riscv_xlen == 64
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd, 2)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
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#else
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#else
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
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u64 load_u64(const u64 *addr,
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u64 load_u64(const u64 *addr,
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struct sbi_scratch *scratch, struct unpriv_trap *trap)
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struct sbi_scratch *scratch, struct unpriv_trap *trap)
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@@ -105,7 +109,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
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ulong rvc_mask = 3, tmp;
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ulong rvc_mask = 3, tmp;
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#endif
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#endif
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trap->ilen = 4;
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trap->cause = 0;
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trap->cause = 0;
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trap->tval = 0;
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trap->tval = 0;
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sbi_hart_set_trap_info(scratch, trap);
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sbi_hart_set_trap_info(scratch, trap);
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@@ -115,20 +118,29 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
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#ifndef __riscv_compressed
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#ifndef __riscv_compressed
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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".option push\n"
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".option norvc\n"
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#if __riscv_xlen == 64
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#if __riscv_xlen == 64
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STR(LWU) " %[insn], (%[addr])\n"
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STR(LWU) " %[insn], (%[addr])\n"
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#else
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#else
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STR(LW) " %[insn], (%[addr])\n"
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STR(LW) " %[insn], (%[addr])\n"
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#endif
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#endif
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".option pop\n"
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"csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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"csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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: [mstatus] "+&r"(__mstatus), [insn] "=&r"(val)
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: [mstatus] "+&r"(__mstatus), [insn] "=&r"(val)
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc));
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc));
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#else
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#else
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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".option push\n"
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".option norvc\n"
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"lhu %[insn], (%[addr])\n"
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"lhu %[insn], (%[addr])\n"
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".option pop\n"
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"bne %[tmp], %[rvc_mask], 2f\n"
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"bne %[tmp], %[rvc_mask], 2f\n"
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".option push\n"
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".option norvc\n"
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"lhu %[tmp], 2(%[addr])\n"
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"lhu %[tmp], 2(%[addr])\n"
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".option pop\n"
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"sll %[tmp], %[tmp], 16\n"
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"sll %[tmp], %[tmp], 16\n"
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"add %[insn], %[insn], %[tmp]\n"
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"add %[insn], %[insn], %[tmp]\n"
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"2: csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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"2: csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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@@ -262,7 +262,7 @@ void sbi_trap_handler(struct sbi_trap_regs *regs, struct sbi_scratch *scratch)
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uptrap = sbi_hart_get_trap_info(scratch);
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uptrap = sbi_hart_get_trap_info(scratch);
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if ((regs->mstatus & MSTATUS_MPRV) && uptrap) {
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if ((regs->mstatus & MSTATUS_MPRV) && uptrap) {
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rc = 0;
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rc = 0;
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regs->mepc += uptrap->ilen;
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regs->mepc += 4;
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uptrap->cause = mcause;
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uptrap->cause = mcause;
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uptrap->tval = mtval;
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uptrap->tval = mtval;
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} else {
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} else {
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