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lib: utils/cache: add Andes last level cache controller

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Introduce a FDT-based driver for the Andes Last Level Cache (LLC)
controller to support cache maintenance operations.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Ben Zong-You Xie
2025-12-29 15:19:13 +08:00
committed by Anup Patel
parent 6d26b43c47
commit 82b0961821
6 changed files with 200 additions and 0 deletions
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10
lib/utils/hsm/fdt_hsm_andes_atcsmu.c
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@@ -84,6 +84,16 @@ u32 atcsmu_get_sleep_type(u32 hartid)
return readl_relaxed((char *)atcsmu_base + PCSm_SCRATCH_OFFSET(hartid));
}
void atcsmu_write_scratch(u32 value)
{
writel_relaxed(value, (char *)atcsmu_base + SCRATCH_PAD_OFFSET);
}
u32 atcsmu_read_scratch(void)
{
return readl_relaxed((char *)atcsmu_base + SCRATCH_PAD_OFFSET);
}
static int ae350_hart_start(u32 hartid, ulong saddr)
{
u32 hartindex = sbi_hartid_to_hartindex(hartid);