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lib: utils/cache: add Andes last level cache controller

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Introduce a FDT-based driver for the Andes Last Level Cache (LLC)
controller to support cache maintenance operations.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Ben Zong-You Xie
2025-12-29 15:19:13 +08:00
committed by Anup Patel
parent 6d26b43c47
commit 82b0961821
6 changed files with 200 additions and 0 deletions
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15
include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h
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@@ -11,6 +11,8 @@
/* clang-format off */
#define SCRATCH_PAD_OFFSET 0x40
#define RESET_VEC_LO_OFFSET 0x50
#define RESET_VEC_HI_OFFSET 0x60
#define RESET_VEC_8CORE_OFFSET 0x1a0
@@ -31,6 +33,9 @@
#define PCS0_WE_OFFSET 0x90
#define PCSm_WE_OFFSET(i) ((i + 3) * 0x20 + PCS0_WE_OFFSET)
#define PCS_WAKEUP_RTC_ALARM_MASK BIT(2)
#define PCS_WAKEUP_UART2_MASK BIT(9)
#define PCS_WAKEUP_MSIP_MASK BIT(29)
#define PCS0_CTL_OFFSET 0x94
#define PCSm_CTL_OFFSET(i) ((i + 3) * 0x20 + PCS0_CTL_OFFSET)
@@ -38,6 +43,14 @@
#define WAKEUP_CMD 0x8
#define DEEP_SLEEP_CMD 0xb
#define PCS0_STATUS_OFFSET 0x98
#define PCSm_STATUS_OFFSET(i) ((i + 3) * 0x20 + PCS0_STATUS_OFFSET)
#define PD_TYPE_MASK GENMASK(2, 0)
#define PD_TYPE_SLEEP 2
#define PD_STATUS_MASK GENMASK(7, 3)
#define PD_STATUS_LIGHT_SLEEP 0
#define PD_STATUS_DEEP_SLEEP 0x10
/* clang-format on */
void atcsmu_set_wakeup_events(u32 events, u32 hartid);
@@ -45,5 +58,7 @@ bool atcsmu_support_sleep_mode(u32 sleep_type, u32 hartid);
void atcsmu_set_command(u32 pcs_ctl, u32 hartid);
int atcsmu_set_reset_vector(u64 wakeup_addr, u32 hartid);
u32 atcsmu_get_sleep_type(u32 hartid);
void atcsmu_write_scratch(u32 value);
u32 atcsmu_read_scratch(void);
#endif