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https://github.com/riscv-software-src/opensbi.git
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lib: Move sbi core library to lib/sbi
Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
227
lib/sbi/sbi_tlb.c
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227
lib/sbi/sbi_tlb.c
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_fifo.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_tlb.h>
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#include <plat/string.h>
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static unsigned long ipi_tlb_fifo_off;
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static unsigned long ipi_tlb_fifo_mem_off;
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static inline int __sbi_tlb_fifo_range_check(struct sbi_tlb_info *curr,
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struct sbi_tlb_info *next)
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{
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unsigned long curr_end;
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unsigned long next_end;
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int ret = SBI_FIFO_UNCHANGED;
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if (!curr || !next)
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return ret;
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next_end = next->start + next->size;
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curr_end = curr->start + curr->size;
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if (next->start <= curr->start && next_end > curr_end) {
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curr->start = next->start;
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curr->size = next->size;
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ret = SBI_FIFO_UPDATED;
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} else if (next->start >= curr->start && next_end <= curr_end) {
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ret = SBI_FIFO_SKIP;
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}
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return ret;
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}
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/**
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* Call back to decide if an inplace fifo update is required or next entry can
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* can be skipped. Here are the different cases that are being handled.
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*
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* Case1:
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* if next flush request range lies within one of the existing entry, skip
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* the next entry.
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* Case2:
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* if flush request range in current fifo entry lies within next flush
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* request, update the current entry.
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* Case3:
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if a complete vma flush is requested, then all entries can be deleted
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and new request can be enqueued. This will not be done for ASID case
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as that means we have to iterate again in the fifo to figure out which
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entries belong to that ASID.
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*/
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static int sbi_tlb_fifo_update_cb(void *in, void *data)
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{
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struct sbi_tlb_info *curr;
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struct sbi_tlb_info *next;
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int ret = SBI_FIFO_UNCHANGED;
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if (!in && !!data)
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return ret;
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curr = (struct sbi_tlb_info *)data;
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next = (struct sbi_tlb_info *)in;
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if (next->type == SBI_TLB_FLUSH_VMA_ASID &&
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curr->type == SBI_TLB_FLUSH_VMA_ASID) {
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if (next->asid == curr->asid)
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ret = __sbi_tlb_fifo_range_check(curr, next);
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} else if (next->type == SBI_TLB_FLUSH_VMA &&
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curr->type == SBI_TLB_FLUSH_VMA) {
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if (next->size == SBI_TLB_FLUSH_ALL)
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ret = SBI_FIFO_RESET;
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else
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ret = __sbi_tlb_fifo_range_check(curr, next);
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}
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return ret;
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}
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int sbi_tlb_fifo_update(struct sbi_scratch *scratch, u32 event, void *data)
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{
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int ret;
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struct sbi_fifo *ipi_tlb_fifo;
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struct sbi_tlb_info *tinfo = data;
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ipi_tlb_fifo = sbi_scratch_offset_ptr(scratch,
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ipi_tlb_fifo_off);
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/*
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* If address range to flush is too big then simply
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* upgrade it to flush all because we can only flush
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* 4KB at a time.
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*/
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if (tinfo->size >= SBI_TLB_FLUSH_MAX_SIZE) {
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tinfo->start = 0;
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tinfo->size = SBI_TLB_FLUSH_ALL;
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}
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ret = sbi_fifo_inplace_update(ipi_tlb_fifo, data,
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sbi_tlb_fifo_update_cb);
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if (ret == SBI_FIFO_SKIP || ret == SBI_FIFO_UPDATED) {
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return 1;
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}
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while (sbi_fifo_enqueue(ipi_tlb_fifo, data) < 0) {
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/**
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* For now, Busy loop until there is space in the fifo.
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* There may be case where target hart is also
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* enqueue in source hart's fifo. Both hart may busy
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* loop leading to a deadlock.
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* TODO: Introduce a wait/wakeup event mechansim to handle
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* this properly.
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*/
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__asm__ __volatile("nop");
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__asm__ __volatile("nop");
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}
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return 0;
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}
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static void sbi_tlb_flush_all(void)
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{
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__asm__ __volatile("sfence.vma");
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}
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static void sbi_tlb_fifo_sfence_vma(struct sbi_tlb_info *tinfo)
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{
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unsigned long start = tinfo->start;
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unsigned long size = tinfo->size;
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unsigned long i;
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if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
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sbi_tlb_flush_all();
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return;
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}
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for (i = 0; i < size; i += PAGE_SIZE) {
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__asm__ __volatile__("sfence.vma %0"
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:
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: "r"(start + i)
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: "memory");
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}
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}
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static void sbi_tlb_fifo_sfence_vma_asid(struct sbi_tlb_info *tinfo)
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{
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unsigned long start = tinfo->start;
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unsigned long size = tinfo->size;
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unsigned long asid = tinfo->asid;
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unsigned long i;
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if (start == 0 && size == 0) {
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sbi_tlb_flush_all();
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return;
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}
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/* Flush entire MM context for a given ASID */
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if (size == SBI_TLB_FLUSH_ALL) {
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__asm__ __volatile__("sfence.vma x0, %0"
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:
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: "r"(asid)
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: "memory");
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return;
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}
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for (i = 0; i < size; i += PAGE_SIZE) {
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__asm__ __volatile__("sfence.vma %0, %1"
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:
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: "r"(start + i), "r"(asid)
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: "memory");
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}
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}
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void sbi_tlb_fifo_process(struct sbi_scratch *scratch, u32 event)
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{
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struct sbi_tlb_info tinfo;
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struct sbi_fifo *ipi_tlb_fifo =
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sbi_scratch_offset_ptr(scratch, ipi_tlb_fifo_off);
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while (!sbi_fifo_dequeue(ipi_tlb_fifo, &tinfo)) {
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if (tinfo.type == SBI_TLB_FLUSH_VMA)
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sbi_tlb_fifo_sfence_vma(&tinfo);
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else if (tinfo.type == SBI_TLB_FLUSH_VMA_ASID)
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sbi_tlb_fifo_sfence_vma_asid(&tinfo);
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memset(&tinfo, 0, SBI_TLB_INFO_SIZE);
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}
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}
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int sbi_tlb_fifo_init(struct sbi_scratch *scratch, bool cold_boot)
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{
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void *ipi_tlb_mem;
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struct sbi_fifo *ipi_tlb_q;
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if (cold_boot) {
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ipi_tlb_fifo_off = sbi_scratch_alloc_offset(sizeof(*ipi_tlb_q),
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"IPI_TLB_FIFO");
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if (!ipi_tlb_fifo_off)
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return SBI_ENOMEM;
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ipi_tlb_fifo_mem_off = sbi_scratch_alloc_offset(
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SBI_TLB_FIFO_NUM_ENTRIES * SBI_TLB_INFO_SIZE,
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"IPI_TLB_FIFO_MEM");
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if (!ipi_tlb_fifo_mem_off) {
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sbi_scratch_free_offset(ipi_tlb_fifo_off);
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return SBI_ENOMEM;
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}
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} else {
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if (!ipi_tlb_fifo_off ||
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!ipi_tlb_fifo_mem_off)
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return SBI_ENOMEM;
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}
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ipi_tlb_q = sbi_scratch_offset_ptr(scratch, ipi_tlb_fifo_off);
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ipi_tlb_mem = sbi_scratch_offset_ptr(scratch, ipi_tlb_fifo_mem_off);
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sbi_fifo_init(ipi_tlb_q, ipi_tlb_mem,
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SBI_TLB_FIFO_NUM_ENTRIES, SBI_TLB_INFO_SIZE);
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return 0;
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}
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