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https://github.com/riscv-software-src/opensbi.git
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lib: Move sbi core library to lib/sbi
Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Atish Patra
222
lib/sbi/riscv_atomic.c
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222
lib/sbi/riscv_atomic.c
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/sbi_types.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_atomic.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/sbi_bits.h>
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long atomic_read(atomic_t *atom)
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{
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long ret = atom->counter;
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rmb();
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return ret;
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}
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void atomic_write(atomic_t *atom, long value)
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{
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atom->counter = value;
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wmb();
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}
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long atomic_add_return(atomic_t *atom, long value)
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{
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long ret;
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__asm__ __volatile__(" amoadd.w.aqrl %1, %2, %0"
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: "+A"(atom->counter), "=r"(ret)
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: "r"(value)
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: "memory");
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return ret + value;
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}
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long atomic_sub_return(atomic_t *atom, long value)
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{
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long ret;
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__asm__ __volatile__(" amoadd.w.aqrl %1, %2, %0"
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: "+A"(atom->counter), "=r"(ret)
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: "r"(-value)
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: "memory");
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return ret - value;
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}
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#define __xchg(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__("0: lr.w %0, %2\n" \
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" sc.w.rl %1, %z3, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__("0: lr.d %0, %2\n" \
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" sc.d.rl %1, %z3, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__new) \
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: "memory"); \
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break; \
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default: \
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break; \
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} \
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__ret; \
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})
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#define xchg(ptr, n) \
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({ \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __xchg((ptr), _n_, sizeof(*(ptr))); \
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})
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#define __cmpxchg(ptr, old, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__("0: lr.w %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.w.rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__old), "rJ"(__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__("0: lr.d %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.d.rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__old), "rJ"(__new) \
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: "memory"); \
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break; \
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default: \
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break; \
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} \
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__ret; \
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})
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) \
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__cmpxchg((ptr), _o_, _n_, sizeof(*(ptr))); \
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})
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long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
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{
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#ifdef __riscv_atomic
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return __sync_val_compare_and_swap(&atom->counter, oldval, newval);
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#else
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return cmpxchg(&atom->counter, oldval, newval);
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#endif
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}
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long arch_atomic_xchg(atomic_t *atom, long newval)
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{
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/* Atomically set new value and return old value. */
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#ifdef __riscv_atomic
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/*
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* The name of GCC built-in macro __sync_lock_test_and_set()
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* is misleading. A more appropriate name for GCC built-in
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* macro would be __sync_val_exchange().
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*/
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return __sync_lock_test_and_set(&atom->counter, newval);
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#else
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return xchg(&atom->counter, newval);
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#endif
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}
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unsigned int atomic_raw_xchg_uint(volatile unsigned int *ptr,
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unsigned int newval)
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{
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/* Atomically set new value and return old value. */
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#ifdef __riscv_atomic
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/*
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* The name of GCC built-in macro __sync_lock_test_and_set()
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* is misleading. A more appropriate name for GCC built-in
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* macro would be __sync_val_exchange().
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*/
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return __sync_lock_test_and_set(ptr, newval);
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#else
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return xchg(ptr, newval);
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#endif
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}
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#if (BITS_PER_LONG == 64)
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#define __AMO(op) "amo" #op ".d"
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#elif (BITS_PER_LONG == 32)
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#define __AMO(op) "amo" #op ".w"
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#else
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#error "Unexpected BITS_PER_LONG"
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#endif
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#define __atomic_op_bit_ord(op, mod, nr, addr, ord) \
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({ \
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unsigned long __res, __mask; \
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__mask = BIT_MASK(nr); \
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__asm__ __volatile__(__AMO(op) #ord " %0, %2, %1" \
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: "=r"(__res), "+A"(addr[BIT_WORD(nr)]) \
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: "r"(mod(__mask)) \
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: "memory"); \
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__res; \
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})
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#define __atomic_op_bit(op, mod, nr, addr) \
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__atomic_op_bit_ord(op, mod, nr, addr, .aqrl)
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/* Bitmask modifiers */
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#define __NOP(x) (x)
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#define __NOT(x) (~(x))
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inline int atomic_raw_set_bit(int nr, volatile unsigned long *addr)
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{
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return __atomic_op_bit(or, __NOP, nr, addr);
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}
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inline int atomic_raw_clear_bit(int nr, volatile unsigned long *addr)
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{
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return __atomic_op_bit(and, __NOT, nr, addr);
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}
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inline int atomic_set_bit(int nr, atomic_t *atom)
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{
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return atomic_raw_set_bit(nr, (unsigned long *)&atom->counter);
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}
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inline int atomic_clear_bit(int nr, atomic_t *atom)
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{
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return atomic_raw_clear_bit(nr, (unsigned long *)&atom->counter);
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}
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