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lib: Use CSR_<FOO> instead of <foo> for csr_*()

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Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.

Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Atish Patra
2019-02-12 18:32:06 -08:00
committed by Anup Patel
parent 4cb4d46875
commit 70a474d2c2
11 changed files with 84 additions and 76 deletions
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8
include/sbi/riscv_encoding.h
View File

@@ -195,10 +195,18 @@
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
#define CSR_USTATUS 0x0
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
#define CSR_FCSR 0x3
#define CSR_CYCLE 0xc00
#define CSR_UIE 0x4
#define CSR_UTVEC 0x5
#define CSR_USCRATCH 0x40
#define CSR_UEPC 0x41
#define CSR_UCAUSE 0x42
#define CSR_UTVAL 0x43
#define CSR_UIP 0x44
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_HPMCOUNTER3 0xc03

12
include/sbi/riscv_fp.h
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@@ -43,12 +43,12 @@
ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
ulong tmp; \
asm volatile ("1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); })
#define GET_FCSR() csr_read(fcsr)
#define SET_FCSR(value) csr_write(fcsr, (value))
#define GET_FRM() csr_read(frm)
#define SET_FRM(value) csr_write(frm, (value))
#define GET_FFLAGS() csr_read(fflags)
#define SET_FFLAGS(value) csr_write(fflags, (value))
#define GET_FCSR() csr_read(CSR_FCSR)
#define SET_FCSR(value) csr_write(CSR_FCSR, (value))
#define GET_FRM() csr_read(CSR_FRM)
#define SET_FRM(value) csr_write(CSR_FRM, (value))
#define GET_FFLAGS() csr_read(CSR_FFLAGS)
#define SET_FFLAGS(value) csr_write(CSR_FFLAGS, (value))
#define SET_FS_DIRTY() ((void) 0)

2
include/sbi/sbi_scratch.h
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@@ -61,7 +61,7 @@ struct sbi_scratch {
/** Get pointer to sbi_scratch for current HART */
#define sbi_scratch_thishart_ptr() \
((struct sbi_scratch *)csr_read(mscratch))
((struct sbi_scratch *)csr_read(CSR_MSCRATCH))
/** Get Arg1 of next booting stage for current HART */
#define sbi_scratch_thishart_arg1_ptr() \

16
include/sbi/sbi_unpriv.h
View File

@@ -20,9 +20,9 @@ static inline type load_##type(const type *addr, ulong mepc) \
register ulong __mepc asm ("a2") = mepc; \
register ulong __mstatus asm ("a3"); \
type val; \
asm ("csrrs %0, mstatus, %3\n" \
asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \
#insn " %1, %2\n" \
"csrw mstatus, %0" \
"csrw "STR(CSR_MSTATUS)", %0" \
: "+&r" (__mstatus), "=&r" (val) \
: "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc)); \
return val; \
@@ -33,9 +33,9 @@ static inline void store_##type(type *addr, type val, ulong mepc) \
{ \
register ulong __mepc asm ("a2") = mepc; \
register ulong __mstatus asm ("a3"); \
asm volatile ("csrrs %0, mstatus, %3\n" \
asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \
#insn " %1, %2\n" \
"csrw mstatus, %0" \
"csrw "STR(CSR_MSTATUS)", %0" \
: "+&r" (__mstatus) \
: "r" (val), "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc)); \
}
@@ -76,18 +76,18 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus)
register ulong __mstatus asm ("a3");
ulong val;
#ifndef __riscv_compressed
asm ("csrrs %[mstatus], mstatus, %[mprv]\n"
asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n"
#if __riscv_xlen == 64
STR(LWU) " %[insn], (%[addr])\n"
#else
STR(LW) " %[insn], (%[addr])\n"
#endif
"csrw mstatus, %[mstatus]"
"csrw "STR(CSR_MSTATUS)", %[mstatus]"
: [mstatus] "+&r" (__mstatus), [insn] "=&r" (val)
: [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc));
#else
ulong rvc_mask = 3, tmp;
asm ("csrrs %[mstatus], mstatus, %[mprv]\n"
asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n"
"and %[tmp], %[addr], 2\n"
"bnez %[tmp], 1f\n"
#if __riscv_xlen == 64
@@ -107,7 +107,7 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus)
"lhu %[tmp], 2(%[addr])\n"
"sll %[tmp], %[tmp], 16\n"
"add %[insn], %[insn], %[tmp]\n"
"2: csrw mstatus, %[mstatus]"
"2: csrw "STR(CSR_MSTATUS)", %[mstatus]"
: [mstatus] "+&r" (__mstatus), [insn] "=&r" (val), [tmp] "=&r" (tmp)
: [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc),
[rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (__riscv_xlen - 16));