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platform: generic: Tenstorrent Atlantis support
Add the Tenstorrent Atlantis as a generic-platform. This initial support enables the single_fw_region option, and verifies and prints HART PMA CSR configuration. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260424062520.238403-1-npiggin@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Nicholas Piggin
committed by
Anup Patel
Anup Patel
parent
1932ee3f0a
commit
6767861c48
@@ -47,6 +47,7 @@ RISC-V Platforms Using Generic Platform
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* **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
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* **Spike** (*[spike.md]*)
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* **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
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* **Tenstorrent Atlantis Platform** (*[tt-atlantis.md]*)
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* **OpenPiton FPGA SoC** (*[fpga-openpiton.md]*)
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* **Ariane FPGA SoC** (*[fpga-ariane.md]*)
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@@ -57,5 +58,6 @@ RISC-V Platforms Using Generic Platform
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[sifive_fu540.md]: sifive_fu540.md
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[spike.md]: spike.md
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[thead-c9xx.md]: thead-c9xx.md
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[tt-atlantis.md]: tt-atlantis.md
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[fpga-openpiton.md]: fpga-openpiton.md
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[fpga-ariane.md]: fpga-ariane.md
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@@ -0,0 +1,35 @@
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Tenstorrent Atlantis Platform
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=============================
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The Tenstorrent Atlantis is an SoC and development board from
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Tenstorrent in partnership with CoreLab Technology. It contains 8 RISC-V
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RVA23 compliant Tenstorrent Ascalon cores with RISC-V AIA, RISC-V IOMMU,
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and a range of devices and IO connectivity.
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To build the platform-specific library and firmware images, provide the
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*PLATFORM=generic* parameter to the top level `make` command.
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Platform Options
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----------------
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The *Tenstorrent Atlantis* platform does not have any platform-specific
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options.
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Building Tenstorrent Atlantis Platform
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--------------------------------------
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The Atlantis Platform is still under development. This section will be
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expanded as firmware and support become available.
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QEMU support is currently being developed and initial support has been
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proposed for upstream. To run QEMU that is patched with 'tt-atlantis'
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machine support, run:
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```
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qemu-system-riscv64 -M tt-atlantis -nographic \
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-bios build/platform/generic/firmware/fw_payload.bin \
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-kernel <linux_build_dir>/Image
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```
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Recent (6.18) Linux/riscv 64-bit defconfig kernels should run the QEMU
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tt-atlantis machine.
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@@ -89,6 +89,11 @@ config PLATFORM_STARFIVE_JH7110
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bool "StarFive JH7110 support"
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default n
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config PLATFORM_TENSTORRENT_ATLANTIS
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bool "Tenstorrent Atlantis support"
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select CPU_TENSTORRENT_ASCALON
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default n
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config PLATFORM_THEAD
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bool "THEAD C9xx support"
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select THEAD_C9XX_ERRATA
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@@ -114,6 +119,7 @@ config PLATFORM_MIPS_P8700_BOSTON
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source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
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source "$(OPENSBI_SRC_DIR)/platform/generic/eswin/Kconfig"
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source "$(OPENSBI_SRC_DIR)/platform/generic/tenstorrent/Kconfig"
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source "$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig"
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endif
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@@ -10,6 +10,7 @@ CONFIG_PLATFORM_SIFIVE_FU540=y
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CONFIG_PLATFORM_SIFIVE_FU740=y
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CONFIG_PLATFORM_SOPHGO_SG2042=y
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CONFIG_PLATFORM_STARFIVE_JH7110=y
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CONFIG_PLATFORM_TENSTORRENT_ATLANTIS=y
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CONFIG_PLATFORM_THEAD=y
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CONFIG_PLATFORM_MIPS_P8700_EYEQ7H=y
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CONFIG_PLATFORM_MIPS_P8700_BOSTON=y
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@@ -0,0 +1,12 @@
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/*
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* SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#ifndef __TENSTORRENT_ASCALON_H__
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#define __TENSTORRENT_ASCALON_H__
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void tt_ascalon_discover_pmas_from_boot_hart(void);
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void tt_ascalon_verify_pmas_nonboot_hart(void);
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#endif
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@@ -0,0 +1,17 @@
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/*
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* SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#ifndef __TENSTORRENT_PMA_H__
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#define __TENSTORRENT_PMA_H__
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/* Max number of PMAs for devices (CPU, IOMMU) for Tenstorrent platforms. */
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#define TT_MAX_PMAS 32
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u64 tt_pma_get(unsigned int n);
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void tt_pma_set(unsigned int n, u64 pma);
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bool tt_pma_validate(unsigned int i, u64 pma);
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void tt_pma_print(unsigned int i, u64 pma);
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#endif
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@@ -0,0 +1,5 @@
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# SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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# SPDX-License-Identifier: BSD-2-Clause
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config CPU_TENSTORRENT_ASCALON
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bool
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@@ -0,0 +1,53 @@
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/*
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* SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_csr_detect.h>
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#include <tenstorrent/ascalon.h>
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#include <tenstorrent/pma.h>
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#define CSR_PMACFG0 0x7e0
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void tt_ascalon_discover_pmas_from_boot_hart(void)
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{
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struct sbi_trap_info trap = {0};
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/* Whisper virtual platform does not implement PMA */
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csr_read_allowed(CSR_PMACFG0, &trap);
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if (trap.cause)
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return;
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for (unsigned int i = 0; i < TT_MAX_PMAS; i++) {
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u64 pma = csr_read_num(CSR_PMACFG0 + i);
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if (!tt_pma_validate(i, pma)) {
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sbi_printf("HART%d: Bad boot PMA%02d 0x%016lx\n",
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current_hartid(), i, pma);
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}
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tt_pma_set(i, pma);
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if (pma)
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tt_pma_print(i, pma);
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}
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}
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void tt_ascalon_verify_pmas_nonboot_hart(void)
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{
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struct sbi_trap_info trap = {0};
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/* Whisper virtual platform does not implement PMA */
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csr_read_allowed(CSR_PMACFG0, &trap);
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if (trap.cause)
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return;
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for (unsigned int i = 0; i < TT_MAX_PMAS; i++) {
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u64 pma = csr_read_num(CSR_PMACFG0 + i);
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if (pma != tt_pma_get(i)) {
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sbi_printf("HART%d: Bad boot PMA%02d 0x%016lx does not match boot HART\n",
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current_hartid(), i, pma);
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}
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}
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}
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@@ -0,0 +1,50 @@
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/*
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* SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <platform_override.h>
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#include <libfdt.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_system.h>
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#include <sbi/sbi_console.h>
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#include <tenstorrent/ascalon.h>
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#include <tenstorrent/pma.h>
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static int tt_atlantis_final_init(bool cold_boot)
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{
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if (cold_boot) {
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/* Boot firmware sets HART PMAs. Read and verify them. */
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tt_ascalon_discover_pmas_from_boot_hart();
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} else {
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/* Verify nonboot HARTs have PMAs matching boot HART */
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tt_ascalon_verify_pmas_nonboot_hart();
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}
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return generic_final_init(cold_boot);
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}
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static bool tt_atlantis_single_fw_region(void)
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{
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return true;
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}
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static int tt_atlantis_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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generic_platform_ops.final_init = tt_atlantis_final_init;
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generic_platform_ops.single_fw_region = tt_atlantis_single_fw_region;
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return 0;
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}
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static const struct fdt_match tt_atlantis_match[] = {
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{ .compatible = "tenstorrent,atlantis" },
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{ },
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};
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const struct fdt_driver tenstorrent_atlantis = {
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.match_table = tt_atlantis_match,
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.init = tt_atlantis_platform_init,
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};
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@@ -0,0 +1,12 @@
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#
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# SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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# SPDX-License-Identifier: BSD-2-Clause
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#
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ifeq ($(PLATFORM_RISCV_XLEN), 64)
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platform-objs-y += tenstorrent/pma.o
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platform-objs-$(CONFIG_CPU_TENSTORRENT_ASCALON) += tenstorrent/ascalon.o
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carray-platform_override_modules-$(CONFIG_PLATFORM_TENSTORRENT_ATLANTIS) += tenstorrent_atlantis
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platform-objs-$(CONFIG_PLATFORM_TENSTORRENT_ATLANTIS) += tenstorrent/atlantis.o
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endif
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@@ -0,0 +1,138 @@
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/*
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* SPDX-FileCopyrightText: (c) 2025-2026 Tenstorrent USA, Inc.
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_math.h>
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#include <libfdt.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <tenstorrent/pma.h>
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/*
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* All PMAs in the system should be the same (after boot). The init code
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* must have set PMAs for all HARTs.
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*/
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/*
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* Ascalon CPU and IOMMU PMA layout:
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* Field
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* [2:0] Permission [0] Read, [1] Write, [2] Execute
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* [4:3] Memory type 00: Main memory, 01: IO memory relaxed,
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* 10: IO memory channel 0, 11: IO memory channel 1
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* [6:5] AMO type 00: AMONone, 01: AMOSwap,
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* 10: AMOLogical, 11: AMOArithmetic
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* [7] Cacheability (main memory type)
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* 1: Cacheable, 0: Non-cacheable
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* Combining Capability (IO memory type)
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* 1: Combining allowed, 0: Combining disallowed
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* [8] Routing (coherency)
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* 1: Coherent network, 0: Non-coherent network
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* [11:9] Reserved
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* [51:12] Physical address [51:12] base
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* [63:58] Size log 2 (number of address LSB to ignore when matching)
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* 0 = invalid entry (no match)
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*/
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#define PMA_PERMISSION_R 0x1
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#define PMA_PERMISSION_W 0x2
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#define PMA_PERMISSION_X 0x4
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#define PMA_PERMISSION_MASK 0x7
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#define PMA_TYPE_MAIN_MEMORY 0x0
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#define PMA_TYPE_IO_RELAXED 0x8
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#define PMA_TYPE_IO_ORDERED_0 0x10
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#define PMA_TYPE_IO_ORDERED_1 0x18
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#define PMA_TYPE_MASK 0x18
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#define PMA_AMO_NONE 0x0
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#define PMA_AMO_SWAP 0x20
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#define PMA_AMO_LOGICAL 0x40
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#define PMA_AMO_ARITHMETIC 0x60
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#define PMA_AMO_MASK 0x60
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#define PMA_MEMORY_CACHEABLE 0x80
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#define PMA_IO_COMBINING 0x80
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#define PMA_ROUTING_COHERENT 0x100
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#define PMA_FLAGS_MASK 0x00000000000001ffULL
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#define PMA_ADDRESS_MASK 0x000ffffffffff000ULL
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#define PMA_SIZE_MASK 0xfc00000000000000ULL
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#define PMA_RESERVED_MASK 0x0300000000000e00ULL
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#define PMA_SIZE_SHIFT 58
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static u64 tt_pma_size(u64 pma)
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{
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if ((pma & PMA_SIZE_MASK) == 0)
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return 0;
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return 1ULL << ((pma & PMA_SIZE_MASK) >> PMA_SIZE_SHIFT);
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}
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static u64 tt_pma_address(u64 pma)
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{
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return (pma & PMA_ADDRESS_MASK) & ~((tt_pma_size(pma) - 1));
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}
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bool tt_pma_validate(unsigned int i, u64 pma)
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{
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if (!pma)
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return true;
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if (pma & PMA_RESERVED_MASK) {
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sbi_printf("PMA%02u 0x%016lx contains reserved bits\n", i, pma);
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return false;
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}
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if (tt_pma_size(pma) < 4096) {
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sbi_printf("PMA%02u 0x%016lx size < 4KB\n", i, pma);
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return false;
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}
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if (tt_pma_address(pma) != (pma & PMA_ADDRESS_MASK)) {
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sbi_printf("PMA%02u 0x%016lx address is not aligned to size\n", i, pma);
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return false;
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}
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return true;
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}
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void tt_pma_print(unsigned int i, u64 pma)
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{
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sbi_printf("PMA%02d : 0x%016lx-0x%016lx perm:%s%s%s type:%s %s %s amo:%s\n", i,
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tt_pma_address(pma), tt_pma_address(pma) + tt_pma_size(pma) - 1,
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pma & PMA_PERMISSION_R ? "R" : " ",
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pma & PMA_PERMISSION_W ? "W" : " ",
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pma & PMA_PERMISSION_X ? "X" : " ",
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(pma & PMA_TYPE_MASK) == PMA_TYPE_MAIN_MEMORY ? "main-memory" :
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((pma & PMA_TYPE_MASK) == PMA_TYPE_IO_RELAXED ? "io-relaxed" :
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((pma & PMA_TYPE_MASK) == PMA_TYPE_IO_ORDERED_0 ? "io-ordered-0" : "io-ordered-1")),
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(pma & PMA_TYPE_MASK) == PMA_TYPE_MAIN_MEMORY ?
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(pma & PMA_MEMORY_CACHEABLE ? "cacheable" : "non-cacheable") :
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(pma & PMA_IO_COMBINING ? "combining" : "non-combining"),
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pma & PMA_ROUTING_COHERENT ? "coherent" : "non-coherent",
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(pma & PMA_AMO_MASK) == PMA_AMO_NONE ? "none" :
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((pma & PMA_AMO_MASK) == PMA_AMO_SWAP ? "swap" :
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((pma & PMA_AMO_MASK) == PMA_AMO_LOGICAL ? "logical" : "arithmetic")));
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}
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static u64 pmas[TT_MAX_PMAS];
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void tt_pma_set(unsigned int n, u64 pma)
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{
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if (n >= TT_MAX_PMAS)
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sbi_panic("PMA exceeded TT_MAX_PMAS");
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pmas[n] = pma;
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}
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u64 tt_pma_get(unsigned int n)
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{
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if (n >= TT_MAX_PMAS)
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sbi_panic("PMA exceeded TT_MAX_PMAS");
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return pmas[n];
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}
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