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lib: Rename unprivileged trap handler

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Unprivileged trap handler can be reused for any cases where the executing
code expects a trap.

Rename it to "expected" trap handler as it will be used in other cases in
future.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Atish Patra
2020-05-09 16:47:23 -07:00
committed by Anup Patel
parent 7be75f519f
commit 63a513edec
5 changed files with 17 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/sbi/sbi_hart.h
View File

@@ -16,10 +16,10 @@ struct sbi_scratch;
int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
extern void (*sbi_hart_unpriv_trap)(void);
static inline ulong sbi_hart_unpriv_trap_addr(void)
extern void (*sbi_hart_expected_trap)(void);
static inline ulong sbi_hart_expected_trap_addr(void)
{
return (ulong)sbi_hart_unpriv_trap;
return (ulong)sbi_hart_expected_trap;
}
void sbi_hart_delegation_dump(struct sbi_scratch *scratch);

2
lib/sbi/objects.mk
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@@ -37,4 +37,4 @@ libsbi-objs-y += sbi_timer.o
libsbi-objs-y += sbi_tlb.o
libsbi-objs-y += sbi_trap.o
libsbi-objs-y += sbi_unpriv.o
libsbi-objs-y += sbi_unpriv_trap.o
libsbi-objs-y += sbi_expected_trap.o

12
lib/sbi/sbi_unpriv_trap.S → lib/sbi/sbi_expected_trap.S
View File

@@ -11,8 +11,8 @@
#include <sbi/sbi_trap.h>
/*
* We assume that faulting unpriv load/store instruction is
* is 4-byte long and blindly increment SEPC by 4.
* We assume that faulting instruction is is 4-byte long and blindly
* increment SEPC by 4.
*
* The trap info will be saved as follows:
* A3 <- pointer struct sbi_trap_info
@@ -20,8 +20,8 @@
*/
.align 3
.global __sbi_unpriv_trap
__sbi_unpriv_trap:
.global __sbi_expected_trap
__sbi_expected_trap:
/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
csrr a4, CSR_MEPC
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
@@ -37,8 +37,8 @@ __sbi_unpriv_trap:
mret
.align 3
.global __sbi_unpriv_trap_hext
__sbi_unpriv_trap_hext:
.global __sbi_expected_trap_hext
__sbi_expected_trap_hext:
/* With H-extension so, MTVAL2 and MTINST CSRs available */
csrr a4, CSR_MEPC
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)

8
lib/sbi/sbi_hart.c
View File

@@ -17,10 +17,10 @@
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
extern void __sbi_unpriv_trap(void);
extern void __sbi_unpriv_trap_hext(void);
extern void __sbi_expected_trap(void);
extern void __sbi_expected_trap_hext(void);
void (*sbi_hart_unpriv_trap)(void) = &__sbi_unpriv_trap;
void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
{
@@ -227,7 +227,7 @@ int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
if (cold_boot) {
if (misa_extension('H'))
sbi_hart_unpriv_trap = &__sbi_unpriv_trap_hext;
sbi_hart_expected_trap = &__sbi_expected_trap_hext;
}
mstatus_init(scratch, hartid);

6
lib/sbi/sbi_unpriv.c
View File

@@ -21,7 +21,7 @@
register ulong tinfo asm("a3"); \
register ulong ttmp asm("a4"); \
register ulong mstatus asm("a5"); \
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
type ret = 0; \
trap->cause = 0; \
asm volatile( \
@@ -51,7 +51,7 @@
register ulong tinfo asm("a3"); \
register ulong ttmp asm("a4"); \
register ulong mstatus asm("a5"); \
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
trap->cause = 0; \
asm volatile( \
"add %[tinfo], %[taddr], zero\n" \
@@ -120,7 +120,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
register ulong tinfo asm("a3");
register ulong ttmp asm("a4");
register ulong mstatus asm("a5");
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr();
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr();
ulong insn = 0;
trap->cause = 0;