mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 15:31:22 +01:00
lib: Rename unprivileged trap handler
Unprivileged trap handler can be reused for any cases where the executing code expects a trap. Rename it to "expected" trap handler as it will be used in other cases in future. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
@@ -16,10 +16,10 @@ struct sbi_scratch;
|
|||||||
|
|
||||||
int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
|
int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
|
||||||
|
|
||||||
extern void (*sbi_hart_unpriv_trap)(void);
|
extern void (*sbi_hart_expected_trap)(void);
|
||||||
static inline ulong sbi_hart_unpriv_trap_addr(void)
|
static inline ulong sbi_hart_expected_trap_addr(void)
|
||||||
{
|
{
|
||||||
return (ulong)sbi_hart_unpriv_trap;
|
return (ulong)sbi_hart_expected_trap;
|
||||||
}
|
}
|
||||||
|
|
||||||
void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
|
void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
|
||||||
|
@@ -37,4 +37,4 @@ libsbi-objs-y += sbi_timer.o
|
|||||||
libsbi-objs-y += sbi_tlb.o
|
libsbi-objs-y += sbi_tlb.o
|
||||||
libsbi-objs-y += sbi_trap.o
|
libsbi-objs-y += sbi_trap.o
|
||||||
libsbi-objs-y += sbi_unpriv.o
|
libsbi-objs-y += sbi_unpriv.o
|
||||||
libsbi-objs-y += sbi_unpriv_trap.o
|
libsbi-objs-y += sbi_expected_trap.o
|
||||||
|
@@ -11,8 +11,8 @@
|
|||||||
#include <sbi/sbi_trap.h>
|
#include <sbi/sbi_trap.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* We assume that faulting unpriv load/store instruction is
|
* We assume that faulting instruction is is 4-byte long and blindly
|
||||||
* is 4-byte long and blindly increment SEPC by 4.
|
* increment SEPC by 4.
|
||||||
*
|
*
|
||||||
* The trap info will be saved as follows:
|
* The trap info will be saved as follows:
|
||||||
* A3 <- pointer struct sbi_trap_info
|
* A3 <- pointer struct sbi_trap_info
|
||||||
@@ -20,8 +20,8 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
.align 3
|
.align 3
|
||||||
.global __sbi_unpriv_trap
|
.global __sbi_expected_trap
|
||||||
__sbi_unpriv_trap:
|
__sbi_expected_trap:
|
||||||
/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
|
/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
|
||||||
csrr a4, CSR_MEPC
|
csrr a4, CSR_MEPC
|
||||||
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
|
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
|
||||||
@@ -37,8 +37,8 @@ __sbi_unpriv_trap:
|
|||||||
mret
|
mret
|
||||||
|
|
||||||
.align 3
|
.align 3
|
||||||
.global __sbi_unpriv_trap_hext
|
.global __sbi_expected_trap_hext
|
||||||
__sbi_unpriv_trap_hext:
|
__sbi_expected_trap_hext:
|
||||||
/* With H-extension so, MTVAL2 and MTINST CSRs available */
|
/* With H-extension so, MTVAL2 and MTINST CSRs available */
|
||||||
csrr a4, CSR_MEPC
|
csrr a4, CSR_MEPC
|
||||||
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
|
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
|
@@ -17,10 +17,10 @@
|
|||||||
#include <sbi/sbi_hart.h>
|
#include <sbi/sbi_hart.h>
|
||||||
#include <sbi/sbi_platform.h>
|
#include <sbi/sbi_platform.h>
|
||||||
|
|
||||||
extern void __sbi_unpriv_trap(void);
|
extern void __sbi_expected_trap(void);
|
||||||
extern void __sbi_unpriv_trap_hext(void);
|
extern void __sbi_expected_trap_hext(void);
|
||||||
|
|
||||||
void (*sbi_hart_unpriv_trap)(void) = &__sbi_unpriv_trap;
|
void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
|
||||||
|
|
||||||
static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
|
static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
|
||||||
{
|
{
|
||||||
@@ -227,7 +227,7 @@ int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
|
|||||||
|
|
||||||
if (cold_boot) {
|
if (cold_boot) {
|
||||||
if (misa_extension('H'))
|
if (misa_extension('H'))
|
||||||
sbi_hart_unpriv_trap = &__sbi_unpriv_trap_hext;
|
sbi_hart_expected_trap = &__sbi_expected_trap_hext;
|
||||||
}
|
}
|
||||||
|
|
||||||
mstatus_init(scratch, hartid);
|
mstatus_init(scratch, hartid);
|
||||||
|
@@ -21,7 +21,7 @@
|
|||||||
register ulong tinfo asm("a3"); \
|
register ulong tinfo asm("a3"); \
|
||||||
register ulong ttmp asm("a4"); \
|
register ulong ttmp asm("a4"); \
|
||||||
register ulong mstatus asm("a5"); \
|
register ulong mstatus asm("a5"); \
|
||||||
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
|
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
|
||||||
type ret = 0; \
|
type ret = 0; \
|
||||||
trap->cause = 0; \
|
trap->cause = 0; \
|
||||||
asm volatile( \
|
asm volatile( \
|
||||||
@@ -51,7 +51,7 @@
|
|||||||
register ulong tinfo asm("a3"); \
|
register ulong tinfo asm("a3"); \
|
||||||
register ulong ttmp asm("a4"); \
|
register ulong ttmp asm("a4"); \
|
||||||
register ulong mstatus asm("a5"); \
|
register ulong mstatus asm("a5"); \
|
||||||
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
|
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
|
||||||
trap->cause = 0; \
|
trap->cause = 0; \
|
||||||
asm volatile( \
|
asm volatile( \
|
||||||
"add %[tinfo], %[taddr], zero\n" \
|
"add %[tinfo], %[taddr], zero\n" \
|
||||||
@@ -120,7 +120,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
|
|||||||
register ulong tinfo asm("a3");
|
register ulong tinfo asm("a3");
|
||||||
register ulong ttmp asm("a4");
|
register ulong ttmp asm("a4");
|
||||||
register ulong mstatus asm("a5");
|
register ulong mstatus asm("a5");
|
||||||
register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr();
|
register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr();
|
||||||
ulong insn = 0;
|
ulong insn = 0;
|
||||||
|
|
||||||
trap->cause = 0;
|
trap->cause = 0;
|
||||||
|
Reference in New Issue
Block a user