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https://github.com/riscv-software-src/opensbi.git
synced 2025-12-17 04:21:39 +00:00
lib: sbi: Factor-out PMP programming into separate sources
The PMP programming is a significant part of sbi_hart.c so factor-out this into separate sources sbi_hart_pmp.c and sbi_hart_pmp.h for better maintainability. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-6-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
@@ -13,26 +13,21 @@
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#include <sbi/riscv_fp.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_csr_detect.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_hart_protection.h>
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#include <sbi/sbi_math.h>
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#include <sbi/sbi_hart_pmp.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_string.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_hfence.h>
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extern void __sbi_expected_trap(void);
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extern void __sbi_expected_trap_hext(void);
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void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
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static unsigned long hart_features_offset;
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static DECLARE_BITMAP(fw_smepmp_ids, PMP_COUNT);
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static bool fw_smepmp_ids_inited;
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unsigned long hart_features_offset;
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static void mstatus_init(struct sbi_scratch *scratch)
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{
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@@ -277,30 +272,6 @@ unsigned int sbi_hart_mhpm_mask(struct sbi_scratch *scratch)
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return hfeatures->mhpm_mask;
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}
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unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
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{
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struct sbi_hart_features *hfeatures =
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sbi_scratch_offset_ptr(scratch, hart_features_offset);
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return hfeatures->pmp_count;
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}
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unsigned int sbi_hart_pmp_log2gran(struct sbi_scratch *scratch)
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{
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struct sbi_hart_features *hfeatures =
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sbi_scratch_offset_ptr(scratch, hart_features_offset);
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return hfeatures->pmp_log2gran;
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}
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unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
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{
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struct sbi_hart_features *hfeatures =
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sbi_scratch_offset_ptr(scratch, hart_features_offset);
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return hfeatures->pmp_addr_bits;
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}
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unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch)
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{
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struct sbi_hart_features *hfeatures =
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@@ -309,307 +280,6 @@ unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch)
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return hfeatures->mhpm_bits;
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}
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bool sbi_hart_smepmp_is_fw_region(unsigned int pmp_idx)
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{
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if (!fw_smepmp_ids_inited)
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return false;
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return bitmap_test(fw_smepmp_ids, pmp_idx) ? true : false;
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}
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static void sbi_hart_pmp_fence(void)
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{
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/*
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* As per section 3.7.2 of privileged specification v1.12,
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* virtual address translations can be speculatively performed
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* (even before actual access). These, along with PMP traslations,
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* can be cached. This can pose a problem with CPU hotplug
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* and non-retentive suspend scenario because PMP states are
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* not preserved.
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* It is advisable to flush the caching structures under such
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* conditions.
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*/
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if (misa_extension('S')) {
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__asm__ __volatile__("sfence.vma");
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/*
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* If hypervisor mode is supported, flush caching
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* structures in guest mode too.
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*/
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if (misa_extension('H'))
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__sbi_hfence_gvma_all();
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}
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}
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static void sbi_hart_smepmp_set(struct sbi_scratch *scratch,
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struct sbi_domain *dom,
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struct sbi_domain_memregion *reg,
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unsigned int pmp_idx,
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unsigned int pmp_flags,
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unsigned int pmp_log2gran,
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unsigned long pmp_addr_max)
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{
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unsigned long pmp_addr = reg->base >> PMP_SHIFT;
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if (pmp_log2gran <= reg->order && pmp_addr < pmp_addr_max) {
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sbi_platform_pmp_set(sbi_platform_ptr(scratch),
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pmp_idx, reg->flags, pmp_flags,
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reg->base, reg->order);
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pmp_set(pmp_idx, pmp_flags, reg->base, reg->order);
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} else {
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sbi_printf("Can not configure pmp for domain %s because"
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" memory region address 0x%lx or size 0x%lx "
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"is not in range.\n", dom->name, reg->base,
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reg->order);
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}
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}
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static bool is_valid_pmp_idx(unsigned int pmp_count, unsigned int pmp_idx)
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{
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if (pmp_count > pmp_idx)
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return true;
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sbi_printf("error: insufficient PMP entries\n");
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return false;
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}
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static int sbi_hart_smepmp_configure(struct sbi_scratch *scratch)
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{
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struct sbi_domain_memregion *reg;
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struct sbi_domain *dom = sbi_domain_thishart_ptr();
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unsigned int pmp_log2gran, pmp_bits;
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unsigned int pmp_idx, pmp_count;
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unsigned long pmp_addr_max;
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unsigned int pmp_flags;
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pmp_count = sbi_hart_pmp_count(scratch);
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pmp_log2gran = sbi_hart_pmp_log2gran(scratch);
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pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1;
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pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1);
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/*
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* Set the RLB so that, we can write to PMP entries without
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* enforcement even if some entries are locked.
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*/
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csr_set(CSR_MSECCFG, MSECCFG_RLB);
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/* Disable the reserved entry */
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pmp_disable(SBI_SMEPMP_RESV_ENTRY);
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/* Program M-only regions when MML is not set. */
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pmp_idx = 0;
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sbi_domain_for_each_memregion(dom, reg) {
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/* Skip reserved entry */
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if (pmp_idx == SBI_SMEPMP_RESV_ENTRY)
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pmp_idx++;
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if (!is_valid_pmp_idx(pmp_count, pmp_idx))
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return SBI_EFAIL;
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/* Skip shared and SU-only regions */
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if (!SBI_DOMAIN_MEMREGION_M_ONLY_ACCESS(reg->flags)) {
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pmp_idx++;
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continue;
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}
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/*
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* Track firmware PMP entries to preserve them during
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* domain switches. Under SmePMP, M-mode requires
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* explicit PMP entries to access firmware code/data.
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* These entries must remain enabled across domain
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* context switches to prevent M-mode access faults.
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*/
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if (SBI_DOMAIN_MEMREGION_IS_FIRMWARE(reg->flags)) {
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if (fw_smepmp_ids_inited) {
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/* Check inconsistent firmware region */
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if (!sbi_hart_smepmp_is_fw_region(pmp_idx))
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return SBI_EINVAL;
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} else {
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bitmap_set(fw_smepmp_ids, pmp_idx, 1);
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}
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}
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pmp_flags = sbi_domain_get_smepmp_flags(reg);
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sbi_hart_smepmp_set(scratch, dom, reg, pmp_idx++, pmp_flags,
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pmp_log2gran, pmp_addr_max);
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}
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fw_smepmp_ids_inited = true;
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/* Set the MML to enforce new encoding */
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csr_set(CSR_MSECCFG, MSECCFG_MML);
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/* Program shared and SU-only regions */
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pmp_idx = 0;
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sbi_domain_for_each_memregion(dom, reg) {
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/* Skip reserved entry */
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if (pmp_idx == SBI_SMEPMP_RESV_ENTRY)
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pmp_idx++;
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if (!is_valid_pmp_idx(pmp_count, pmp_idx))
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return SBI_EFAIL;
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/* Skip M-only regions */
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if (SBI_DOMAIN_MEMREGION_M_ONLY_ACCESS(reg->flags)) {
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pmp_idx++;
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continue;
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}
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pmp_flags = sbi_domain_get_smepmp_flags(reg);
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sbi_hart_smepmp_set(scratch, dom, reg, pmp_idx++, pmp_flags,
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pmp_log2gran, pmp_addr_max);
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}
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/*
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* All entries are programmed.
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* Keep the RLB bit so that dynamic mappings can be done.
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*/
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sbi_hart_pmp_fence();
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return 0;
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}
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static int sbi_hart_smepmp_map_range(struct sbi_scratch *scratch,
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unsigned long addr, unsigned long size)
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{
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/* shared R/W access for M and S/U mode */
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unsigned int pmp_flags = (PMP_W | PMP_X);
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unsigned long order, base = 0;
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if (is_pmp_entry_mapped(SBI_SMEPMP_RESV_ENTRY))
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return SBI_ENOSPC;
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for (order = MAX(sbi_hart_pmp_log2gran(scratch), log2roundup(size));
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order <= __riscv_xlen; order++) {
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if (order < __riscv_xlen) {
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base = addr & ~((1UL << order) - 1UL);
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if ((base <= addr) &&
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(addr < (base + (1UL << order))) &&
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(base <= (addr + size - 1UL)) &&
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((addr + size - 1UL) < (base + (1UL << order))))
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break;
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} else {
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return SBI_EFAIL;
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}
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}
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sbi_platform_pmp_set(sbi_platform_ptr(scratch), SBI_SMEPMP_RESV_ENTRY,
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SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW,
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pmp_flags, base, order);
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pmp_set(SBI_SMEPMP_RESV_ENTRY, pmp_flags, base, order);
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return SBI_OK;
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}
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static int sbi_hart_smepmp_unmap_range(struct sbi_scratch *scratch,
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unsigned long addr, unsigned long size)
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{
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sbi_platform_pmp_disable(sbi_platform_ptr(scratch), SBI_SMEPMP_RESV_ENTRY);
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return pmp_disable(SBI_SMEPMP_RESV_ENTRY);
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}
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static int sbi_hart_oldpmp_configure(struct sbi_scratch *scratch)
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{
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struct sbi_domain_memregion *reg;
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struct sbi_domain *dom = sbi_domain_thishart_ptr();
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unsigned long pmp_addr, pmp_addr_max;
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unsigned int pmp_log2gran, pmp_bits;
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unsigned int pmp_idx, pmp_count;
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unsigned int pmp_flags;
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pmp_count = sbi_hart_pmp_count(scratch);
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pmp_log2gran = sbi_hart_pmp_log2gran(scratch);
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pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1;
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pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1);
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pmp_idx = 0;
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sbi_domain_for_each_memregion(dom, reg) {
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if (!is_valid_pmp_idx(pmp_count, pmp_idx))
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return SBI_EFAIL;
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pmp_flags = 0;
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/*
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* If permissions are to be enforced for all modes on
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* this region, the lock bit should be set.
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*/
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if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS)
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pmp_flags |= PMP_L;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
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pmp_flags |= PMP_X;
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pmp_addr = reg->base >> PMP_SHIFT;
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if (pmp_log2gran <= reg->order && pmp_addr < pmp_addr_max) {
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sbi_platform_pmp_set(sbi_platform_ptr(scratch),
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pmp_idx, reg->flags, pmp_flags,
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reg->base, reg->order);
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pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
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} else {
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sbi_printf("Can not configure pmp for domain %s because"
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" memory region address 0x%lx or size 0x%lx "
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"is not in range.\n", dom->name, reg->base,
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reg->order);
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}
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}
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sbi_hart_pmp_fence();
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return 0;
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}
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static void sbi_hart_pmp_unconfigure(struct sbi_scratch *scratch)
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{
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int i, pmp_count = sbi_hart_pmp_count(scratch);
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for (i = 0; i < pmp_count; i++) {
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/* Don't revoke firmware access permissions */
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if (sbi_hart_smepmp_is_fw_region(i))
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continue;
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sbi_platform_pmp_disable(sbi_platform_ptr(scratch), i);
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pmp_disable(i);
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}
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}
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static struct sbi_hart_protection pmp_protection = {
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.name = "pmp",
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.rating = 100,
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.configure = sbi_hart_oldpmp_configure,
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.unconfigure = sbi_hart_pmp_unconfigure,
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};
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static struct sbi_hart_protection epmp_protection = {
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.name = "epmp",
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.rating = 200,
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.configure = sbi_hart_smepmp_configure,
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.unconfigure = sbi_hart_pmp_unconfigure,
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.map_range = sbi_hart_smepmp_map_range,
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.unmap_range = sbi_hart_smepmp_unmap_range,
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};
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static int sbi_hart_pmp_init(struct sbi_scratch *scratch)
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{
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int rc;
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if (sbi_hart_pmp_count(scratch)) {
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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rc = sbi_hart_protection_register(&epmp_protection);
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if (rc)
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return rc;
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} else {
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rc = sbi_hart_protection_register(&pmp_protection);
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if (rc)
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return rc;
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}
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}
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return 0;
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}
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int sbi_hart_priv_version(struct sbi_scratch *scratch)
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{
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struct sbi_hart_features *hfeatures =
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