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lib: Allow custom CSRs in csr_read_num() and csr_write_num()

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Some of the platforms use platform specific CSR access functions for
configuring implementation specific CSRs (such as PMA registers).

Extend the common csr_read_num() and csr_write_num() to allow custom
CSRs so that platform specific CSR access functions are not needed.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
2025-09-30 21:02:16 +05:30
committed by Anup Patel
parent 3990c8ee07
commit 55296fd27c
4 changed files with 127 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

76
platform/generic/mips/p8700.c
View File

@@ -18,78 +18,6 @@
extern void mips_warm_boot(void);
static unsigned long mips_csr_read_num(int csr_num)
{
#define switchcase_csr_read(__csr_num, __val) \
case __csr_num: \
__val = csr_read(__csr_num); \
break;
#define switchcase_csr_read_2(__csr_num, __val) \
switchcase_csr_read(__csr_num + 0, __val) \
switchcase_csr_read(__csr_num + 1, __val)
#define switchcase_csr_read_4(__csr_num, __val) \
switchcase_csr_read_2(__csr_num + 0, __val) \
switchcase_csr_read_2(__csr_num + 2, __val)
#define switchcase_csr_read_8(__csr_num, __val) \
switchcase_csr_read_4(__csr_num + 0, __val) \
switchcase_csr_read_4(__csr_num + 4, __val)
#define switchcase_csr_read_16(__csr_num, __val) \
switchcase_csr_read_8(__csr_num + 0, __val) \
switchcase_csr_read_8(__csr_num + 8, __val)
unsigned long ret = 0;
switch(csr_num) {
switchcase_csr_read_16(CSR_MIPSPMACFG0, ret)
default:
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
break;
}
return ret;
#undef switchcase_csr_read_16
#undef switchcase_csr_read_8
#undef switchcase_csr_read_4
#undef switchcase_csr_read_2
#undef switchcase_csr_read
}
static void mips_csr_write_num(int csr_num, unsigned long val)
{
#define switchcase_csr_write(__csr_num, __val) \
case __csr_num: \
csr_write(__csr_num, __val); \
break;
#define switchcase_csr_write_2(__csr_num, __val) \
switchcase_csr_write(__csr_num + 0, __val) \
switchcase_csr_write(__csr_num + 1, __val)
#define switchcase_csr_write_4(__csr_num, __val) \
switchcase_csr_write_2(__csr_num + 0, __val) \
switchcase_csr_write_2(__csr_num + 2, __val)
#define switchcase_csr_write_8(__csr_num, __val) \
switchcase_csr_write_4(__csr_num + 0, __val) \
switchcase_csr_write_4(__csr_num + 4, __val)
#define switchcase_csr_write_16(__csr_num, __val) \
switchcase_csr_write_8(__csr_num + 0, __val) \
switchcase_csr_write_8(__csr_num + 8, __val)
switch(csr_num) {
switchcase_csr_write_16(CSR_MIPSPMACFG0, val)
default:
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
break;
}
#undef switchcase_csr_write_16
#undef switchcase_csr_write_8
#undef switchcase_csr_write_4
#undef switchcase_csr_write_2
#undef switchcase_csr_write
}
static void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
unsigned long prot, unsigned long addr,
unsigned long log2len)
@@ -103,11 +31,11 @@ static void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
cfgmask = ~(0xffUL << pmacfg_shift);
/* Read pmacfg to change cacheability */
pmacfg = (mips_csr_read_num(pmacfg_csr) & cfgmask);
pmacfg = (csr_read_num(pmacfg_csr) & cfgmask);
cca = (flags & SBI_DOMAIN_MEMREGION_MMIO) ? CCA_CACHE_DISABLE :
CCA_CACHE_ENABLE | PMA_SPECULATION;
pmacfg |= ((cca << pmacfg_shift) & ~cfgmask);
mips_csr_write_num(pmacfg_csr, pmacfg);
csr_write_num(pmacfg_csr, pmacfg);
}
#if CLUSTERS_IN_PLATFORM > 1