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lib: Allow custom CSRs in csr_read_num() and csr_write_num()

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Some of the platforms use platform specific CSR access functions for
configuring implementation specific CSRs (such as PMA registers).

Extend the common csr_read_num() and csr_write_num() to allow custom
CSRs so that platform specific CSR access functions are not needed.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
2025-09-30 21:02:16 +05:30
committed by Anup Patel
parent 3990c8ee07
commit 55296fd27c
4 changed files with 127 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

135
lib/sbi/riscv_asm.c
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@@ -93,77 +93,91 @@ void misa_string(int xlen, char *out, unsigned int out_sz)
unsigned long csr_read_num(int csr_num)
{
#define switchcase_csr_read(__csr_num, __val) \
#define switchcase_csr_read(__csr_num) \
case __csr_num: \
__val = csr_read(__csr_num); \
break;
#define switchcase_csr_read_2(__csr_num, __val) \
switchcase_csr_read(__csr_num + 0, __val) \
switchcase_csr_read(__csr_num + 1, __val)
#define switchcase_csr_read_4(__csr_num, __val) \
switchcase_csr_read_2(__csr_num + 0, __val) \
switchcase_csr_read_2(__csr_num + 2, __val)
#define switchcase_csr_read_8(__csr_num, __val) \
switchcase_csr_read_4(__csr_num + 0, __val) \
switchcase_csr_read_4(__csr_num + 4, __val)
#define switchcase_csr_read_16(__csr_num, __val) \
switchcase_csr_read_8(__csr_num + 0, __val) \
switchcase_csr_read_8(__csr_num + 8, __val)
#define switchcase_csr_read_32(__csr_num, __val) \
switchcase_csr_read_16(__csr_num + 0, __val) \
switchcase_csr_read_16(__csr_num + 16, __val)
#define switchcase_csr_read_64(__csr_num, __val) \
switchcase_csr_read_32(__csr_num + 0, __val) \
switchcase_csr_read_32(__csr_num + 32, __val)
unsigned long ret = 0;
return csr_read(__csr_num);
#define switchcase_csr_read_2(__csr_num) \
switchcase_csr_read(__csr_num + 0) \
switchcase_csr_read(__csr_num + 1)
#define switchcase_csr_read_4(__csr_num) \
switchcase_csr_read_2(__csr_num + 0) \
switchcase_csr_read_2(__csr_num + 2)
#define switchcase_csr_read_8(__csr_num) \
switchcase_csr_read_4(__csr_num + 0) \
switchcase_csr_read_4(__csr_num + 4)
#define switchcase_csr_read_16(__csr_num) \
switchcase_csr_read_8(__csr_num + 0) \
switchcase_csr_read_8(__csr_num + 8)
#define switchcase_csr_read_32(__csr_num) \
switchcase_csr_read_16(__csr_num + 0) \
switchcase_csr_read_16(__csr_num + 16)
#define switchcase_csr_read_64(__csr_num) \
switchcase_csr_read_32(__csr_num + 0) \
switchcase_csr_read_32(__csr_num + 32)
#define switchcase_csr_read_128(__csr_num) \
switchcase_csr_read_64(__csr_num + 0) \
switchcase_csr_read_64(__csr_num + 64)
#define switchcase_csr_read_256(__csr_num) \
switchcase_csr_read_128(__csr_num + 0) \
switchcase_csr_read_128(__csr_num + 128)
switch (csr_num) {
switchcase_csr_read_16(CSR_PMPCFG0, ret)
switchcase_csr_read_64(CSR_PMPADDR0, ret)
switchcase_csr_read(CSR_MCYCLE, ret)
switchcase_csr_read(CSR_MINSTRET, ret)
switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
switchcase_csr_read(CSR_MCYCLECFG, ret)
switchcase_csr_read(CSR_MINSTRETCFG, ret)
switchcase_csr_read(CSR_MHPMEVENT3, ret)
switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
switchcase_csr_read_16(CSR_PMPCFG0)
switchcase_csr_read_64(CSR_PMPADDR0)
switchcase_csr_read(CSR_MCYCLE)
switchcase_csr_read(CSR_MINSTRET)
switchcase_csr_read(CSR_MHPMCOUNTER3)
switchcase_csr_read_4(CSR_MHPMCOUNTER4)
switchcase_csr_read_8(CSR_MHPMCOUNTER8)
switchcase_csr_read_16(CSR_MHPMCOUNTER16)
switchcase_csr_read(CSR_MCOUNTINHIBIT)
switchcase_csr_read(CSR_MCYCLECFG)
switchcase_csr_read(CSR_MINSTRETCFG)
switchcase_csr_read(CSR_MHPMEVENT3)
switchcase_csr_read_4(CSR_MHPMEVENT4)
switchcase_csr_read_8(CSR_MHPMEVENT8)
switchcase_csr_read_16(CSR_MHPMEVENT16)
#if __riscv_xlen == 32
switchcase_csr_read(CSR_MCYCLEH, ret)
switchcase_csr_read(CSR_MINSTRETH, ret)
switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
switchcase_csr_read(CSR_MCYCLEH)
switchcase_csr_read(CSR_MINSTRETH)
switchcase_csr_read(CSR_MHPMCOUNTER3H)
switchcase_csr_read_4(CSR_MHPMCOUNTER4H)
switchcase_csr_read_8(CSR_MHPMCOUNTER8H)
switchcase_csr_read_16(CSR_MHPMCOUNTER16H)
/**
* The CSR range M[CYCLE, INSTRET]CFGH are available only if smcntrpmf
* extension is present. The caller must ensure that.
*/
switchcase_csr_read(CSR_MCYCLECFGH, ret)
switchcase_csr_read(CSR_MINSTRETCFGH, ret)
switchcase_csr_read(CSR_MCYCLECFGH)
switchcase_csr_read(CSR_MINSTRETCFGH)
/**
* The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
* extension is present. The caller must ensure that.
*/
switchcase_csr_read(CSR_MHPMEVENT3H, ret)
switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
switchcase_csr_read(CSR_MHPMEVENT3H)
switchcase_csr_read_4(CSR_MHPMEVENT4H)
switchcase_csr_read_8(CSR_MHPMEVENT8H)
switchcase_csr_read_16(CSR_MHPMEVENT16H)
#endif
switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE)
switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE)
switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE)
switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE)
default:
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
break;
return 0;
}
return ret;
#undef switchcase_csr_read_256
#undef switchcase_csr_read_128
#undef switchcase_csr_read_64
#undef switchcase_csr_read_32
#undef switchcase_csr_read_16
@@ -197,6 +211,12 @@ void csr_write_num(int csr_num, unsigned long val)
#define switchcase_csr_write_64(__csr_num, __val) \
switchcase_csr_write_32(__csr_num + 0, __val) \
switchcase_csr_write_32(__csr_num + 32, __val)
#define switchcase_csr_write_128(__csr_num, __val) \
switchcase_csr_write_64(__csr_num + 0, __val) \
switchcase_csr_write_64(__csr_num + 64, __val)
#define switchcase_csr_write_256(__csr_num, __val) \
switchcase_csr_write_128(__csr_num + 0, __val) \
switchcase_csr_write_128(__csr_num + 128, __val)
switch (csr_num) {
switchcase_csr_write_16(CSR_PMPCFG0, val)
@@ -228,12 +248,21 @@ void csr_write_num(int csr_num, unsigned long val)
switchcase_csr_write_4(CSR_MHPMEVENT4, val)
switchcase_csr_write_8(CSR_MHPMEVENT8, val)
switchcase_csr_write_16(CSR_MHPMEVENT16, val)
switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val)
default:
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
break;
}
#undef switchcase_csr_write_256
#undef switchcase_csr_write_128
#undef switchcase_csr_write_64
#undef switchcase_csr_write_32
#undef switchcase_csr_write_16