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lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi
To support 64 bit firmware counters on RV32 systems, we implement sbi_pmu_counter_fw_read_hi() which returns the upper 32 bits of the firmware counter value. On RV64 (or higher) systems, this function will always return zero. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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committed by
Anup Patel

parent
1fe8dc9955
commit
51951d9e9a
@@ -101,6 +101,7 @@
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#define SBI_EXT_PMU_COUNTER_START 0x3
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#define SBI_EXT_PMU_COUNTER_START 0x3
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#define SBI_EXT_PMU_COUNTER_STOP 0x4
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#define SBI_EXT_PMU_COUNTER_STOP 0x4
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#define SBI_EXT_PMU_COUNTER_FW_READ 0x5
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#define SBI_EXT_PMU_COUNTER_FW_READ 0x5
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#define SBI_EXT_PMU_COUNTER_FW_READ_HI 0x6
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/** General pmu event codes specified in SBI PMU extension */
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/** General pmu event codes specified in SBI PMU extension */
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enum sbi_pmu_hw_generic_events_t {
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enum sbi_pmu_hw_generic_events_t {
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@@ -54,6 +54,14 @@ static int sbi_ecall_pmu_handler(unsigned long extid, unsigned long funcid,
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ret = sbi_pmu_ctr_fw_read(regs->a0, &temp);
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ret = sbi_pmu_ctr_fw_read(regs->a0, &temp);
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*out_val = temp;
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*out_val = temp;
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break;
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break;
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case SBI_EXT_PMU_COUNTER_FW_READ_HI:
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#if __riscv_xlen == 32
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ret = sbi_pmu_ctr_fw_read(regs->a0, &temp);
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*out_val = temp >> 32;
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#else
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*out_val = 0;
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#endif
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break;
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case SBI_EXT_PMU_COUNTER_START:
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case SBI_EXT_PMU_COUNTER_START:
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#if __riscv_xlen == 32
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#if __riscv_xlen == 32
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