platform: generic: Add Metanoia MT2824 initial support

Add the Metanoia MT2824 as a generic platform. This SoC contains two
AX45MP cores from Andes Technology and uses Andes PMU and vendor-specific
extensions.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260724-mt5824-v3-1-9a7d17d69974@bootlin.com
Signed-off-by: Anup Patel <anup@brainfault.org>

docs/platform/generic.md

@@ -50,6 +50,7 @@ RISC-V Platforms Using Generic Platform
 * **Tenstorrent Atlantis Platform** (*[tt-atlantis.md]*)
 * **OpenPiton FPGA SoC** (*[fpga-openpiton.md]*)
 * **Ariane FPGA SoC** (*[fpga-ariane.md]*)
+* **Metanoia MT2824 SoC** (*[metanoia-mt2824.md]*)
 
 [andes-ae350.md]: andes-ae350.md
 [qemu_virt.md]: qemu_virt.md
@@ -61,3 +62,4 @@ RISC-V Platforms Using Generic Platform
 [tt-atlantis.md]: tt-atlantis.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [fpga-ariane.md]: fpga-ariane.md
+[metanoia-mt2824.md]: metanoia-mt2824.md

docs/platform/metanoia-mt2824.md

@@ -0,0 +1,147 @@
+Metanoia MT2824 SoC Platform
+============================
+The Metanoia MT2824 is a highly integrated 5G System-on-Chip designed
+for O-RAN radio units and small cells. It features two Andes AX45MP
+RISC-V cores. More details about the SoC and its reference platform
+named MT5824 can be found at the following [link][0].
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=generic* parameter to the top level make command.
+
+[0]: https://metanoia-comm.com/products/5g/mt5824/
+
+Platform Options
+----------------
+
+The Metanoia MT2824 platform does not have any platform-specific options.
+
+Building Metanoia MT2824 Platform
+---------------------------------
+
+```
+make PLATFORM=generic
+```
+
+DTS Example: (Metanoia MT2824)
+------------------------------
+
+```
+	compatible = "metanoia,mt2824";
+
+	cpus: cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		timebase-frequency = <20000000>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0x00>;
+			status = "okay";
+			compatible = "andestech,ax45mp", "riscv";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <900000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x100>;
+			i-cache-line-size = <0x40>;
+			i-cache-block-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			d-cache-line-size = <0x40>;
+			d-cache-block-size = <0x40>;
+			next-level-cache = <0x01>;
+
+			cpu0intc: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+			};
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			reg = <0x01>;
+			status = "okay";
+			compatible = "andestech,ax45mp", "riscv";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <900000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x100>;
+			i-cache-line-size = <0x40>;
+			i-cache-block-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			d-cache-line-size = <0x40>;
+			d-cache-block-size = <0x40>;
+			next-level-cache = <0x01>;
+
+			cpu1intc: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+			};
+		};
+	};
+
+	l2c: l2-cache@a000000 {
+		compatible = "andestech,ax45mp-cache", "cache";
+		reg = <0x00 0xa000000 0x00 0x40000>;
+		cache-line-size = <64>;
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		cache-sets = <1024>;
+		cache-unified;
+		interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&plic>;
+	};
+
+	soc: soc {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		ranges;
+
+		plic: interrupt-controller@c000000 {
+			compatible = "metanoia,mt2824-plic", "andestech,nceplic100";
+			reg = <0x0 0x0c000000 0x0 0x400000>;
+			interrupts-extended =
+				<&cpu0intc 0x0b>,
+				<&cpu0intc 0x09>,
+				<&cpu1intc 0x0b>,
+				<&cpu1intc 0x09>;
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x02>;
+			riscv,ndev = <0x47>;
+		};
+
+		plicsw: interrupt-controller@c800000 {
+			compatible = "metanoia,mt2824-plicsw", "andestech,plicsw";
+			reg = <0x00 0x0c800000 0x00 0x400000>;
+			interrupts-extended =
+				<&cpu0intc IRQ_TYPE_EDGE_BOTH>,
+				<&cpu1intc IRQ_TYPE_EDGE_BOTH>;
+		};
+
+		plmt0@c400000 {
+			compatible = "metanoia,mt2824-plmt", "andestech,plmt0";
+			reg = <0x0 0x0c400000 0x0 0x00400000>;
+			interrupts-extended =
+				<&cpu0intc 0x07>,
+				<&cpu1intc 0x07>;
+		};
+
+		reboot: reboot@10000004 {
+			compatible = "metanoia,mt2824-reboot";
+			reg = <0x0 0x10000004 0x0 0x08>;
+		};
+	};
+```

platform/generic/Kconfig

@@ -51,6 +51,13 @@ config PLATFORM_ESWIN_EIC770X
 	bool "ESWIN EIC770X support"
 	default n
 
+config PLATFORM_METANOIA_MT2824
+	bool "Metanoia MT2824 support"
+	select ANDES_PMA
+	select ANDES_SBI
+	select ANDES_PMU
+	default n
+
 config PLATFORM_OPENHWGROUP_OPENPITON
 	bool "OpenHWGroup Openpiton support"
 	default n

platform/generic/configs/defconfig

@@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
 CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_ANDES_QILAI=y
 CONFIG_PLATFORM_ESWIN_EIC770X=y
+CONFIG_PLATFORM_METANOIA_MT2824=y
 CONFIG_PLATFORM_OPENHWGROUP_ARIANE=y
 CONFIG_PLATFORM_OPENHWGROUP_OPENPITON=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y

platform/generic/metanoia/mt2824/mt2824.c

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2026 Metanoia Communication Inc.
+ *
+ * Authors:
+ *      Jun Chang <jun.chang@metanoia-comm.com>
+ */
+
+#include <andes/andes_pmu.h>
+#include <andes/andes_sbi.h>
+#include <platform_override.h>
+
+static int metanoia_mt2824_platform_init(const void *fdt, int nodeoff,
+					const struct fdt_match *match)
+{
+	generic_platform_ops.extensions_init = andes_pmu_extensions_init;
+	generic_platform_ops.pmu_init = andes_pmu_init;
+	generic_platform_ops.vendor_ext_provider = andes_sbi_vendor_ext_provider;
+
+	return 0;
+}
+
+static const struct fdt_match metanoia_mt2824_match[] = {
+	{ .compatible = "metanoia,mt2824" },
+	{ /* sentinel */ }
+};
+
+const struct fdt_driver metanoia_mt2824 = {
+	.match_table = metanoia_mt2824_match,
+	.init = metanoia_mt2824_platform_init,
+};

platform/generic/metanoia/mt2824/objects.mk

@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2026 Metanoia Communication Inc.
+#
+
+ifeq ($(PLATFORM_RISCV_XLEN), 64)
+carray-platform_override_modules-$(CONFIG_PLATFORM_METANOIA_MT2824) += metanoia_mt2824
+platform-objs-$(CONFIG_PLATFORM_METANOIA_MT2824) += metanoia/mt2824/mt2824.o
+endif