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firmware: Use lw instead of lwu for 32-bit architectures

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis
2019-01-23 09:29:55 -08:00
committed by Anup Patel
parent f9b033e577
commit 4f32b13802
2 changed files with 22 additions and 0 deletions
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14
firmware/fw_base.S
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@@ -69,7 +69,11 @@ _prev_arg1_override_done:
add t0, a1, zero add t0, a1, zero
and t0, t0, a3 and t0, t0, a3
/* t2 = source FDT size in big-endian */ /* t2 = source FDT size in big-endian */
#if __riscv_xlen == 64
lwu t2, 4(t0) lwu t2, 4(t0)
#else
lw t2, 4(t0)
#endif
/* t3 = bit[15:8] of FDT size */ /* t3 = bit[15:8] of FDT size */
add t3, t2, zero add t3, t2, zero
srli t3, t3, 16 srli t3, t3, 16
@@ -132,8 +136,13 @@ _start_warm:
*/ */
csrr s6, mhartid csrr s6, mhartid
la a4, platform la a4, platform
#if __riscv_xlen == 64
lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4) lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
#else
lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
#endif
/* HART ID should be within expected limit */ /* HART ID should be within expected limit */
csrr s6, mhartid csrr s6, mhartid
@@ -202,8 +211,13 @@ _hartid_to_scratch:
* s2 -> Temporary * s2 -> Temporary
*/ */
la s2, platform la s2, platform
#if __riscv_xlen == 64
lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
lwu s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) lwu s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
#else
lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
lw s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
#endif
mul s2, s2, s0 mul s2, s2, s0
la s1, _fw_end la s1, _fw_end
add s1, s1, s2 add s1, s1, s2

8
include/sbi/sbi_unpriv.h
View File

@@ -77,7 +77,11 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus)
ulong val; ulong val;
#ifndef __riscv_compressed #ifndef __riscv_compressed
asm ("csrrs %[mstatus], mstatus, %[mprv]\n" asm ("csrrs %[mstatus], mstatus, %[mprv]\n"
#if __riscv_xlen == 64
STR(LWU) " %[insn], (%[addr])\n" STR(LWU) " %[insn], (%[addr])\n"
#else
STR(LW) " %[insn], (%[addr])\n"
#endif
"csrw mstatus, %[mstatus]" "csrw mstatus, %[mstatus]"
: [mstatus] "+&r" (__mstatus), [insn] "=&r" (val) : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val)
: [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc)); : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc));
@@ -86,7 +90,11 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus)
asm ("csrrs %[mstatus], mstatus, %[mprv]\n" asm ("csrrs %[mstatus], mstatus, %[mprv]\n"
"and %[tmp], %[addr], 2\n" "and %[tmp], %[addr], 2\n"
"bnez %[tmp], 1f\n" "bnez %[tmp], 1f\n"
#if __riscv_xlen == 64
STR(LWU) " %[insn], (%[addr])\n" STR(LWU) " %[insn], (%[addr])\n"
#else
STR(LW) " %[insn], (%[addr])\n"
#endif
"and %[tmp], %[insn], %[rvc_mask]\n" "and %[tmp], %[insn], %[rvc_mask]\n"
"beq %[tmp], %[rvc_mask], 2f\n" "beq %[tmp], %[rvc_mask], 2f\n"
"sll %[insn], %[insn], %[xlen_minus_16]\n" "sll %[insn], %[insn], %[xlen_minus_16]\n"