firmware: fw_base.S: Improve loading u32

lwu exists under the current rv64 and should also exist under the rv128
in the future, so I modified the conditions of conditional compilation
so that it can adapt to the future situation

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Xiang W
2024-01-17 18:41:58 +08:00
committed by Anup Patel
parent 92e8affb31
commit 4c6b7cb76b

View File

@@ -358,7 +358,7 @@ _scratch_init:
/* t0 = source FDT start address */ /* t0 = source FDT start address */
add t0, a1, zero add t0, a1, zero
/* t2 = source FDT size in big-endian */ /* t2 = source FDT size in big-endian */
#if __riscv_xlen == 64 #if __riscv_xlen > 32
lwu t2, 4(t0) lwu t2, 4(t0)
#else #else
lw t2, 4(t0) lw t2, 4(t0)
@@ -424,7 +424,7 @@ _start_warm:
/* Find HART count and HART stack size */ /* Find HART count and HART stack size */
lla a4, platform lla a4, platform
#if __riscv_xlen == 64 #if __riscv_xlen > 32
lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4) lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
#else #else
@@ -440,7 +440,7 @@ _start_warm:
beqz s9, 3f beqz s9, 3f
li a4, 0 li a4, 0
1: 1:
#if __riscv_xlen == 64 #if __riscv_xlen > 32
lwu a5, (s9) lwu a5, (s9)
#else #else
lw a5, (s9) lw a5, (s9)
@@ -527,7 +527,7 @@ _hartid_to_scratch:
* t2 -> Temporary * t2 -> Temporary
*/ */
lla t2, platform lla t2, platform
#if __riscv_xlen == 64 #if __riscv_xlen > 32
lwu t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2) lwu t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
lwu t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2) lwu t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
#else #else