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https://github.com/riscv-software-src/opensbi.git
synced 2025-08-29 01:21:56 +01:00
dbtr: Add support for icount trigger type
The linux kernel needs icount to implement hardware breakpoints. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250724183120.1822667-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
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@@ -336,6 +336,19 @@ static void dbtr_trigger_setup(struct sbi_dbtr_trigger *trig,
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if (__test_bit(RV_DBTR_BIT(MC6, VS), &tdata1))
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__set_bit(RV_DBTR_BIT(TS, VS), &trig->state);
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break;
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case RISCV_DBTR_TRIG_ICOUNT:
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if (__test_bit(RV_DBTR_BIT(ICOUNT, U), &tdata1))
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__set_bit(RV_DBTR_BIT(TS, U), &trig->state);
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if (__test_bit(RV_DBTR_BIT(ICOUNT, S), &tdata1))
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__set_bit(RV_DBTR_BIT(TS, S), &trig->state);
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if (__test_bit(RV_DBTR_BIT(ICOUNT, VU), &tdata1))
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__set_bit(RV_DBTR_BIT(TS, VU), &trig->state);
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if (__test_bit(RV_DBTR_BIT(ICOUNT, VS), &tdata1))
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__set_bit(RV_DBTR_BIT(TS, VS), &trig->state);
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break;
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default:
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sbi_dprintf("%s: Unknown type (tdata1: 0x%lx Type: %ld)\n",
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__func__, tdata1, TDATA1_GET_TYPE(tdata1));
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@@ -379,6 +392,16 @@ static void dbtr_trigger_enable(struct sbi_dbtr_trigger *trig)
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update_bit(state & RV_DBTR_BIT_MASK(TS, S),
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RV_DBTR_BIT(MC6, S), &trig->tdata1);
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break;
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case RISCV_DBTR_TRIG_ICOUNT:
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update_bit(state & RV_DBTR_BIT_MASK(TS, VU),
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RV_DBTR_BIT(ICOUNT, VU), &trig->tdata1);
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update_bit(state & RV_DBTR_BIT_MASK(TS, VS),
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RV_DBTR_BIT(ICOUNT, VS), &trig->tdata1);
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update_bit(state & RV_DBTR_BIT_MASK(TS, U),
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RV_DBTR_BIT(ICOUNT, U), &trig->tdata1);
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update_bit(state & RV_DBTR_BIT_MASK(TS, S),
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RV_DBTR_BIT(ICOUNT, S), &trig->tdata1);
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break;
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default:
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break;
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}
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@@ -418,6 +441,12 @@ static void dbtr_trigger_disable(struct sbi_dbtr_trigger *trig)
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__clear_bit(RV_DBTR_BIT(MC6, U), &trig->tdata1);
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__clear_bit(RV_DBTR_BIT(MC6, S), &trig->tdata1);
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break;
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case RISCV_DBTR_TRIG_ICOUNT:
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__clear_bit(RV_DBTR_BIT(ICOUNT, VU), &trig->tdata1);
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__clear_bit(RV_DBTR_BIT(ICOUNT, VS), &trig->tdata1);
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__clear_bit(RV_DBTR_BIT(ICOUNT, U), &trig->tdata1);
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__clear_bit(RV_DBTR_BIT(ICOUNT, S), &trig->tdata1);
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break;
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default:
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break;
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}
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@@ -441,6 +470,7 @@ static int dbtr_trigger_supported(unsigned long type)
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switch (type) {
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case RISCV_DBTR_TRIG_MCONTROL:
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case RISCV_DBTR_TRIG_MCONTROL6:
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case RISCV_DBTR_TRIG_ICOUNT:
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return 1;
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default:
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break;
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@@ -462,6 +492,11 @@ static int dbtr_trigger_valid(unsigned long type, unsigned long tdata)
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!(tdata & RV_DBTR_BIT_MASK(MC6, M)))
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return 1;
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break;
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case RISCV_DBTR_TRIG_ICOUNT:
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if (!(tdata & RV_DBTR_BIT_MASK(ICOUNT, DMODE)) &&
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!(tdata & RV_DBTR_BIT_MASK(ICOUNT, M)))
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return 1;
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break;
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default:
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break;
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}
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