Mirrors/opensbi
5
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2025-08-30 09:56:33 +01:00
Code Issues Packages Projects Releases Wiki Activity

generic: mips: support harts to boot from mips_warm_boot

Browse Source 
We program reset base for harts (other than hart 0) to boot at
mips_warm_boot that jumps to _start_warm. This helps to skip some code
sequence to speed up.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250723204010.9927-1-cfu@mips.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Chao-ying Fu
2025-07-23 13:40:10 -07:00
committed by Anup Patel
parent 6a1f53bc2d
commit 1ffbd063c4
3 changed files with 18 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
platform/generic/mips/mips_warm_boot.S Normal file
View File

@@ -0,0 +1,12 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2025 MIPS
*
*/
.text
.align 12
.globl mips_warm_boot
mips_warm_boot:
j _start_warm
.align 2

2
platform/generic/mips/objects.mk
View File

@@ -4,5 +4,5 @@
ifeq ($(PLATFORM_RISCV_XLEN), 64) ifeq ($(PLATFORM_RISCV_XLEN), 64)
carray-platform_override_modules-$(CONFIG_PLATFORM_MIPS_P8700) += mips_p8700 carray-platform_override_modules-$(CONFIG_PLATFORM_MIPS_P8700) += mips_p8700
platform-objs-$(CONFIG_PLATFORM_MIPS_P8700) += mips/p8700.o platform-objs-$(CONFIG_PLATFORM_MIPS_P8700) += mips/p8700.o mips/mips_warm_boot.o
endif endif

5
platform/generic/mips/p8700.c
View File

@@ -16,6 +16,8 @@
#include <mips/p8700.h> #include <mips/p8700.h>
#include <mips/mips-cm.h> #include <mips/mips-cm.h>
extern void mips_warm_boot(void);
static unsigned long mips_csr_read_num(int csr_num) static unsigned long mips_csr_read_num(int csr_num)
{ {
#define switchcase_csr_read(__csr_num, __val) \ #define switchcase_csr_read(__csr_num, __val) \
@@ -150,6 +152,9 @@ static int mips_hart_start(u32 hartid, ulong saddr)
if (hartid == 0) if (hartid == 0)
return SBI_ENOTSUPP; return SBI_ENOTSUPP;
/* Change reset base to mips_warm_boot */
write_gcr_co_reset_base(hartid, (unsigned long)mips_warm_boot, local_p);
if (cpu_hart(hartid) == 0) { if (cpu_hart(hartid) == 0) {
/* Ensure its coherency is disabled */ /* Ensure its coherency is disabled */
write_gcr_co_coherence(hartid, 0, local_p); write_gcr_co_coherence(hartid, 0, local_p);