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include: sbi: Add GET_RDS_NUM/SET(_FP32/_FP64)_RDS macros

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These macros can be used to decode rd' and set rd' in RVC instructions

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
Link: https://lore.kernel.org/r/20260605113214.242-4-ganboing@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Bo Gan
2026-06-05 04:32:09 -07:00
committed by Anup Patel
parent bd986ed03d
commit 1b3424d5c0
3 changed files with 20 additions and 6 deletions
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include/sbi/riscv_encoding.h
+1
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@@ -1434,6 +1434,7 @@
#define GET_RS2S_NUM(insn) RVC_RS2S(insn) #define GET_RS2S_NUM(insn) RVC_RS2S(insn)
#define GET_RS2C_NUM(insn) RVC_RS2(insn) #define GET_RS2C_NUM(insn) RVC_RS2(insn)
#define GET_RD_NUM(insn) ((insn & MASK_RD) >> SH_RD) #define GET_RD_NUM(insn) ((insn & MASK_RD) >> SH_RD)
#define GET_RDS_NUM(insn) RVC_RS2S(insn)
#define GET_CSR_NUM(insn) ((insn & MASK_CSR) >> SHIFT_CSR) #define GET_CSR_NUM(insn) ((insn & MASK_CSR) >> SHIFT_CSR)
#define GET_AQRL(insn) ((insn & MASK_AQRL) >> SHIFT_AQRL) #define GET_AQRL(insn) ((insn & MASK_AQRL) >> SHIFT_AQRL)
include/sbi/riscv_fp.h
+18 -6
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@@ -91,15 +91,27 @@
#define GET_F64_RS1(insn, regs) (GET_F64_REG(insn, 15, regs)) #define GET_F64_RS1(insn, regs) (GET_F64_REG(insn, 15, regs))
#define GET_F64_RS2(insn, regs) (GET_F64_REG(insn, 20, regs)) #define GET_F64_RS2(insn, regs) (GET_F64_REG(insn, 20, regs))
#define GET_F64_RS3(insn, regs) (GET_F64_REG(insn, 27, regs)) #define GET_F64_RS3(insn, regs) (GET_F64_REG(insn, 27, regs))
#define SET_F32_RD(insn, regs, val) \ #define SET_F32_RD(insn, regs, val) do { \
(SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY(regs)) SET_F32_REG(insn, 7, regs, val); \
#define SET_F64_RD(insn, regs, val) \ SET_FS_DIRTY(regs); \
(SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY(regs)) } while(0)
#define SET_F64_RD(insn, regs, val) do { \
SET_F64_REG(insn, 7, regs, val); \
SET_FS_DIRTY(regs); \
} while(0)
#define GET_F32_RS2C(insn, regs) (GET_F32_REG(insn, 2, regs)) #define GET_F32_RS2C(insn, regs) (GET_F32_REG(insn, 2, regs))
#define GET_F32_RS2S(insn, regs) (GET_F32_REG(RVC_RS2S(insn), 0, regs)) #define GET_F32_RS2S(insn, regs) (GET_F32_REG(GET_RS2S_NUM(insn), 0, regs))
#define GET_F64_RS2C(insn, regs) (GET_F64_REG(insn, 2, regs)) #define GET_F64_RS2C(insn, regs) (GET_F64_REG(insn, 2, regs))
#define GET_F64_RS2S(insn, regs) (GET_F64_REG(RVC_RS2S(insn), 0, regs)) #define GET_F64_RS2S(insn, regs) (GET_F64_REG(GET_RS2S_NUM(insn), 0, regs))
#define SET_F32_RDS(insn, regs, val) do { \
SET_F32_REG(GET_RDS_NUM(insn), 0, regs, val); \
SET_FS_DIRTY(regs); \
} while(0)
#define SET_F64_RDS(insn, regs, val) do { \
SET_F64_REG(GET_RDS_NUM(insn), 0, regs, val); \
SET_FS_DIRTY(regs); \
} while(0)
#endif #endif
include/sbi/sbi_trap.h
+1
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@@ -218,6 +218,7 @@ _Static_assert(
#define GET_RS2S(insn, regs) REG_VAL(GET_RS2S_NUM(insn), regs) #define GET_RS2S(insn, regs) REG_VAL(GET_RS2S_NUM(insn), regs)
#define GET_RS2C(insn, regs) REG_VAL(GET_RS2C_NUM(insn), regs) #define GET_RS2C(insn, regs) REG_VAL(GET_RS2C_NUM(insn), regs)
#define SET_RD(insn, regs, val) (REG_VAL(GET_RD_NUM(insn), regs) = (val)) #define SET_RD(insn, regs, val) (REG_VAL(GET_RD_NUM(insn), regs) = (val))
#define SET_RDS(insn, regs, val) (REG_VAL(GET_RDS_NUM(insn), regs) = (val))
/** Representation of trap details */ /** Representation of trap details */
struct sbi_trap_info { struct sbi_trap_info {