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platform: andes/ae350: Use fdt irqchip driver
Andes PLIC is compatible with plic driver. The PLIC base address and number of source can be obtained by parsing the device tree. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:

committed by
Anup Patel

parent
8234fc1bdf
commit
127a3f2ab4
@@ -3,13 +3,14 @@
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config PLATFORM_ANDES_AE350
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config PLATFORM_ANDES_AE350
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bool
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bool
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select FDT
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select FDT
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select IRQCHIP_PLIC
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select FDT_SERIAL
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select FDT_SERIAL
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select FDT_SERIAL_UART8250
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select FDT_SERIAL_UART8250
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select FDT_TIMER
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select FDT_TIMER
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select FDT_TIMER_PLMT
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select FDT_TIMER_PLMT
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select FDT_RESET
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select FDT_RESET
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select FDT_RESET_ATCWDT200
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select FDT_RESET_ATCWDT200
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select FDT_IRQCHIP
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select FDT_IRQCHIP_PLIC
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default y
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default y
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if PLATFORM_ANDES_AE350
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if PLATFORM_ANDES_AE350
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@@ -17,7 +17,7 @@
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_trap.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/irqchip/fdt_irqchip.h>
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#include <sbi_utils/reset/fdt_reset.h>
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#include <sbi_utils/reset/fdt_reset.h>
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#include <sbi_utils/serial/fdt_serial.h>
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#include <sbi_utils/serial/fdt_serial.h>
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#include <sbi_utils/timer/fdt_timer.h>
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#include <sbi_utils/timer/fdt_timer.h>
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@@ -25,11 +25,6 @@
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#include "plicsw.h"
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#include "plicsw.h"
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#include "cache.h"
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#include "cache.h"
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static struct plic_data plic = {
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.addr = AE350_PLIC_ADDR,
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.num_src = AE350_PLIC_NUM_SOURCES,
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};
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/* Platform final initialization. */
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/* Platform final initialization. */
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static int ae350_final_init(bool cold_boot)
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static int ae350_final_init(bool cold_boot)
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{
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{
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@@ -46,21 +41,6 @@ static int ae350_final_init(bool cold_boot)
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return 0;
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return 0;
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}
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}
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/* Initialize the platform interrupt controller for current HART. */
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static int ae350_irqchip_init(bool cold_boot)
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{
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(&plic);
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if (ret)
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return ret;
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}
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return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1);
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}
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static struct sbi_ipi_device plicsw_ipi = {
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static struct sbi_ipi_device plicsw_ipi = {
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.name = "ae350_plicsw",
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.name = "ae350_plicsw",
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.ipi_send = plicsw_ipi_send,
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.ipi_send = plicsw_ipi_send,
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@@ -134,7 +114,7 @@ const struct sbi_platform_operations platform_ops = {
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.console_init = fdt_serial_init,
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.console_init = fdt_serial_init,
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.irqchip_init = ae350_irqchip_init,
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.irqchip_init = fdt_irqchip_init,
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.ipi_init = ae350_ipi_init,
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.ipi_init = ae350_ipi_init,
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@@ -13,9 +13,6 @@
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#define AE350_HART_COUNT 4
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#define AE350_HART_COUNT 4
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#define AE350_PLIC_ADDR 0xe4000000
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#define AE350_PLIC_NUM_SOURCES 71
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#define AE350_PLICSW_ADDR 0xe6400000
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#define AE350_PLICSW_ADDR 0xe6400000
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#define AE350_L2C_ADDR 0xe0500000
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#define AE350_L2C_ADDR 0xe0500000
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