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lib: sbi_pmu: fix integer overflow in pmu_ctr_idx_validate
pmu_ctr_idx_validate() checks whether counter indices are in range using cbase + sbi_fls(cmask) < total_ctrs. Both operands are unsigned long, so a crafted cbase close to ULONG_MAX causes the addition to wrap around to a small value that passes the comparison. Once validation is bypassed, sbi_pmu_ctr_cfg_match() with the SKIP_MATCH flag uses the overflowed index directly as an array subscript into phs->active_events[], producing an out-of-bounds read in M-mode. Through the firmware-event code path, the same overflowed index reaches fw_counters_data[] and fw_counters_started, giving an attacker OOB write-zero and OOB bit-set primitives in M-mode memory. Fix pmu_ctr_idx_validate() by checking for unsigned overflow before the comparison, and add a secondary bounds check on cidx_first in the SKIP_MATCH path so that even if validation is somehow bypassed in the future, the array access remains bounded. Signed-off-by: liutong <liutong@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260624035049.1753003-1-liutong@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
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+13
-2
@@ -223,8 +223,16 @@ static int pmu_ctr_validate(struct sbi_pmu_hart_state *phs,
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static bool pmu_ctr_idx_validate(unsigned long cbase, unsigned long cmask)
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{
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/* Do a basic sanity check of counter base & mask */
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return cmask && cbase + sbi_fls(cmask) < total_ctrs;
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unsigned long last;
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if (!cmask)
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return false;
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last = sbi_fls(cmask);
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if (cbase > -1UL - last)
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return false;
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return (cbase + last) < total_ctrs;
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}
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int sbi_pmu_ctr_fw_read(unsigned long cidx, uint64_t *cval, bool high_bits)
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@@ -915,6 +923,9 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
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*/
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unsigned long cidx_first = cidx_base + sbi_ffs(cidx_mask);
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if (cidx_first >= total_ctrs)
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return SBI_EINVAL;
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if (phs->active_events[cidx_first] == SBI_PMU_EVENT_IDX_INVALID)
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return SBI_EINVAL;
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ctr_idx = cidx_first;
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