#ifndef _DMA_REGS_H_ #define _DMA_REGS_H_ #include #include #define DMA_REG_START 0x00 #define DMA_REG_CLEAR_INTERRUPT 0x0C #define DMA_REG_FPGA_ADDRESS 0x10 #define DMA_REG_SC_ADDRESS 0x20 #define DMA_REG_OPERATION 0x30 // 0 = READ, 1 = WRITE, 2 = ALLOC, 3 = FREE #define DMA_REG_BYTES 0x40 #define DMA_REG_ALLOC_ADDRESS 0x50 template class dma_regs { public: // storage declarations // BEGIN_BF_DECL(start_t, uint32_t); // BF_FIELD(start, 0, 1); // END_BF_DECL() r_start; uint32_t r_start; uint32_t r_address; uint32_t r_operation; uint32_t r_bytes; static inline uint32_t& start_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_START); } static inline uint32_t& clear_interrupt_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_CLEAR_INTERRUPT); } static inline uint32_t & fpga_address_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_FPGA_ADDRESS); } static inline uint32_t & sc_address_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_SC_ADDRESS); } static inline uint32_t & operation_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_OPERATION); } static inline uint32_t & bytes_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_BYTES); } static inline uint32_t & alloc_address_reg(){ return *reinterpret_cast(BASE_ADDR+DMA_REG_ALLOC_ADDRESS); } }; #endif // _SPN_REGS_H_