/* * riscv-bldc.h * * Created on: 28.07.2018 * Author: eyck */ #ifndef RISCV_BLDC_H_ #define RISCV_BLDC_H_ #include extern uint32_t pwm; extern uint32_t DRIVE_PORT; enum PINS{ UL=1, //! Port pin connected to phase U, low side enable switch. UH=0, //! Port pin connected to phase U, high side enable switch. VL=11,//! Port pin connected to phase V, low side enable switch. VH=10,//! Port pin connected to phase V, high side enable switch. WL=19,//! Port pin connected to phase W, low side enable switch. WH=20 //! Port pin connected to phase W, high side enable switch. }; enum { CW=0, //! Clockwise rotation flag. CCW=1 //! Counterclockwise rotation flag. }; namespace DRIVE_PATTERN_CCW{ enum { STEP1=((1 << UL) | (1 << VH)),//! Drive pattern for commutation step 1, CCW rotation. STEP2=((1 << UL) | (1 << WH)),//! Drive pattern for commutation step 2, CCW rotation. STEP3=((1 << VL) | (1 << WH)),//! Drive pattern for commutation step 3, CCW rotation. STEP4=((1 << VL) | (1 << UH)),//! Drive pattern for commutation step 4, CCW rotation. STEP5=((1 << WL) | (1 << UH)),//! Drive pattern for commutation step 5, CCW rotation. STEP6=((1 << WL) | (1 << VH)) //! Drive pattern for commutation step 6, CCW rotation. }; } namespace DRIVE_PATTERN_CW { enum { STEP1=((1 << VH) | (1 << WL)),//! Drive pattern for commutation step 1, CW rotation. STEP2=((1 << UH) | (1 << WL)),//! Drive pattern for commutation step 2, CW rotation. STEP3=((1 << UH) | (1 << VL)),//! Drive pattern for commutation step 3, CW rotation. STEP4=((1 << WH) | (1 << VL)),//! Drive pattern for commutation step 4, CW rotation. STEP5=((1 << WH) | (1 << UL)),//! Drive pattern for commutation step 5, CW rotation. STEP6=((1 << VH) | (1 << UL)) //! Drive pattern for commutation step 6, CW rotation. }; } //! Startup delays are given in microseconds times STARTUP_DELAY_MULTIPLIER. const auto STARTUP_DELAY_MULTIPLIER=1000; /*! * Number of milliseconds to lock rotor in first commutation step before * the timed startup sequence is initiated. */ const auto STARTUP_LOCK_DELAY=50; #endif /* RISCV_BLDC_H_ */