From 3512206d772631df964c059187d1ef10872eafa6 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 25 Sep 2018 18:31:29 +0200 Subject: [PATCH] Added hello world project --- .gitignore | 1 - hello-world/Makefile | 14 + .../bsp/drivers/fe300prci/fe300prci_driver.c | 252 ++++ .../bsp/drivers/fe300prci/fe300prci_driver.h | 79 + hello-world/bsp/drivers/plic/plic_driver.c | 127 ++ hello-world/bsp/drivers/plic/plic_driver.h | 51 + hello-world/bsp/env/common.mk | 65 + hello-world/bsp/env/encoding.h | 1313 +++++++++++++++++ hello-world/bsp/env/entry.S | 97 ++ hello-world/bsp/env/freedom-e300-arty/init.c | 87 ++ .../bsp/env/freedom-e300-arty/link.lds | 167 +++ .../bsp/env/freedom-e300-arty/openocd.cfg | 30 + .../bsp/env/freedom-e300-arty/platform.h | 125 ++ .../bsp/env/freedom-e300-hifive1/init.c | 238 +++ .../bsp/env/freedom-e300-hifive1/link.lds | 167 +++ .../bsp/env/freedom-e300-hifive1/openocd.cfg | 34 + .../bsp/env/freedom-e300-hifive1/platform.h | 133 ++ hello-world/bsp/env/hifive1.h | 81 + hello-world/bsp/env/iss/init.c | 238 +++ hello-world/bsp/env/iss/link.lds | 168 +++ hello-world/bsp/env/iss/openocd.cfg | 34 + hello-world/bsp/env/iss/platform.h | 133 ++ hello-world/bsp/env/start.S | 54 + hello-world/bsp/include/sifive/bits.h | 35 + hello-world/bsp/include/sifive/const.h | 17 + hello-world/bsp/include/sifive/devices/aon.h | 88 ++ .../bsp/include/sifive/devices/clint.h | 14 + hello-world/bsp/include/sifive/devices/gpio.h | 24 + hello-world/bsp/include/sifive/devices/otp.h | 23 + hello-world/bsp/include/sifive/devices/plic.h | 31 + hello-world/bsp/include/sifive/devices/prci.h | 56 + hello-world/bsp/include/sifive/devices/pwm.h | 37 + hello-world/bsp/include/sifive/devices/spi.h | 80 + hello-world/bsp/include/sifive/devices/uart.h | 27 + hello-world/bsp/include/sifive/sections.h | 16 + hello-world/bsp/libwrap/libwrap.mk | 54 + hello-world/bsp/libwrap/misc/write_hex.c | 19 + hello-world/bsp/libwrap/stdlib/malloc.c | 17 + hello-world/bsp/libwrap/sys/_exit.c | 17 + hello-world/bsp/libwrap/sys/close.c | 9 + hello-world/bsp/libwrap/sys/execve.c | 9 + hello-world/bsp/libwrap/sys/fork.c | 9 + hello-world/bsp/libwrap/sys/fstat.c | 16 + hello-world/bsp/libwrap/sys/getpid.c | 6 + hello-world/bsp/libwrap/sys/isatty.c | 11 + hello-world/bsp/libwrap/sys/kill.c | 9 + hello-world/bsp/libwrap/sys/link.c | 9 + hello-world/bsp/libwrap/sys/lseek.c | 14 + hello-world/bsp/libwrap/sys/open.c | 9 + hello-world/bsp/libwrap/sys/openat.c | 9 + hello-world/bsp/libwrap/sys/read.c | 30 + hello-world/bsp/libwrap/sys/sbrk.c | 16 + hello-world/bsp/libwrap/sys/stat.c | 10 + hello-world/bsp/libwrap/sys/stub.h | 10 + hello-world/bsp/libwrap/sys/times.c | 10 + hello-world/bsp/libwrap/sys/unlink.c | 9 + hello-world/bsp/libwrap/sys/wait.c | 9 + hello-world/bsp/libwrap/sys/write.c | 29 + hello-world/hello | Bin 0 -> 205008 bytes hello-world/hello.c | 32 + hello-world/wrap_printf.c | 271 ++++ hello-world/wrap_stubs.c | 15 + riscv-bldc-forced-commutation/Makefile | 28 + .../bsp/env/common.mk | 18 +- .../src/{peripherals.cpp => hifive1_io.cpp} | 0 .../src/{peripherals.h => hifive1_io.h} | 0 .../src/{ => io}/gpio.h | 0 .../src/{ => io}/pwm.h | 0 .../src/{ => io}/spi.h | 0 .../src/{ => io}/uart.h | 0 70 files changed, 4835 insertions(+), 5 deletions(-) create mode 100644 hello-world/Makefile create mode 100644 hello-world/bsp/drivers/fe300prci/fe300prci_driver.c create mode 100644 hello-world/bsp/drivers/fe300prci/fe300prci_driver.h create mode 100644 hello-world/bsp/drivers/plic/plic_driver.c create mode 100644 hello-world/bsp/drivers/plic/plic_driver.h create mode 100644 hello-world/bsp/env/common.mk create mode 100644 hello-world/bsp/env/encoding.h create mode 100644 hello-world/bsp/env/entry.S create mode 100644 hello-world/bsp/env/freedom-e300-arty/init.c create mode 100644 hello-world/bsp/env/freedom-e300-arty/link.lds create mode 100644 hello-world/bsp/env/freedom-e300-arty/openocd.cfg create mode 100644 hello-world/bsp/env/freedom-e300-arty/platform.h create mode 100644 hello-world/bsp/env/freedom-e300-hifive1/init.c create mode 100644 hello-world/bsp/env/freedom-e300-hifive1/link.lds create mode 100644 hello-world/bsp/env/freedom-e300-hifive1/openocd.cfg create mode 100644 hello-world/bsp/env/freedom-e300-hifive1/platform.h create mode 100644 hello-world/bsp/env/hifive1.h create mode 100644 hello-world/bsp/env/iss/init.c create mode 100644 hello-world/bsp/env/iss/link.lds create mode 100644 hello-world/bsp/env/iss/openocd.cfg create mode 100644 hello-world/bsp/env/iss/platform.h create mode 100644 hello-world/bsp/env/start.S create mode 100644 hello-world/bsp/include/sifive/bits.h create mode 100644 hello-world/bsp/include/sifive/const.h create mode 100644 hello-world/bsp/include/sifive/devices/aon.h create mode 100644 hello-world/bsp/include/sifive/devices/clint.h create mode 100644 hello-world/bsp/include/sifive/devices/gpio.h create mode 100644 hello-world/bsp/include/sifive/devices/otp.h create mode 100644 hello-world/bsp/include/sifive/devices/plic.h create mode 100644 hello-world/bsp/include/sifive/devices/prci.h create mode 100644 hello-world/bsp/include/sifive/devices/pwm.h create mode 100644 hello-world/bsp/include/sifive/devices/spi.h create mode 100644 hello-world/bsp/include/sifive/devices/uart.h create mode 100644 hello-world/bsp/include/sifive/sections.h create mode 100644 hello-world/bsp/libwrap/libwrap.mk create mode 100644 hello-world/bsp/libwrap/misc/write_hex.c create mode 100644 hello-world/bsp/libwrap/stdlib/malloc.c create mode 100644 hello-world/bsp/libwrap/sys/_exit.c create mode 100644 hello-world/bsp/libwrap/sys/close.c create mode 100644 hello-world/bsp/libwrap/sys/execve.c create mode 100644 hello-world/bsp/libwrap/sys/fork.c create mode 100644 hello-world/bsp/libwrap/sys/fstat.c create mode 100644 hello-world/bsp/libwrap/sys/getpid.c create mode 100644 hello-world/bsp/libwrap/sys/isatty.c create mode 100644 hello-world/bsp/libwrap/sys/kill.c create mode 100644 hello-world/bsp/libwrap/sys/link.c create mode 100644 hello-world/bsp/libwrap/sys/lseek.c create mode 100644 hello-world/bsp/libwrap/sys/open.c create mode 100644 hello-world/bsp/libwrap/sys/openat.c create mode 100644 hello-world/bsp/libwrap/sys/read.c create mode 100644 hello-world/bsp/libwrap/sys/sbrk.c create mode 100644 hello-world/bsp/libwrap/sys/stat.c create mode 100644 hello-world/bsp/libwrap/sys/stub.h create mode 100644 hello-world/bsp/libwrap/sys/times.c create mode 100644 hello-world/bsp/libwrap/sys/unlink.c create mode 100644 hello-world/bsp/libwrap/sys/wait.c create mode 100644 hello-world/bsp/libwrap/sys/write.c create mode 100755 hello-world/hello create mode 100644 hello-world/hello.c create mode 100644 hello-world/wrap_printf.c create mode 100644 hello-world/wrap_stubs.c create mode 100644 riscv-bldc-forced-commutation/Makefile rename riscv-bldc-forced-commutation/src/{peripherals.cpp => hifive1_io.cpp} (100%) rename riscv-bldc-forced-commutation/src/{peripherals.h => hifive1_io.h} (100%) rename riscv-bldc-forced-commutation/src/{ => io}/gpio.h (100%) rename riscv-bldc-forced-commutation/src/{ => io}/pwm.h (100%) rename riscv-bldc-forced-commutation/src/{ => io}/spi.h (100%) rename riscv-bldc-forced-commutation/src/{ => io}/uart.h (100%) diff --git a/.gitignore b/.gitignore index c3271b5..1ff2a48 100644 --- a/.gitignore +++ b/.gitignore @@ -148,7 +148,6 @@ CMakeCache.txt CMakeFiles CMakeScripts Testing -Makefile cmake_install.cmake install_manifest.txt compile_commands.json diff --git a/hello-world/Makefile b/hello-world/Makefile new file mode 100644 index 0000000..92a6582 --- /dev/null +++ b/hello-world/Makefile @@ -0,0 +1,14 @@ + +TARGET = hello +C_SRCS += $(wildcard *.c) +#CFLAGS += -O2 +#-fno-builtin-printf + +BOARD=freedom-e300-hifive1 +LINK_TARGET=link +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 + +TOOL_DIR?=/opt/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin +BSP_BASE = ./bsp +include $(BSP_BASE)/env/common.mk diff --git a/hello-world/bsp/drivers/fe300prci/fe300prci_driver.c b/hello-world/bsp/drivers/fe300prci/fe300prci_driver.c new file mode 100644 index 0000000..2d9c52f --- /dev/null +++ b/hello-world/bsp/drivers/fe300prci/fe300prci_driver.c @@ -0,0 +1,252 @@ +// See LICENSE file for license details + +#include "platform.h" + +#ifdef PRCI_BASE_ADDR +#include "fe300prci/fe300prci_driver.h" +#include + +#define rdmcycle(x) { \ + uint32_t lo, hi, hi2; \ + __asm__ __volatile__ ("1:\n\t" \ + "csrr %0, mcycleh\n\t" \ + "csrr %1, mcycle\n\t" \ + "csrr %2, mcycleh\n\t" \ + "bne %0, %2, 1b\n\t" \ + : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ + *(x) = lo | ((uint64_t) hi << 32); \ + } + +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq) +{ + + uint32_t start_mtime = CLINT_REG(CLINT_MTIME); + uint32_t end_mtime = start_mtime + mtime_ticks + 1; + + // Make sure we won't get rollover. + while (end_mtime < start_mtime){ + start_mtime = CLINT_REG(CLINT_MTIME); + end_mtime = start_mtime + mtime_ticks + 1; + } + + // Don't start measuring until mtime edge. + uint32_t tmp = start_mtime; + do { + start_mtime = CLINT_REG(CLINT_MTIME); + } while (start_mtime == tmp); + + uint64_t start_mcycle; + rdmcycle(&start_mcycle); + + while (CLINT_REG(CLINT_MTIME) < end_mtime) ; + + uint64_t end_mcycle; + rdmcycle(&end_mcycle); + uint32_t difference = (uint32_t) (end_mcycle - start_mcycle); + + uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks; + return (uint32_t) freq & 0xFFFFFFFF; + +} + + +void PRCI_use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + // It is OK to change this even if we are running off of it. + + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0); + + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + PRCI_use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if desired. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + + // To overclock, use the hfrosc + if (hfrosctrim >= 0 && hfroscdiv >= 0) { + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + } + + // Set DIV Settings for PLL + + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + if (finaldiv == 1){ + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1)); + } + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = CLINT_REG(CLINT_MTIME); + while (CLINT_REG(CLINT_MTIME) - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0); + + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); + + // If we're running off HFXOSC, turn off the HFROSC to + // save power. + if (refsel) { + PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); + } + +} + +void PRCI_use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + PRCI_use_hfrosc(4, 16); +} + +void PRCI_use_hfxosc(uint32_t finaldiv) +{ + + PRCI_use_pll(1, // Use HFXTAL + 1, // Bypass = 1 + 0, // PLL settings don't matter + 0, // PLL settings don't matter + 0, // PLL settings don't matter + finaldiv, + -1, + -1); +} + +// This is a generic function, which +// doesn't span the entire range of HFROSC settings. +// It only adjusts the trim, which can span a hundred MHz or so. +// This function does not check the legality of the PLL settings +// at all, and it is quite possible to configure invalid PLL settings +// this way. +// It returns the actual measured CPU frequency. + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target ) +{ + + uint32_t hfrosctrim = 0; + uint32_t hfroscdiv = 4; + uint32_t prev_trim = 0; + + // In this function we use PLL settings which + // will give us a 32x multiplier from the output + // of the HFROSC source to the output of the + // PLL. We first measure our HFROSC to get the + // right trim, then finally use it as the PLL source. + // We should really check here that the f_cpu + // requested is something in the limit of the PLL. For + // now that is up to the user. + + // This will undershoot for frequencies not divisible by 16. + uint32_t desired_hfrosc_freq = (f_cpu/ 16); + + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + + // Ignore the first run (for icache reasons) + uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + uint32_t prev_freq = cpu_freq; + + while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){ + prev_trim = hfrosctrim; + prev_freq = cpu_freq; + hfrosctrim ++; + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + } + + // We couldn't go low enough + if (prev_freq > desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // We couldn't go high enough + if (cpu_freq < desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // Check for over/undershoot + switch(target) { + case(PRCI_FREQ_CLOSEST): + if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + } else { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + break; + case(PRCI_FREQ_UNDERSHOOT): + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + break; + default: + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + +} + +#endif diff --git a/hello-world/bsp/drivers/fe300prci/fe300prci_driver.h b/hello-world/bsp/drivers/fe300prci/fe300prci_driver.h new file mode 100644 index 0000000..7100f46 --- /dev/null +++ b/hello-world/bsp/drivers/fe300prci/fe300prci_driver.h @@ -0,0 +1,79 @@ +// See LICENSE file for license details + +#ifndef _FE300PRCI_DRIVER_H_ +#define _FE300PRCI_DRIVER_H_ + +__BEGIN_DECLS + +#include + +typedef enum prci_freq_target { + + PRCI_FREQ_OVERSHOOT, + PRCI_FREQ_CLOSEST, + PRCI_FREQ_UNDERSHOOT + +} PRCI_freq_target; + +/* Measure and return the approximate frequency of the + * CPU, as given by measuring the mcycle counter against + * the mtime ticks. + */ +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq); + +/* Safely switch over to the HFROSC using the given div + * and trim settings. + */ +void PRCI_use_hfrosc(int div, int trim); + +/* Safely switch over to the 16MHz HFXOSC, + * applying the finaldiv clock divider (1 is the lowest + * legal value). + */ +void PRCI_use_hfxosc(uint32_t finaldiv); + +/* Safely switch over to the PLL using the given + * settings. + * + * Note that not all combinations of the inputs are actually + * legal, and this function does not check for their + * legality ("safely" means that this function won't turn off + * or glitch the clock the CPU is actually running off, but + * doesn't protect against you making it too fast or slow.) + */ + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim); + +/* Use the default clocks configured at reset. + * This is ~16Mhz HFROSC and turns off the LFROSC + * (on the current FE310 Dev Platforms, an external LFROSC is + * used as it is more power efficient). + */ +void PRCI_use_default_clocks(); + +/* This routine will adjust the HFROSC trim + * while using HFROSC as the clock source, + * measure the resulting frequency, then + * use it as the PLL clock source, + * in an attempt to get over, under, or close to the + * requested frequency. It returns the actual measured + * frequency. + * + * Note that the requested frequency must be within the + * range supported by the PLL so not all values are + * achievable with this function, and not all + * are guaranteed to actually work. The PLL + * is rated higher than the hardware. + * + * There is no check on the desired f_cpu frequency, it + * is up to the user to specify something reasonable. + */ + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target); + +__END_DECLS + +#endif + diff --git a/hello-world/bsp/drivers/plic/plic_driver.c b/hello-world/bsp/drivers/plic/plic_driver.c new file mode 100644 index 0000000..b27d7a5 --- /dev/null +++ b/hello-world/bsp/drivers/plic/plic_driver.c @@ -0,0 +1,127 @@ +// See LICENSE for license details. + +#include "sifive/devices/plic.h" +#include "plic/plic_driver.h" +#include "platform.h" +#include "encoding.h" +#include + + +// Note that there are no assertions or bounds checking on these +// parameter values. + +void volatile_memzero(uint8_t * base, unsigned int size) +{ + volatile uint8_t * ptr; + for (ptr = base; ptr < (base + size); ptr++){ + *ptr = 0; + } +} + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ) +{ + + this_plic->base_addr = base_addr; + this_plic->num_sources = num_sources; + this_plic->num_priorities = num_priorities; + + // Disable all interrupts (don't assume that these registers are reset). + unsigned long hart_id = read_csr(mhartid); + volatile_memzero((uint8_t*) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)), + (num_sources + 8) / 8); + + // Set all priorities to 0 (equal priority -- don't assume that these are reset). + volatile_memzero ((uint8_t *)(this_plic->base_addr + + PLIC_PRIORITY_OFFSET), + (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE); + + // Set the threshold to 0. + volatile plic_threshold* threshold = (plic_threshold*) + (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold = 0; + +} + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold_ptr = threshold; + +} + + +void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current | ( 1 << (source & 0x7)); + *current_ptr = current; + +} + +void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current & ~(( 1 << (source & 0x7))); + *current_ptr = current; + +} + +void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){ + + if (this_plic->num_priorities > 0) { + volatile plic_priority * priority_ptr = (volatile plic_priority *) + (this_plic->base_addr + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; + } +} + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ + + unsigned long hart_id = read_csr(mhartid); + + volatile plic_source * claim_addr = (volatile plic_source * ) + (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + + return *claim_addr; + +} + +void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; + +} + diff --git a/hello-world/bsp/drivers/plic/plic_driver.h b/hello-world/bsp/drivers/plic/plic_driver.h new file mode 100644 index 0000000..e7d609b --- /dev/null +++ b/hello-world/bsp/drivers/plic/plic_driver.h @@ -0,0 +1,51 @@ +// See LICENSE file for licence details + +#ifndef PLIC_DRIVER_H +#define PLIC_DRIVER_H + + +__BEGIN_DECLS + +#include "platform.h" + +typedef struct __plic_instance_t +{ + uintptr_t base_addr; + + uint32_t num_sources; + uint32_t num_priorities; + +} plic_instance_t; + +typedef uint32_t plic_source; +typedef uint32_t plic_priority; +typedef uint32_t plic_threshold; + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ); + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold); + +void PLIC_enable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_disable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_set_priority (plic_instance_t * this_plic, + plic_source source, + plic_priority priority); + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic); + +void PLIC_complete_interrupt(plic_instance_t * this_plic, + plic_source source); + +__END_DECLS + +#endif diff --git a/hello-world/bsp/env/common.mk b/hello-world/bsp/env/common.mk new file mode 100644 index 0000000..241f81d --- /dev/null +++ b/hello-world/bsp/env/common.mk @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_COMMON +_SIFIVE_MK_COMMON := # defined + +.PHONY: all +all: $(TARGET) + +include $(BSP_BASE)/libwrap/libwrap.mk + +ENV_DIR = $(BSP_BASE)/env +PLATFORM_DIR = $(ENV_DIR)/$(BOARD) + +ASM_SRCS += $(ENV_DIR)/start.S +ASM_SRCS += $(ENV_DIR)/entry.S +C_SRCS += $(PLATFORM_DIR)/init.c + +LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds + +INCLUDES += -I$(BSP_BASE)/include +INCLUDES += -I$(BSP_BASE)/drivers/ +INCLUDES += -I$(ENV_DIR) +INCLUDES += -I$(PLATFORM_DIR) + +TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin + +LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles +LDFLAGS += -L$(ENV_DIR) --specs=nano.specs + +ASM_OBJS := $(ASM_SRCS:.S=.o) +C_OBJS := $(C_SRCS:.c=.o) +CXX_OBJS := $(CXX_SRCS:.cpp=.o) + +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS) +LINK_DEPS += $(LINKER_SCRIPT) + +CLEAN_OBJS += $(TARGET) $(LINK_OBJS) + +CFLAGS += -march=$(RISCV_ARCH) +CFLAGS += -mabi=$(RISCV_ABI) +CFLAGS += -mcmodel=medany + +TRIPLET?=riscv64-unknown-elf +CXX=$(TOOL_DIR)/$(TRIPLET)-c++ +CC=$(TOOL_DIR)/$(TRIPLET)-gcc +LD=$(TOOL_DIR)/$(TRIPLET)-gcc + + +$(TARGET): $(LINK_OBJS) $(LINK_DEPS) + $(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@ + +$(ASM_OBJS): %.o: %.S $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(C_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + +$(CXX_OBJS): %.o: %.cpp $(HEADERS) + $(CXX) $(CFLAGS) $(CXXFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + +.PHONY: clean +clean: + rm -f $(CLEAN_OBJS) + +endif # _SIFIVE_MK_COMMON diff --git a/hello-world/bsp/env/encoding.h b/hello-world/bsp/env/encoding.h new file mode 100644 index 0000000..35e0f9f --- /dev/null +++ b/hello-world/bsp/env/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/hello-world/bsp/env/entry.S b/hello-world/bsp/env/entry.S new file mode 100644 index 0000000..1f5de24 --- /dev/null +++ b/hello-world/bsp/env/entry.S @@ -0,0 +1,97 @@ +// See LICENSE for license details + +#ifndef ENTRY_S +#define ENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x2, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + csrw mepc, a0 + + # Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x1, 1*REGBYTES(sp) + LOAD x2, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + mret + +.weak handle_trap +handle_trap: +1: + j 1b + +#endif diff --git a/hello-world/bsp/env/freedom-e300-arty/init.c b/hello-world/bsp/env/freedom-e300-arty/init.c new file mode 100644 index 0000000..a6f4b39 --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-arty/init.c @@ -0,0 +1,87 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long get_cpu_freq() +{ + return 65000000; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + #endif +} + +void _fini() +{ +} diff --git a/hello-world/bsp/env/freedom-e300-arty/link.lds b/hello-world/bsp/env/freedom-e300-arty/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-arty/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/hello-world/bsp/env/freedom-e300-arty/openocd.cfg b/hello-world/bsp/env/freedom-e300-arty/openocd.cfg new file mode 100644 index 0000000..f4b28ed --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/hello-world/bsp/env/freedom-e300-arty/platform.h b/hello-world/bsp/env/freedom-e300-arty/platform.h new file mode 100644 index 0000000..d5d6dda --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-arty/platform.h @@ -0,0 +1,125 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF Mappings +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt Numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS +#include "hifive1.h" + +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/hello-world/bsp/env/freedom-e300-hifive1/init.c b/hello-world/bsp/env/freedom-e300-hifive1/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-hifive1/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/hello-world/bsp/env/freedom-e300-hifive1/link.lds b/hello-world/bsp/env/freedom-e300-hifive1/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-hifive1/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/hello-world/bsp/env/freedom-e300-hifive1/openocd.cfg b/hello-world/bsp/env/freedom-e300-hifive1/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/hello-world/bsp/env/freedom-e300-hifive1/platform.h b/hello-world/bsp/env/freedom-e300-hifive1/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/hello-world/bsp/env/freedom-e300-hifive1/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/hello-world/bsp/env/hifive1.h b/hello-world/bsp/env/hifive1.h new file mode 100644 index 0000000..4c65f18 --- /dev/null +++ b/hello-world/bsp/env/hifive1.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_HIFIVE1_H +#define _SIFIVE_HIFIVE1_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. +// These are also mapped to RGB LEDs on the Freedom E300 Arty +// FPGA +// Dev Kit. + +#define RED_LED_OFFSET 22 +#define GREEN_LED_OFFSET 19 +#define BLUE_LED_OFFSET 21 + +// These are the GPIO bit offsets for the differen digital pins +// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. +#define PIN_0_OFFSET 16 +#define PIN_1_OFFSET 17 +#define PIN_2_OFFSET 18 +#define PIN_3_OFFSET 19 +#define PIN_4_OFFSET 20 +#define PIN_5_OFFSET 21 +#define PIN_6_OFFSET 22 +#define PIN_7_OFFSET 23 +#define PIN_8_OFFSET 0 +#define PIN_9_OFFSET 1 +#define PIN_10_OFFSET 2 +#define PIN_11_OFFSET 3 +#define PIN_12_OFFSET 4 +#define PIN_13_OFFSET 5 +//#define PIN_14_OFFSET 8 //This pin is not connected on either board. +#define PIN_15_OFFSET 9 +#define PIN_16_OFFSET 10 +#define PIN_17_OFFSET 11 +#define PIN_18_OFFSET 12 +#define PIN_19_OFFSET 13 + +// These are *PIN* numbers, not +// GPIO Offset Numbers. +#define PIN_SPI1_SCK (13u) +#define PIN_SPI1_MISO (12u) +#define PIN_SPI1_MOSI (11u) +#define PIN_SPI1_SS0 (10u) +#define PIN_SPI1_SS1 (14u) +#define PIN_SPI1_SS2 (15u) +#define PIN_SPI1_SS3 (16u) + +#define SS_PIN_TO_CS_ID(x) \ + ((x==PIN_SPI1_SS0 ? 0 : \ + (x==PIN_SPI1_SS1 ? 1 : \ + (x==PIN_SPI1_SS2 ? 2 : \ + (x==PIN_SPI1_SS3 ? 3 : \ + -1))))) + + +// These buttons are present only on the Freedom E300 Arty Dev Kit. +#ifdef HAS_BOARD_BUTTONS +#define BUTTON_0_OFFSET 15 +#define BUTTON_1_OFFSET 30 +#define BUTTON_2_OFFSET 31 + +#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) + +#endif + +#define HAS_HFXOSC 1 +#define HAS_LFROSC_BYPASS 1 + +#define RTC_FREQ 32768 + +void write_hex(int fd, uint32_t hex); + +#endif /* _SIFIVE_HIFIVE1_H */ diff --git a/hello-world/bsp/env/iss/init.c b/hello-world/bsp/env/iss/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/hello-world/bsp/env/iss/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/hello-world/bsp/env/iss/link.lds b/hello-world/bsp/env/iss/link.lds new file mode 100644 index 0000000..bc60026 --- /dev/null +++ b/hello-world/bsp/env/iss/link.lds @@ -0,0 +1,168 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /*flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M*/ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/hello-world/bsp/env/iss/openocd.cfg b/hello-world/bsp/env/iss/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/hello-world/bsp/env/iss/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/hello-world/bsp/env/iss/platform.h b/hello-world/bsp/env/iss/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/hello-world/bsp/env/iss/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/hello-world/bsp/env/start.S b/hello-world/bsp/env/start.S new file mode 100644 index 0000000..b526411 --- /dev/null +++ b/hello-world/bsp/env/start.S @@ -0,0 +1,54 @@ +// See LICENSE for license details. + + .section .init + .globl _start + .type _start,@function + +_start: + la gp, _gp + la sp, _sp + + /* Load data section */ + la a0, _data_lma + la a1, _data + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start + la a1, _end + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + + /* Call global constructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + +#ifndef __riscv_float_abi_soft + /* Enable FPU */ + li t0, MSTATUS_FS + csrs mstatus, t0 + csrr t1, mstatus + and t1, t1, t0 + beqz t1, 1f + fssr x0 +1: +#endif + + /* argc = argv = 0 */ + li a0, 0 + li a1, 0 + call main + tail exit diff --git a/hello-world/bsp/include/sifive/bits.h b/hello-world/bsp/include/sifive/bits.h new file mode 100644 index 0000000..e550f80 --- /dev/null +++ b/hello-world/bsp/include/sifive/bits.h @@ -0,0 +1,35 @@ +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#ifdef __riscv64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/hello-world/bsp/include/sifive/const.h b/hello-world/bsp/include/sifive/const.h new file mode 100644 index 0000000..3e0a681 --- /dev/null +++ b/hello-world/bsp/include/sifive/const.h @@ -0,0 +1,17 @@ +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/hello-world/bsp/include/sifive/devices/aon.h b/hello-world/bsp/include/sifive/devices/aon.h new file mode 100644 index 0000000..63f1db3 --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_AON_H +#define _SIFIVE_AON_H + +/* Register offsets */ + +#define AON_WDOGCFG 0x000 +#define AON_WDOGCOUNT 0x008 +#define AON_WDOGS 0x010 +#define AON_WDOGFEED 0x018 +#define AON_WDOGKEY 0x01C +#define AON_WDOGCMP 0x020 + +#define AON_RTCCFG 0x040 +#define AON_RTCLO 0x048 +#define AON_RTCHI 0x04C +#define AON_RTCS 0x050 +#define AON_RTCCMP 0x060 + +#define AON_BACKUP0 0x080 +#define AON_BACKUP1 0x084 +#define AON_BACKUP2 0x088 +#define AON_BACKUP3 0x08C +#define AON_BACKUP4 0x090 +#define AON_BACKUP5 0x094 +#define AON_BACKUP6 0x098 +#define AON_BACKUP7 0x09C +#define AON_BACKUP8 0x0A0 +#define AON_BACKUP9 0x0A4 +#define AON_BACKUP10 0x0A8 +#define AON_BACKUP11 0x0AC +#define AON_BACKUP12 0x0B0 +#define AON_BACKUP13 0x0B4 +#define AON_BACKUP14 0x0B8 +#define AON_BACKUP15 0x0BC + +#define AON_PMUWAKEUPI0 0x100 +#define AON_PMUWAKEUPI1 0x104 +#define AON_PMUWAKEUPI2 0x108 +#define AON_PMUWAKEUPI3 0x10C +#define AON_PMUWAKEUPI4 0x110 +#define AON_PMUWAKEUPI5 0x114 +#define AON_PMUWAKEUPI6 0x118 +#define AON_PMUWAKEUPI7 0x11C +#define AON_PMUSLEEPI0 0x120 +#define AON_PMUSLEEPI1 0x124 +#define AON_PMUSLEEPI2 0x128 +#define AON_PMUSLEEPI3 0x12C +#define AON_PMUSLEEPI4 0x130 +#define AON_PMUSLEEPI5 0x134 +#define AON_PMUSLEEPI6 0x138 +#define AON_PMUSLEEPI7 0x13C +#define AON_PMUIE 0x140 +#define AON_PMUCAUSE 0x144 +#define AON_PMUSLEEP 0x148 +#define AON_PMUKEY 0x14C + +#define AON_LFROSC 0x070 +/* Constants */ + +#define AON_WDOGKEY_VALUE 0x51F15E +#define AON_WDOGFEED_VALUE 0xD09F00D + +#define AON_WDOGCFG_SCALE 0x0000000F +#define AON_WDOGCFG_RSTEN 0x00000100 +#define AON_WDOGCFG_ZEROCMP 0x00000200 +#define AON_WDOGCFG_ENALWAYS 0x00001000 +#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 +#define AON_WDOGCFG_CMPIP 0x10000000 + +#define AON_RTCCFG_SCALE 0x0000000F +#define AON_RTCCFG_ENALWAYS 0x00001000 +#define AON_RTCCFG_CMPIP 0x10000000 + +#define AON_WAKEUPCAUSE_RESET 0x00 +#define AON_WAKEUPCAUSE_RTC 0x01 +#define AON_WAKEUPCAUSE_DWAKEUP 0x02 +#define AON_WAKEUPCAUSE_AWAKEUP 0x03 + +#define AON_RESETCAUSE_POWERON 0x0000 +#define AON_RESETCAUSE_EXTERNAL 0x0100 +#define AON_RESETCAUSE_WATCHDOG 0x0200 + +#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF +#define AON_PMUCAUSE_RESETCAUSE 0xFF00 + +#endif /* _SIFIVE_AON_H */ diff --git a/hello-world/bsp/include/sifive/devices/clint.h b/hello-world/bsp/include/sifive/devices/clint.h new file mode 100644 index 0000000..cd3e0c7 --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/hello-world/bsp/include/sifive/devices/gpio.h b/hello-world/bsp/include/sifive/devices/gpio.h new file mode 100644 index 0000000..f7f0acb --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/hello-world/bsp/include/sifive/devices/otp.h b/hello-world/bsp/include/sifive/devices/otp.h new file mode 100644 index 0000000..93833e2 --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_OTP_H +#define _SIFIVE_OTP_H + +/* Register offsets */ + +#define OTP_LOCK 0x00 +#define OTP_CK 0x04 +#define OTP_OE 0x08 +#define OTP_SEL 0x0C +#define OTP_WE 0x10 +#define OTP_MR 0x14 +#define OTP_MRR 0x18 +#define OTP_MPP 0x1C +#define OTP_VRREN 0x20 +#define OTP_VPPEN 0x24 +#define OTP_A 0x28 +#define OTP_D 0x2C +#define OTP_Q 0x30 +#define OTP_READ_TIMINGS 0x34 + +#endif diff --git a/hello-world/bsp/include/sifive/devices/plic.h b/hello-world/bsp/include/sifive/devices/plic.h new file mode 100644 index 0000000..e1ca5d6 --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/hello-world/bsp/include/sifive/devices/prci.h b/hello-world/bsp/include/sifive/devices/prci.h new file mode 100644 index 0000000..1a3de58 --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PRCI_H +#define _SIFIVE_PRCI_H + +/* Register offsets */ + +#define PRCI_HFROSCCFG (0x0000) +#define PRCI_HFXOSCCFG (0x0004) +#define PRCI_PLLCFG (0x0008) +#define PRCI_PLLDIV (0x000C) +#define PRCI_PROCMONCFG (0x00F0) + +/* Fields */ +#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) +#define ROSC_TRIM(x) (((x) & 0x1F) << 16) +#define ROSC_EN(x) (((x) & 0x1 ) << 30) +#define ROSC_RDY(x) (((x) & 0x1 ) << 31) + +#define XOSC_EN(x) (((x) & 0x1) << 30) +#define XOSC_RDY(x) (((x) & 0x1) << 31) + +#define PLL_R(x) (((x) & 0x7) << 0) +// single reserved bit for F LSB. +#define PLL_F(x) (((x) & 0x3F) << 4) +#define PLL_Q(x) (((x) & 0x3) << 10) +#define PLL_SEL(x) (((x) & 0x1) << 16) +#define PLL_REFSEL(x) (((x) & 0x1) << 17) +#define PLL_BYPASS(x) (((x) & 0x1) << 18) +#define PLL_LOCK(x) (((x) & 0x1) << 31) + +#define PLL_R_default 0x1 +#define PLL_F_default 0x1F +#define PLL_Q_default 0x3 + +#define PLL_REFSEL_HFROSC 0x0 +#define PLL_REFSEL_HFXOSC 0x1 + +#define PLL_SEL_HFROSC 0x0 +#define PLL_SEL_PLL 0x1 + +#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) +#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) + +#define PROCMON_DIV(x) (((x) & 0x1F) << 0) +#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) +#define PROCMON_EN(x) (((x) & 0x1) << 16) +#define PROCMON_SEL(x) (((x) & 0x3) << 24) +#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) + +#define PROCMON_SEL_HFCLK 0 +#define PROCMON_SEL_HFXOSCIN 1 +#define PROCMON_SEL_PLLOUTDIV 2 +#define PROCMON_SEL_PROCMON 3 + +#endif // _SIFIVE_PRCI_H diff --git a/hello-world/bsp/include/sifive/devices/pwm.h b/hello-world/bsp/include/sifive/devices/pwm.h new file mode 100644 index 0000000..067889a --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PWM_H +#define _SIFIVE_PWM_H + +/* Register offsets */ + +#define PWM_CFG 0x00 +#define PWM_COUNT 0x08 +#define PWM_S 0x10 +#define PWM_CMP0 0x20 +#define PWM_CMP1 0x24 +#define PWM_CMP2 0x28 +#define PWM_CMP3 0x2C + +/* Constants */ + +#define PWM_CFG_SCALE 0x0000000F +#define PWM_CFG_STICKY 0x00000100 +#define PWM_CFG_ZEROCMP 0x00000200 +#define PWM_CFG_DEGLITCH 0x00000400 +#define PWM_CFG_ENALWAYS 0x00001000 +#define PWM_CFG_ONESHOT 0x00002000 +#define PWM_CFG_CMP0CENTER 0x00010000 +#define PWM_CFG_CMP1CENTER 0x00020000 +#define PWM_CFG_CMP2CENTER 0x00040000 +#define PWM_CFG_CMP3CENTER 0x00080000 +#define PWM_CFG_CMP0GANG 0x01000000 +#define PWM_CFG_CMP1GANG 0x02000000 +#define PWM_CFG_CMP2GANG 0x04000000 +#define PWM_CFG_CMP3GANG 0x08000000 +#define PWM_CFG_CMP0IP 0x10000000 +#define PWM_CFG_CMP1IP 0x20000000 +#define PWM_CFG_CMP2IP 0x40000000 +#define PWM_CFG_CMP3IP 0x80000000 + +#endif /* _SIFIVE_PWM_H */ diff --git a/hello-world/bsp/include/sifive/devices/spi.h b/hello-world/bsp/include/sifive/devices/spi.h new file mode 100644 index 0000000..916d86b --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + + +#endif /* _SIFIVE_SPI_H */ diff --git a/hello-world/bsp/include/sifive/devices/uart.h b/hello-world/bsp/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/hello-world/bsp/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/hello-world/bsp/include/sifive/sections.h b/hello-world/bsp/include/sifive/sections.h new file mode 100644 index 0000000..848c237 --- /dev/null +++ b/hello-world/bsp/include/sifive/sections.h @@ -0,0 +1,16 @@ +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/hello-world/bsp/libwrap/libwrap.mk b/hello-world/bsp/libwrap/libwrap.mk new file mode 100644 index 0000000..313ed00 --- /dev/null +++ b/hello-world/bsp/libwrap/libwrap.mk @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_LIBWRAP +_SIFIVE_MK_LIBWRAP := # defined + +LIBWRAP_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +LIBWRAP_DIR := $(LIBWRAP_DIR:/=) + +LIBWRAP_SRCS := \ + stdlib/malloc.c \ + sys/open.c \ + sys/lseek.c \ + sys/read.c \ + sys/write.c \ + sys/fstat.c \ + sys/stat.c \ + sys/close.c \ + sys/link.c \ + sys/unlink.c \ + sys/execve.c \ + sys/fork.c \ + sys/getpid.c \ + sys/kill.c \ + sys/wait.c \ + sys/isatty.c \ + sys/times.c \ + sys/sbrk.c \ + sys/_exit.c \ + misc/write_hex.c + +LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f)) +LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o) + +LIBWRAP_SYMS := malloc free \ + open lseek read write fstat stat close link unlink \ + execve fork getpid kill wait \ + isatty times sbrk _exit + +LIBWRAP := libwrap.a + +LINK_DEPS += $(LIBWRAP) + +LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s)) +LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group + +CLEAN_OBJS += $(LIBWRAP_OBJS) + +$(LIBWRAP_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(LIBWRAP): $(LIBWRAP_OBJS) + $(AR) rcs $@ $^ + +endif # _SIFIVE_MK_LIBWRAP diff --git a/hello-world/bsp/libwrap/misc/write_hex.c b/hello-world/bsp/libwrap/misc/write_hex.c new file mode 100644 index 0000000..e678bdc --- /dev/null +++ b/hello-world/bsp/libwrap/misc/write_hex.c @@ -0,0 +1,19 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "platform.h" + +void write_hex(int fd, uint32_t hex) +{ + uint8_t ii; + uint8_t jj; + char towrite; + write(fd , "0x", 2); + for (ii = 8 ; ii > 0; ii--) { + jj = ii - 1; + uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4)); + towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA)); + write(fd, &towrite, 1); + } +} diff --git a/hello-world/bsp/libwrap/stdlib/malloc.c b/hello-world/bsp/libwrap/stdlib/malloc.c new file mode 100644 index 0000000..8f4f432 --- /dev/null +++ b/hello-world/bsp/libwrap/stdlib/malloc.c @@ -0,0 +1,17 @@ +/* See LICENSE for license details. */ + +/* These functions are intended for embedded RV32 systems and are + obviously incorrect in general. */ + +void* __wrap_malloc(unsigned long sz) +{ + extern void* sbrk(long); + void* res = sbrk(sz); + if ((long)res == -1) + return 0; + return res; +} + +void __wrap_free(void* ptr) +{ +} diff --git a/hello-world/bsp/libwrap/sys/_exit.c b/hello-world/bsp/libwrap/sys/_exit.c new file mode 100644 index 0000000..7261891 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/_exit.c @@ -0,0 +1,17 @@ +/* See LICENSE of license details. */ + +#include +#include "platform.h" + +void __wrap__exit(int code) +{ +//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); + const char message[] = "\nProgam has exited with code:"; +//*leds = (~(code)); + + write(STDERR_FILENO, message, sizeof(message) - 1); + write_hex(STDERR_FILENO, code); + write(STDERR_FILENO, "\n", 1); + + for (;;); +} diff --git a/hello-world/bsp/libwrap/sys/close.c b/hello-world/bsp/libwrap/sys/close.c new file mode 100644 index 0000000..e4f8e14 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/close.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_close(int fd) +{ + return _stub(EBADF); +} diff --git a/hello-world/bsp/libwrap/sys/execve.c b/hello-world/bsp/libwrap/sys/execve.c new file mode 100644 index 0000000..6178a01 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/execve.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_execve(const char* name, char* const argv[], char* const env[]) +{ + return _stub(ENOMEM); +} diff --git a/hello-world/bsp/libwrap/sys/fork.c b/hello-world/bsp/libwrap/sys/fork.c new file mode 100644 index 0000000..13a3e65 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/fork.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int fork(void) +{ + return _stub(EAGAIN); +} diff --git a/hello-world/bsp/libwrap/sys/fstat.c b/hello-world/bsp/libwrap/sys/fstat.c new file mode 100644 index 0000000..6ea3e6a --- /dev/null +++ b/hello-world/bsp/libwrap/sys/fstat.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +int __wrap_fstat(int fd, struct stat* st) +{ + if (isatty(fd)) { + st->st_mode = S_IFCHR; + return 0; + } + + return _stub(EBADF); +} diff --git a/hello-world/bsp/libwrap/sys/getpid.c b/hello-world/bsp/libwrap/sys/getpid.c new file mode 100644 index 0000000..5aa510b --- /dev/null +++ b/hello-world/bsp/libwrap/sys/getpid.c @@ -0,0 +1,6 @@ +/* See LICENSE of license details. */ + +int __wrap_getpid(void) +{ + return 1; +} diff --git a/hello-world/bsp/libwrap/sys/isatty.c b/hello-world/bsp/libwrap/sys/isatty.c new file mode 100644 index 0000000..55eab0a --- /dev/null +++ b/hello-world/bsp/libwrap/sys/isatty.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */ + +#include + +int __wrap_isatty(int fd) +{ + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + return 1; + + return 0; +} diff --git a/hello-world/bsp/libwrap/sys/kill.c b/hello-world/bsp/libwrap/sys/kill.c new file mode 100644 index 0000000..9c56632 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/kill.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_kill(int pid, int sig) +{ + return _stub(EINVAL); +} diff --git a/hello-world/bsp/libwrap/sys/link.c b/hello-world/bsp/libwrap/sys/link.c new file mode 100644 index 0000000..9340cad --- /dev/null +++ b/hello-world/bsp/libwrap/sys/link.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_link(const char *old_name, const char *new_name) +{ + return _stub(EMLINK); +} diff --git a/hello-world/bsp/libwrap/sys/lseek.c b/hello-world/bsp/libwrap/sys/lseek.c new file mode 100644 index 0000000..46f58fa --- /dev/null +++ b/hello-world/bsp/libwrap/sys/lseek.c @@ -0,0 +1,14 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +off_t __wrap_lseek(int fd, off_t ptr, int dir) +{ + if (isatty(fd)) + return 0; + + return _stub(EBADF); +} diff --git a/hello-world/bsp/libwrap/sys/open.c b/hello-world/bsp/libwrap/sys/open.c new file mode 100644 index 0000000..d1871f9 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/open.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_open(const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/hello-world/bsp/libwrap/sys/openat.c b/hello-world/bsp/libwrap/sys/openat.c new file mode 100644 index 0000000..7f1c945 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/openat.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_openat(int dirfd, const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/hello-world/bsp/libwrap/sys/read.c b/hello-world/bsp/libwrap/sys/read.c new file mode 100644 index 0000000..4e57f08 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/read.c @@ -0,0 +1,30 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_read(int fd, void* ptr, size_t len) +{ + uint8_t * current = (uint8_t *)ptr; + volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + + ssize_t result = 0; + + if (isatty(fd)) { + for (current = (uint8_t *)ptr; + (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); + current ++) { + *current = *uart_rx; + result++; + } + return result; + } + + return _stub(EBADF); +} diff --git a/hello-world/bsp/libwrap/sys/sbrk.c b/hello-world/bsp/libwrap/sys/sbrk.c new file mode 100644 index 0000000..6e6b36a --- /dev/null +++ b/hello-world/bsp/libwrap/sys/sbrk.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include + +void *__wrap_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} diff --git a/hello-world/bsp/libwrap/sys/stat.c b/hello-world/bsp/libwrap/sys/stat.c new file mode 100644 index 0000000..1ccc2f4 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/stat.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +int __wrap_stat(const char* file, struct stat* st) +{ + return _stub(EACCES); +} diff --git a/hello-world/bsp/libwrap/sys/stub.h b/hello-world/bsp/libwrap/sys/stub.h new file mode 100644 index 0000000..fb5e5be --- /dev/null +++ b/hello-world/bsp/libwrap/sys/stub.h @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ +#ifndef _SIFIVE_SYS_STUB_H +#define _SIFIVE_SYS_STUB_H + +static inline int _stub(int err) +{ + return -1; +} + +#endif /* _SIFIVE_SYS_STUB_H */ diff --git a/hello-world/bsp/libwrap/sys/times.c b/hello-world/bsp/libwrap/sys/times.c new file mode 100644 index 0000000..26a9566 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/times.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +clock_t __wrap_times(struct tms* buf) +{ + return _stub(EACCES); +} diff --git a/hello-world/bsp/libwrap/sys/unlink.c b/hello-world/bsp/libwrap/sys/unlink.c new file mode 100644 index 0000000..b62b1ba --- /dev/null +++ b/hello-world/bsp/libwrap/sys/unlink.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_unlink(const char* name) +{ + return _stub(ENOENT); +} diff --git a/hello-world/bsp/libwrap/sys/wait.c b/hello-world/bsp/libwrap/sys/wait.c new file mode 100644 index 0000000..ea3225b --- /dev/null +++ b/hello-world/bsp/libwrap/sys/wait.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int wait(int* status) +{ + return _stub(ECHILD); +} diff --git a/hello-world/bsp/libwrap/sys/write.c b/hello-world/bsp/libwrap/sys/write.c new file mode 100644 index 0000000..d00eb17 --- /dev/null +++ b/hello-world/bsp/libwrap/sys/write.c @@ -0,0 +1,29 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_write(int fd, const void* ptr, size_t len) +{ + const uint8_t * current = (const char *)ptr; + + if (isatty(fd)) { + for (size_t jj = 0; jj < len; jj++) { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = current[jj]; + + if (current[jj] == '\n') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = '\r'; + } + } + return len; + } + + return _stub(EBADF); +} diff --git a/hello-world/hello b/hello-world/hello new file mode 100755 index 0000000000000000000000000000000000000000..74933cfa158c58fcfb3099cbd16712939d7f3066 GIT binary patch literal 205008 zcmeEueOwb)*6^JqlOc#T7$l(3BBP+JWl{X7ZjFf$1`sV;1-07NPL+1It+iY0x?8ry zWQYMQ;-C>fwus;C*0oU0mOc``<0n$9psrOk#Z>zNv_guK@SZyZYTfSh?EAjYpKX7b znLGEMd+s^so_p@O=brcUDG3BYpn?A+=m#XeX~QN$p)yn|yiY`7NQ%awAfy(*D{%{L z82(#$5h46X;vy&)+IQd=l(q1pHmpv85dM?n5}_S_Kk9PcB3m*JOR{`-Xj zzfj;83j9KWUnuYk1%9ExFBJHN0>4n;7Yh7BfnO-_3kCjHDPZ-ldVx0(!_~T~7gU6y zPu+%)isVdI63RKws}6*6dGvDcyh>i=W5c=Q%_lFPzS?-B>E^lH=f7+I{$ls#yH~tde?K~G z;t!*h6MeG*cKq*^!zS9o5#rZLvVLDIiP@wL*OlpJ&OA5srMU0oB=a}T4_{EWU}oC6 zw3pJqPnRcdNsLH3nv{^-oV;RI_bmC6ElVPn9$lL7eDm`wUg&;7vF!IKEQTmXXzi-- zW)wt6@9E_jdej{+{2Ot{JN|$)(&RNp)_Kb*w*;5tXO6<(r0@i99_KYzuMui#xC!(1 z%hqKP{_@7~(@1Hp2Q0bz_egy^N_~fp*yE+cWnP|&_mT;f908>pXVRngc*pAJPAN6h zVHmc|tH~DIaqmh;*LmBO+AuZ10lL52u8i?FFdFWA?Mw0GL;YaLJXI$^#eE%4j52c! zJIswRuKvZI^apJojFKMrF~-`1M}q6^h?BxtRBPNr=q#7eaz~uXtQMZO))Hu7Y~hVa zDU4;*$I#B?EjlH(=Cc_D5WE4kJL3Eg{A-zpd#fMo|6d5>SIMu1f00E1ukOGo?$A+n zcjz(a@6Zun-T@B5uS^&b#vaPN#)$YXX{4+x)_qfwL-BH1-%%@l$ki>4jPC-9cd@^7 z1Lop$c{*@8>du{N8-WNsiZ0`5QCQSUyxmcm-F-ClBZZMVb#AYr7)rf4l!}t| zRam9_9d7Ym?8Ugx;oi%zT`h>G-Xw#Ic?wCPRzFk?C&4hi{V=`GSsix?bT{?4^Tz^r z7p=-}E;)blTw_yK5YYQBJ?i7TbXeV8I{f@yI{M2W>2Y^{1nloh$Hd=-=UzHm=E3}w zj;Zt1nAuB|1YqAajyBy@kxdeez4%Slj_z8v(2EJ6;la74J1VfC>GS z5jhZ#VZwJ2PQ2Ioy1SP^M^hu_2QJE9v>bRbb(Q>T_?3vu$rrOgqW1IxFM8?lx?Vc$ zeDC-J?0Q)YwCxq305)~KK=s}T4%0lo7x!0b;;B@LbH^Qw>-~E1y?`Ci3`uqmzSHYT z#~J|sjRszVo}kCbgxZ1>hkrQ$$9&$SqEbnAnR|@N8i}mHC*Dj=udr^76Q7xm;3HzB<##0-m>=`S_&;Y)d zY#?pDDl-E*|I6MTak$-BkQbTP`2}@{4wHE;cF>t)?(`mnxg(T+M%@8wcpi+4v;#aZ zyNL=3eFPfdB~T4>B(oIvw3E8NU1c^4y={y;ABQ1Hp*JJYRyw+_w|@L0q22&S(t{LY z0~JVp0_02a>aQ>c?6VzmDf6)hQ-dAsmSGr`Tr$_LM9)N-agCyUjNSMHMyT~L4)~i# zJ)o1Fx(+WMtB51!EU9>?2BQED?>vs7I~yr10Ul^8&=pE9Py(IAwki?{bMYt8XLfjR zfo_li1>#{9>3JGfgMO{dUZb!E7HBgtkMUa6p~W>03M#Ws6%?Evso(OUcn$qMIDIxPpBkJzcdhNs~v7Qs!JyjS{ zya)P(c{9G8K;NgnH2>WEnTtlk+*!Ix-W+~jTv=19ly&p#f{rgaPLGp;{th4j14)5; zV6>Il(5uIw7j?w)P0PmP^{y;6eEzaWAkpJK?tK&%raOj&VeV27XbD&uJrw}g1e_P) zj^0R473yXQwDo8}5`^_#`=Bpz4NpEf=lHyav^u2xFf1zPP|m8bQnSWlNJ`Fb%$~rQ%Ac^AB%8J~juETvzV^EjuAz zN36@z`O6!^>ym5cR3V?98Df7Y&2ylS8m>$m9zQf`U6NQ2x89X8(2nr`X^*h3xZN;+ zL8ES=2pjbT>dIf5Z=;YF{xu^35B$3$4(6{HKkcFl`E2rRaNu_v zB|~DF2m_aGt;NqD!Fq}@TwQEq2<1p-Ywb_#gBJ1Z%zYT9%(IE&-PDYS%j$Ydp?@v| zv|QE07(Cp=qdh;M!4#^uPo%=G>GY^QUIH1WW1V60hURZzoOfMNBDMw!UilXaW-Jis zhi3ww1tM30+b}M`2UEKL3D)8&u^&vkC#Mq#a~X5^KGk8xQB244vnLi~ay^y~-vcXP zykLJh6>jejk?8P%uEKg}X)MMx9^0&1ykbjXRX4(Xb-vtR7uFqUkIOtl9njj+NSRbMw~P{_hvCv=5AOz*@%Rvqcg>9fuUC)BiMu^7L~-EHU5zW|mH&qzF?vX$l@K zU<{bsrVz^ORHho_2%dIPTjRuERfZa2dHy-unFdRCSb}JEFTYCacZFkU9HrsLjvBzu zFo|S531osnPw3A~?aWYdR9MlJkzlujRuSxT{Xg4LOuE(G*T zfbE3K@%%RlHoaJOkYPjIK*I-Z@Y5vF6AzE04qJ2{C+oh8e=*Jn{|(Mk%x{LJ@IIi< zYhl;`H{uxoV!Zl@Ja~96iguRcnDGFZRtFfgo;l5IoOOQI)@SH30UkO^=Ap-do{R=P z83uF?KMx%F(ravS5OkohI(b$nRB{S^{UpG)7e6V+kp1#E`X37Y^+`nWqdZp($mc&W z<(5v`#q6f;c#jnu8L%1EG&~!bFJT`tohetl5njm6mxVcz`$>7gf|-M4eTXxPm`vLJ>cH(Q}sR2Pp}?io|kfl1R{aZuM7)&O6PCT zhu6s)qD<{!#nZ)k9=Uma+>)gQwd<_mT=gWvKjP#eQyKRrNb@v=3&PfE^tOJ`0$z*l$5&|HdfcS5A+C-zfMSN1~B1 z%VEDwwxc%(i#@wO2x$_Z_LnT_e~R26a$YQ>O0}n#oWHNnpkJMTM2$+GCFf0DedVS) zNpe-R1^3T$@zmOgC=+o;?0+;dp7g0xWt-#%>x#SuBO*2j&uhb%ql z64wwbg(>Cue#sXbz{=~2=BfJVC=)%ZD;i)%C+diV0=;5}Pdu5hS3h=2V!R^ZgkCX) zV?wSBV2JUvy6vE;sXs;3nBtPF+Mo?9U>hnnMvMeE6^u%<7cd|THf^$Lx=SsBL1hCSFgc)A(R?9$ zG={%%vVI!ZksE#urLg0Mzi^oh>dBVc*JX+S_v5%~eVi5cj6A1z4lWVP94iOPxLZ?8 z2!C-#MlK9L4M-xuF+J8~)<&F6K0c>G-l#Ac;x(4eMQm^(dMW;UEtZ-xkefvxmzyU_ zIoV08alfN)oweR(bda#?4Wn4jC09{zQf!_J-j#B;&?Qk(Sz#QbBD0iZi@`d1kz+>c z$ya!v!xEJ=i&FXcWGN0@VnV91+_AZV1e>)&!jZ-X5`BC3QhrFyx~#!Po!eE*NrHDp zqAzUaE{dqP5sZQH*DtqET{XG+ZKb?%+C|OfnO737PHq67k^FltwjHLfns9z{v*z-& zi};I3f&DLtay}8-;JO>7VqNg>oKJ3=cRKB)ygB0BoJN(5j3$!EWY6N@ukgH0<~Gfj zEc!m_rQ~zTcn-_rjbr1HCzw4C0Xy1GyRoGXvG3kRM(dY|U7t=waM2CxHkavRUp$oP*@Wg;wQ;=M+{d>}gdOU6q-87= z>t~iN(JqV+i0|B9V!hZ9;J6rvZIp|(bBk3ih2SshkP@c~7`D~r!?(N)Gu|x4o`AbM;@cejh)!Pg#PB-K=T&W4SDr=Luxg%Ai2@&?s7`Dv?*x1M<8&7FT z)&*}Zb%2jc&Vg@1J4`IO10`#yPwc#0yMU)!Dd+8*clef31ZXO1mu-GLnkGhrXVC zHKtdTyAhYjrR>WYh*e2LjDNKt>7H4L|6^Sr>)M85&D*rc7`E0mMx3SQh^#pA$u+7l zE;Bu%P?N(J-3-#nO27-jMSIeta#_?BR&IWdVBhXS?6%)Lq3*T6pz`~MmPYykHAEWS z3}*{7)ch8PU^mJGjr%Pqtx)xH0II6Rc&RAI6Go^V6vw{fMgpdz-H(f3T%l0}ptmj5rpB+@UhV_Z{M_SGQC36Zv9yL; zn;anxR*Xq;%RhwQ(w3vVE2v*)=`c0%Q8|0c=OOtCiN|e1Kb>G2c0^^)?kk+>Q9DgH zZ%jW{K#6kDcD3u%Qu7yfF5?)bDfFz#%=_?&G{P5o(%67zAEB4OW+?d8e?pe}T}(M= z(?)OSGAcJOF7&7~^I~&2?K$A$>*1bsHlPbF=7?m>g;;XA?wmDhn?Uhjx#gkI-zk{y zc&7ZVyJS`6^tdQ9`}Q^KuQsLD&ynKLQJ5e8H`Zm9%WJhc za;pTPEn70O_92?GfgNc>H2m!*;TQgP%itIOc1z(G{&q{?7yfn=@C$#t5&Xj6x-7n{ zYY4xELl-viTS(%3-~Vu=-KOBS=o2DWL2v}^EF$XZ`b~~*M@BXapfCW6Qi^J z^x}HAEBvP`WAwR)*GAX3JL2Xmqq6hBddI8d*eJ0!UQMD*(VW295~@Sq&|a)u0Ne}i z5;z3*Q2UO!g4&R(0ZR$Dh&CBFw;`yjMZ?%65-J-kP5Oh18kJ5he!dxm-NO_x)AADBE&ehdW1B}Fv1w68zKD_ zF~az(>fzFHhT+C>y5Z6%iQ&d4tAp3VN-e_BzA*O-*r%ReZs&cfA8V*x=U7)yBug$! zE=uYo=OoRN(-9`{vP+DN3>DRa_2&~is8GxL4U$wcbn#Y1m%Kt;wpKb0F`>*ZAC9W5 zXP^=ClCCxl*Z3;;8_nIlfy;_+~yQX(ZzJ&f?|8q)J{a zsbQpNC%7sOs9t;KF+R{4J9 z2AGoF(oSEC4X;9zKri{C0$)v|^Ahzv_DyRVRWHY*VPG*FmRz^bWMFi_dyZm*&q$${WGqK zIdJgQ&(WWK-Vc@gZPb-d*+|6tW$9x5dbPrd4A9Jz?hL*6xbtzpQF|HZ*VfT|o}Y9# zRS?X}I)hfi(W=-xz$OYDn5(KQy*j-e-evgB;;8ZCulVV{wLwW(*XK9jEl<}8-%aR5 z?E}p5iOE*x3R8CC=&6b`m1oy01YT27Ef!`|BCJ9#VC;Fd{gEYA%HG_dVD^Z8KpB8&T z7Wav==mY&~K+nE7{v`BUdEzotdFnP(dFC!tdG?46d@g}q5-)@Ing80;%eBtx{rAM4 zUanbW=l|q^lN_at-FZ(oAk}zx2An3@fNwF!sofyyJQX9ylFojSF`g$!AVJPM@~cZt zFs48<2J08zMai%Z5}w_Z%xR`7JV#+I@VN&&>NjPQ8n*BrVr7G(|D4Qc$dsBU$(1>C zuFn20gG*_tggH|xqgLX-Nkj6*IjAPDt;k3;c|kH0{Xey zzVXdJlyXryK8o8Ze@tmF4x>&o@`UfxDw{4dWfuYabGKm>K1AjDyUfiiH?CGTAHCeZ zG0eZ5OD2rqPt@-1byHzheG&&TOoe-E1kvMryLt^vHo6o%SOsL1^=beFDH&j8Z2540W zt!f5ZtpJ*!@!5%NVzK1t%ze)UK7;E9p7`^rKc0EG&Wod$^=`v4q|Bb;#;; zw(c9mF4|774ON+Y`+x`UcswdnDdXSq3^C~0z&p;**OW1S@kxVRQ z)d{lh+vyA5xNENAJT>00k{hibn^?Yr0&5&}AOpU+Y`JuIev6mYw*|quk+es>d&o^M zFJCr@{mvG+B)Ht%t<_wN&1DFfMfD(yp!17r&oP?qSi_4lD{8D8=@y4dn8(+BCG!o* z)AvbgULHESJgR0`xuhm|*3?fIgMJ(N>F)fa-nL^LoTIphjJJ`#yNBF{6ND6<^PiMg zVf#KE(*Q|h^E_bZ@YIVkHuoOPxl|eNI|8xBd+2hGA|bf=a?ap{kYJTh^`JlaH)s1P z=5P&FZ=HDS>Kmt4oPl`});bo?uTs-n&jT+u0|dbPhy%lm&6`iKAKa5j9WsE6q^#O4 z5qbWg{ewABOkoI$dX6d2N!O*dRHSQm;MxgS-#Q`o^`LI6?E8fncg3xjuKjUw=rKN9 zjV52i9`L*A&fDg`E}IJackcN52AjT-WQPqxD!@v2_8b#y?nTqKs|LR)-+Z9V{0UG; z3h@b?e0Tm$@7`lPwQNvPo1lvZVZF0z5atwyj$wavYyi^OQ|B1GdtYj2Pp1$V_KIA> z0nl@Mk!tXp@{tGNJN(8Dx{KHZSTm&Cb*e!s#Q#aAB~qMOgT6G(axUHIKO|?o(nDV@Dv{Hu}k+mGf4bs$=2rHm-Xp47KdaOB@z-Kwrwzqvs`h8(j z!Rj`xK?Q3UUf~p{UIMRqrukxRS#nMM%8tKxz!!pW;8Kqbo@M?HX}W=+H@Z-dUG=ss zEVD_zHtJ`OQ26uNdqH@@Q5*NJ}#8PFJ+& z9}m_%gRtg}FNW1kW^ov=_#z?&tTb5b+FFdKebE`aSoiuG-a#4ZfKFfQeryrBUesL1 z>m!kZHNOR@nMEzKiFGjsp7ew!;~rnc4!MUGXB+epTzl9?T~y7wg-$717&~aQR#G#m z0!m|=6zdj7*88+3_VeEoi(%BOdHooX^1+m5)u&{HaEl`mcV73dAzM#Jn(*yTe~6^>{I{;g;KdGmhDm=~SH z$;WX^Hg~Y(DSzBb@lY$p&$en>;(US}F4(H+FhhLUB9{!0qkID%$6-=8r=PxwJLg1$ z?fWCD1Rsnl8^#e=`765QAH>m}-#IGkcP5mre;Aw8bf=08#Bj@Veyd}jO(k`S)(?SG z8)nCc3XuLm+=rB~a4cQ2kT|-n`DY*@aE!Sc}Af9lq^hD?H6T zvEK^U#ysO3N2-T9OVbyVY z@qFP;?!FB-`F8@4f$ttfASZ*XE`a`lA_x|}1aiOscwmcX`Y!KeGodOMNK4<>^7 zKgzUwXN^rTB&^_WU`zkSjW4Q564sOtp{=Kn^aX1u%U4#yVEdjOaaRI9$000rSHcGP zA@+yu(oN}Q3leH}=4rC=ym)a@2}2}rN;HC=F*r&Xm6Dbl%;IJOLF}+yj3l1+*gg3Du{G@^7p##uS8iD7X5aw95wVyhr8^{wLO? zyD6}PJDxeqN(R3}%Xg{p>`iM}+0pLM$?1}dL>bH)cHT9K$mhFY&vaK!yV|aeiD8G6 zZ$vy3I466~Tj}5U>(qzVFZ!q&+8ig2f?Tmp-}SfYuF_n6>q@&;`6TO4zLq`b`}CKd z@9?h<*nymS_pNAm#v@lDeMsC?EL-D%n>Z< zX(yg%60S(9r=5C(!FJlTGk<0zj%jDx-&BU)SO|8fvR`h3@GJt~Psxwy5W@}r&Vl!j zcpv%D9#Wf1vnui>EWH)!1FQQnM@jlTs7L?pNAEd?KJ=rvlBww5g+8(e)uuiH?Vrc( zdD-1QcJW3@^(<>Cwh)v3LQ@XGOkPN6fQLMu$qn0Objem!QMk{6F*&;4Imdm{e?6;| zrM)$KT{`=$2Wd9kU~a=+wvsWN8kk|qV4&Z^P0YG_b}O|Q_qDo0N6{sJASwV3ySVqh zZhA8itgiWY{Hp_wuAgh0md?&;eXL)vQ2z-v-W&?;Q$=bNxY%L7g4OWJwf_rxJjRY7 zQv?W$+4H`#a^F;4f?1bh{VUKUchJ4i*+7%9HK3C?3OF%qiIfgc7c>&4$itjDtN>mn zVn_qNfJEXPaN)yBkezTd$PV@fchbNd{wcpHPpWQ~B%V8I$N~4+P zomh{NK(&R0s7ImqhqOAxtvx|%aclN-Ut~xw&sid9)9Tr3(59-vueXQJ!g~3@18v%{ zRQ2z*X;mhxCZEReKrd;_a|($KwV|_PbK?n7JHLLL-8x9g2Kgz=&G7{LLpo8J^FRW3 zp8C%z9=3)ZN>0W-ohvLi&(~GVFPCl8vY%TaR*qe?QShWJB(U7=`*)rcZR=aClAM5H z>@%~U%aDN)q3q0a&fVBNAkk6R9+hb4rS0c_UJ|Qbhw+aSC9%_nXFIH5SUW8K`aZ|9 zeh2=WC~=lAIKn>W=aU&ymOeCHoOzqlAD(&QynDdystkZ1fiW%tOaD2Ypj)4HqY5*- zxI>~5<{h5-8d&|KVJ-`+_|k9t`__P-DP}>w!f&Kw7#bKgcF8jc+{G@4Z=tU^wt2hnO6mP&x8DhytVK~I*dqNwjN8%gSFQg|6?!4=P2-? zqP}dsbKbXi2j(|=4(7LD8?3b*V!#3cN#zEE&d3FwkpMdmSd-Xn`B2d|`A*Os56={o z4($W^K|l+vw+7LFyC>+ad;g8zs(KdaHx##d;Gf`q@AgTm1rG)2RqUYvKLzO3EN1MP zN+z1&WFGZ7E6kzd?ckYvj=&??3H`B`UH5saowN29hPot}F209q(r2dg>vN&@J@iu@ z>RjMH3~S9j=aN(pXoo$Z9ZaJ>37w6pwjJt{pfPh1o4kZ*wm#_VXzpBlHO%2$p>KB4 z00-K&RS8qS1!)_8G&j?ZEjW=%&ZX||oi@Q(*Ad_&mw|5_yxO8?<_-cMF9SYa zCV~V1E(3mE2KrCLu?wOXzl@uljWMM^q}~GW{6@5_-;*z3pYhhCo_ujsk*`J6l$zGZ z;b@F#lcGLkX_2$N>4n=kx`9_yM75FcHltnN@!b?*`ED<>qe_*5Jw;!l%mvuPzDbDE zD#+d7@LOm(0g_V@V>8m%x71kkcWFgudEs1ng99%4hnu0qSh9TXG4ez_~Cn zsIJrAKep$$#zh&8k>&u4i>Dj`^eA`0#kkDG%mwVsuVj2sBw`g(Ni3%(=u!1P(gWro zG9fnbCW?LKIHLDZ!StvLN=pK({u~+iIf53vPs6_?b+NX=n&-gh8f#aH{p?Sl(`bZf zYw^5%;QajghSHqq9CDU%k0roxyh^K5-0Aa`MHI426+*<&PtVQqsX43gh1jxqCCf2H zX7H+jOZJP}CE83i8yG32OGXi0EyjJOpjh><2;*PlQP2C9@77r_YT;xd!1?%^9;f+E z?_4{kHpCI^s|$kIX`j{kge#4M6MlO%{QH>@KOmg=U^zJm<{HS!i;)k@iR+n13n>KDhSSj< z+5+d8<9-Y2;!(uj3lHYaf^bZUB0G`5L2nZ1Eh^g?)YZL1`(X?8#<_4DMxjfF+mUwO zC5O3q2j(K&A2>)7&U{6O^dN}_=hDTKh*-r`9YoVOuOx-kIp>9SE=f&EIhj2Nb}zsc zrWky^qISu&mlnk;4nnjG0jG5G#wb%T=mCo>x}m+vey~iB>0RIm=WwhLxh&}jrXr!o z6fEV4Z~J)@IS_#~x_4z$U!z#cM68cnZNm{VVnj(a#K%Ngte1p%kW=lg?Pd71w@hCb z$7QHYZg1z-!Fdsd)FGE{z04xo+k!~wrX#E=40G;pVj$zS8q9) zrNw1K%7MBgx+G$aUzbUt#<7HQs!i+sXZKxeGxVFC5L!4>jHnp40hiFb_C3A~PHZg5 zkjH-+fa+>R+#Ml1;*z;oh?~Oi^da+bfPaA0Z?>~$G6ZYgh?*$VArs7@)|LB=d+Yl6 zY*U~50>mGX+%ewW))$-IjTX+7j^PkzS+$)FIxefQT5d`AoBE30-=#f5XPPY>t95>gbRWrnrFtKU}O4V`H z`_$b0QmfE*)XhU%<5bz^z9xWBSUcZgv6G2&ZK(;Vj-Up;UDa$w{tWwuL!xTQ0DTY9 zJ93ELkwEzvE_7ieDUI&ivSV?$y6{04v9T!vllfR;GQLWLu5 zGT^NRm$)Fx0!oI7C2lBL15p+{L|MSyC(8Lv{f`gIR535PE2iL_KQN7NO227tlK!IRpD?1a#&I3x(kbqaWe+(jnsLIiU7l0*|dn zErsuE)wI%qoZGs+^iW*mI;ons}9SHQf= zq@c>p#tS4Wmv_VX>5WH`)9UhKZ5B)Imq;&0pz<{tsK%of*+dJECOdn0)yLl?BnoxYrQ=>sTu*@i2&K>*vxhz^|I12d04C0n_*eD{?Fc6nO z=)bTV)uRb9iWRT0>_tij_uV#jAt}J#l>t#TFw!=pQji4r{$ve1DfqU9a&B(%hI2=?5%F8%tkQJwzQJ6r0b`4Wn8WFY ze~~vb7VZQ(@Y}NBFY=a6?Xij9G6T5WFYf;mMnXTU3Wk)00jBlnvvr2ViJznoO_~jp=%XBdmpcQdOmEwbQ&(R#7`9(F?-+{;%h&IA=d)Eq2AWvl=c6c*-RnRKj4UmByFgK6s$Ym7P zG_Jn2!)X5tph;Yy9p*x`YQ(uxQz8mKFK>=Eee$%l*Jl2Egc!H`ql75U_tqL}O>nwsDMSK_Y?^8MHRG%Z8;+ zjDNy1H`$^w$s0>ehb$9vDsl{yU^l4178u*IU$QHsN6l78j^xdw&@I`(thIU{*scT8 zz&@wI=YnoFuII6nV0VYcg0J8)*6bU!P#dCUDYr}o^M2QaC0Z4gC1ouxC7a~-TgJfC zQ1I1C*&LU0JQGwmg(9*t)eDb<-y-Bo^dz&eZehGJ%|wi(VCM-eBVmi>{QJ$J#+ z2z8{ud%mH&uk(Fc*#cVbWuhD+G{0zML){STsqkGAFHJWQ*>Drr*h0ZAxeK-XI6Q{x zX|Eo5lpgiRxFmmA_mK=v4$o? zV%P1FTwg;6_rN+d^66D}u}ytpIQP+n*>qOkQTAgB9ouXsy?fJ|>(Sr+oD(>HO=+ zIDeOf_{P92V%|oTTa3*S=vK`u=(CBjvSO_TW+-klocQjr-cV&QEx10L;mDApF_J`1Zj-74#d5+1Kiaf((5V`i5-O6E3EziW9 zUg=>G85qIsjVZN+a~opV&5A%a2$#Hu$NfF#0MMZm(;xG}BJf~<&a6=$I7T^rTDic5 z>!>8x(Efl!?0R{?D~Oy>K1k$)6ll*|l7SC!I%m$2(%WxKG&w5s?fZJtVk(=w^*+oDO7c zOlJTO>j8K=L+Oa|q4X#nM9e~5Y&1mBMnME^_}oxBY*{F@fhbytlN|$bvJoGRnAz}F z)9`Z%=jo`CKhz8%4B{xF5iN15j{^{Mqfz|T{xgbaW? zTU8qv7Tpc_ES~j+GcQw5A5Rra*z;Dz%ZlM9u5Q?RAI)*#2w2?xGWrLQ#Xn;_zfrFD z!F>W(ON{B)DMPa0KQgn6D8WAL$*=w`{Y0nSGkhGO2Kk2EJ*fcc11Z#HgQ!3Js5CHp z6YvW5>TQlvP|ocw-aKLq0oc`!Bi6(3kPq^RudwvhKwtR%FB^ToQH~*|KP`Q(I#`_t zF#X0Qvq6K<4NjU&UA zDcub<;690j9@ME+4O->TF3KXHrF1vEXNIT-8T?5Z`<&mL@N9AXdw&c1T#3?Fq8C@< z+h^5B8cm%?jOuEtpFXd^uH&_Dl;Vgv9gMhY@CEh-azctf#&KnSK?X#V_<$eV7wC~G4)QZFe+Uw-{;fp6)t`SeO2mVl3S26EvOce$6Xa7s)$9eun2)g# ziIGRV64c)DcaB|DtSBUIo2MtR$=wn@eKyji@mtiW-0YBSB`UV40YmT)Ot=l%J>b;6 z#W57``(hKm7DelYw~(MuTnK`=i>9_cBS0vk?3Z{$q&t)){wK6wdYI zDXpBp5`vtey|<0&%LZXN`$n1QUtwLfMny%sE3BC2?X54k@5^Ikd+U4M#4PSLey~<4 zQh$GBihn=NCdcMw01hknIQ7NNDgG~kF8KRyc6KpJ^)KTJeP05*HU{`q#=XRiehM%c zB=-L4y(d2vA?zKQ2iU#PA&g{GDA>Fs2a7gur{8EBM2~#;jiSG=C!n9gzXc1U=Ruzg zHZI*Y1ZLG>oJB_!N)f81g9-ZaU4zTbHXS>+L!RP$AQ+!^T>Iv4!Cxt$mv6pNB*N&f zL6i_~i@p2cW$K2zLh?!uYIOX4Z`1|>a=Kv%ZUZ-*ecD?;=-uI~g0=Cx?8Vu)xdXu< zQzr)>==ni}YX55FEm$Xqu-W_ZjBNej26v48U@(%ZuMaUW>?{gF3+OwKz%5tWEXS}t z@NqEq)JfAKkfMPbOox6nq}~Raaygx>EcxhS&a? z=nwy1!~ec_O)PuiJCFz84HT{F^o82K*S|KVR}V74Ny#!__SJhRk4W^-3;=vCI)|I? ziMrXp!mgEuBz|T6v%RWP*jf5yy(BIVo$%47^#p1%x{9mDw*3f4mXy$OI>dw1u@c&zp&JQ|J~Z^zip_*~F7t$io)w-?UgfBQbevjM2` zg{Vb=(`PdSuqMs?FV&zyQmh4c`!4ez(1e$B%FPg2mD(!qVW;WWRkz$L&7e9O>b0 z;M;@U@MR$eh|6{6QF}JqSfvA^Jl%b~9QJ89Z$kV7j&_>#U!)A8uuHu#qylI2SdWc^DNQ3*mwtoowm>R?!0Y3OqI({m2PW@YmPxow0e;#s=`Ln7|A9 z^P7|kNY`rn0>l?bdXWLsp2 z_9c{b@gS6DGVULQDvMO+sc^cXkQFeH?~E{xPLi>iEwW_pLIfRlP}aL%+mF&)&H4LozVTM3q z-EaNi3h%4)_iqD>qVC8T;oD?Q&*+< zXsVXzS61^`6w*gx1Kfr8|5c&asVz4U_aD1Wyd$maN`&4}ESw)gV;0C_~ zeD`L@#vO6TpHsA{kKogW(Q6+5M&&>JZTV{P+tdcQ<1WlY^7aG{pY~2LwIk)CVbx;k z@~^;lM9PK!C&c&BcHuqUz$n^8t-##GzC{g(y=-DhWSfQ?z-YgDN8FX?EH0}J<43(A ztv3%{mn9ut|JXncGxu-}*YBiz9rwREjN-}q!TTqa!f7^)mEK2X!wJiqRm=NNDTVQ4 zSP$Pz3thDjaw*{3T_vZp8z-39DuE?ci!>IUA4{X zz!_2;H?Lg5=W#w&KF8rq+XsIu0hnb>!C8C{4q(J+!-*5P4sHz*)ldV!#lDJn=%a`v zTR-hrK1}C~1=8KjV-h2GUFZKAoPheDT)V(<(#Xisj%ul1j$$Vj_xnwQ;fv*wFZj+O zzNZ+qg$;l+SMaSGAyUD)!R94NkL_JO_B!Ib=izm*qqJ;x{20%x$AYJPecZ5b$@tiS zQG`l9ANk5TJ>Va?62p>(L`oYC2xl&S~Zx2gN`Ks>KE;!*6VhKdQb&zgrt&o2r zf<$dL%ZV#GoZ0PNJW@G=~I-6 zJXwdLEDE`=d_3766ZTjMM3NktQI?Qw!d{yk*gu}Hr7_WKYuPJx5NHA`58l!T`OdR-K*wfvzdEB&y&n8U(JrZ(a;fcKrd%-GGDGJd^ zOGF{3FgEn`l|mFL+;{NI%ria`k2A2RlcSB@{e&;Aekw6MnA3&k8aJ zVr^iBw5kz1A8u)oSpPt#wyY4H%Dn~+uEl3G1XFZV<&H%D4$c@-4fk$98(82;!F*xI zIku|TL5&;LMjgX91k#ymt+;gNDdz@(-;u#7p-}ka71A zR3It;Gu#w^|2t{9`*Xy9E+s1eg3pl3%`WM_zo=RsBg(y3(O;~fbIxOFRGFWFxZf7Y z{^s_wUk;_{k`It^UIb!uC6J%b2i3eEoo{$X8aV_RKaYl-WvlaJsdS0|kjJfmw(?H^ zTvs3BjdKuv=m)Pcy}i%)_c=%ha-S|K@4JS)xSwkj!M^$g#1?vyzuezvyuBjdV*ktg zt8JM9{&40$a4$Ff^t?KL&18`NGVn|r&U(~pVgIyW$d9-&&XBNde5u7^`lwDi$|Cds ziYJwk$sEoGc2EWxSHj?SoI3y&oNDC4v*DCzdQ?s$m&_T)pR;f#!)YHaaVtC<-}5(2 z@~OhLqfFIytTX4pyMrp1DuQpb!1SYuxMTE586IZQr&?QfiB;RhF?RGngI|MWk{2 zxDPd04(2_QErcVpDcDCIl6y&Nt}Vg*x~+hc?sN3{Q*^Y$>%86K&9sLkZA~i5-{AD6 z=8~V06V_U1B-pbAFg2QkYj_FWN9@g?L zdfjY>W!%U{`k?X)UD^w_kJLS&L*c$a1Dwl(y^K9Z73Lm@Fo`%POPbTjEA&K;tg$fs zymU`pUvg7)LpUdI_Mcp)ht*tS$=^{8R+XPoX+yl&8Uo&ie$z-Wf~a z*o*~a?65ru=ZHFy|6uNGxT74N|FDbf9!nUZp2`Ashmj|+wu+VS*Tx3yK^Wemyz*uT zsvdwCd7`fzLc3$r9gy2kZ@0-iW>mkwT!@Lm+6~9Wl!3I*J3Y-JZ=Rg9I%W!`L_Fp0 zYs>#Ei@$T{y;94Et(u0>bz@L?UDCvogpp?^Fyd&+Ve}XBW7GE|y0i!GFinW3|7Jn4 z6SH6^Lm#l9kLq~S`Tr^{QLJgQ6iYwdLDC6sA@1x9A6?epa9?bAlp|4zr-ya0&;Mwv0n!fr{lzD^FMKRRO3Mg;mnn=m)4@h%pW`9epFXqQ1WIoN8!B4 z34||IYMpFl+ioKExA^q3KrY?a(C1Im(e>VMZTOe;eqjqp;#(Gg_d-vwj&2Eitp#~3 zhBG*uL&cVjGf91U+EG-#`6yx^KMM9kg_T_ax!UyWvW}Y1*gMsQac!4Lc*CQLf@}+bZ$x<5vAm>f;<>3FX+`;Zyz`gDqn zePuslr9Ltn%#-MBcCK5}&)-UX#~U&){0h9Ly`>PVi`#>3uAK{B_Q)!Y6) zs&z(C)o1yl%{iH?6!tWeR%uSz;2ty9E1E{l@#-~`9np2sr@_M+_BJsNWna~toOWX7 znS`^GYp#cvFn9;uojMq1&%d_BZ6?%Dc8K*gCq)c1jzrZ(on9X|k%-R5@Fv&jegY>p z;|TIRJ2-c(%VvJ>J=mGLmAXP*`CHv6mhDEBo62vzgjnlaer!;)JXLr8(Jx!y@?}Rf z%ar;;{UdD(;LGF9l2rZqN55=)%ZK%EmMD`7lOAcqzvYA1E9a2rZk1Y2@K!m2a}27| z;kiXl#FB0;zq)Hk!7bpMvD$e5{W@5RYurQdompH4dq7x~j145%kQ~XXn$hyRv1Bup z3t9AsHVct5BgtK)Go-l}&x-NnN2D`QeAbcGq*EzAmzt%JjSTK{lGr!0`W{3d!aT)Z zlh^yOX3HFgqYH4J7Mx|Q3r+^qNafSrhwltqZcebWTU;=MHRhSwop$UQp}hYt-^Zc< zDBnkv1^m6{{(K)D@44Z84?W2Ffp?wUDdTY2h$iW0TH_E4E5#=}sN8V3zZv@>7cNY1L*~>U@n#ZdA z{G_`nLx1j#HzOY0<}7evsQi+F+#C4K;+W~DTJj+G#!K+_ALrg^ec|kXn0rH;HR)$^ zZ@dkwy{WE1$h{#xZ@iy-WA;jvI^y5v-bg*X_WvsPh5&s}u8?~}e9n0&_eRk@ADF*F zMj7zc{`=e;mog^d+#7xlIXhB2X8i{_JG31O{ugt0#5BF} z|B$mIrfK#6n6o1$=G9+vb{J;=Z|Ce#`H49@7U$ud9gFiG=N^4%0SMJ*gUiDC7iQk+rv3K9iV$P1gK+XfJEV~Lz;Hij zhxGK%=IqG8d)NJ=HJASnd+!1lRki+&uf1pX%mB*85e7Y2C}~FJF?L~j3TF^zzk4OO1xl??LRK zcki8l9f%!{`RC}79qn_W?e^e#i~XK7Z|7e6D`dhHv4f^`Aa=A-#E#VFGj|X>vVqvK zXeps69Tc&H|5qwQ(K{r>4y=|xKxjGhk!4&6g}%cp)y z(>T_daH8Is#);VBIdFi`8L9KS~Fpk+vi9iC$z|2Gjk2A-YjMC@?zsc(KCqrx$J z-*`m$HxWCW>HU%Ze#8!GPxwRs`|%C_>xdnWG6wcU|2Ysl);SP65`Kl);fT3f^8myS zsW-}w{+Zrbt^W5BJDmOD@f(O8uYxD7{JZAQAa*!%I^in(NyH9kd?gSQ{td(qN9s$m z-$d*HHwAiSmp_Zx;mGgoJ2>U=V8jlIJ9kz7_YpfBC21E6{|&?rM;_#@KS1n|X7rI? z?w`>QLhNw1e-7IJn}{8bI9p%)cMvB4UT5E&da+zW*)64rlsUr2o^19gZ|-$D#lJ9Ad}7SGxQe#12QkuZ;e;5Id%W zJERm>{X2*q&h{AoG-8KTmb~H~#E!2XgxKN8SsQv6vE$uKk{!B(b9Vt<(%3*h{7XZm4O~PlM062@#z!hyT`-QD*X2K~7g@mtwFCJk;_IEk(hty{tBf?iJ z7{4&f&BONhdGek|z}Ss!JnZfjcn;xRZ+2fZK%lJrvOSQZ0Edix>2h)<7Gzl0*ax)~_aI1hJJ zDL;}r7GLD?&5evv?pg_%Q#WYlb(?I2R$e!tjC6x$o)y#rSX9US3e3b}N+E9b8tttZ0IXEoV#FBka+n;gu;C#TYgj zNS45l-dLj$SA^+=<*sZlP^JtF#g?kJ9w^QRo?mYzFocSP)2(DRp*i<`0UUJk1XJ|} znp#L!zO7yXZM?1w+Xn1TW@O(HY7Usus;#U{?@BmVi$c*Z%&v-e>~SC6u|jbmdu`}} z>}9D&xz1*d!Fn(m#sF7(VOLf#DMs~jQ7=ieC-({zdn+5 zg~fnRaC(Qf#-ac&YY&Ai`4JbQRzwnt`P4QpC@px!Q??HcV#+nvsF2}2-R`v(PSMt| z=*#xt6^tz@>{tQHR5k9YOidbwcq?wPYK5ZBsK{GSV@q)teA#}|Sw^Bl@To@6A&r03 ze*DW5_BcvEc=rxFi{4>g+@IVJb?Fi*jX;3nq{xFYZLoCZxkV1QTs9i3*pUy>&3@tCS zl#Y?*%ncoEDlF_Or&npEMJh|JilRR+?CRfAc@9_0f&Q#UEoeQxTzZsRYJSlLY+cBl zDcbV|!WpKNUKy!h4*%+fOqOU_)Ybo|nt;TG%zIySv|>}muUkP!KS@vLUP82xR6JmI zs@RyrAoRMho_j(t%0oE4kW>1^3$%t(t&^l$<6R7;rIjYfy5Q~pb$Zvou{t>d=hOAwt?IzkaC_&c%s`QfG}3N>c}(tK^uxI??M^NaI}HtAs};dH5URgQcbJB*MC zCR)y>Qnlh!ndc!+pRFHrs2^}W^NTn|UU4t1Wnp}^GllVa?0^SPFbSrv>>IwGhg>?v zcKKE8G@Adj6HHeOSTQOgy9Ovm|u=r z)ogz*|M${7Mep93le1He`d%WZZ%8dIbyazjZOO)IJMd1dAc(y`69Q zrR~xxNNcsHe`i_HivR}-$HoLjK6&5c^LBMwlYL{4+*M-Aqq=nQNNOCgL%V8|MylNz zkC0-$^!D9k99*e(X}8Zmp|60ojz`(a+o%qT?0t{j?Z&QGBD%$VdMM8z>923jhvq+U zIajo?;1~qjlPwxqrQuw-{sixGQyT)!v%xrLV&0NxNE$gGX*6V6?7AYXgHpZoT_5*7 z&(5ar`n#6TH|#k%EaRgBwF~1>1U&`W({*TgQ1o?tBW2{euWR0q674U>mCCrtU;xoUb=hSEN{H2Uh3KXrSF zjlB|4XDsYBz|>o$v6YV4-_$x|>raFtuKCh)jmu)^)0ln(Ox_|^PRcE9!xSI{j?j$9 zN_R;cv1w#Bp1hATxq72gDBsA29m-#uTYR9Xm!aY1>!%#G#c7Qn8|2(6x^tl4rG!K! zBu4fmitA`)@(~*|{&btOY@B?!u;k_hQ(^Z>wp_#InvOg^ZibGtm1>30*nS5=?b7H= z|Hly2E}4G>f?9+FLG9uv7q9-;G1Q#(+u+okmTFs;gn@zFjYaR@PRPUm-

Nhe}=kKNsmho2G*B+Ma zj!`XRhkh}&)CH?!DbVUa;Q>@#ih^V@T|+(2dI)hiHLS=a#z-czZNg*21<&WWex0-2r>P;@{9S%6`(8tSN;~F?OrNlw|SP zw0OE(1qur+v@EUUp!et)hvsE{jwTMJxL(jIPi4yeCT2GGf!(!>tB)rJ=^a``xsolI z@J{CiXxe~}mCK+rrPWSy>P$%^xntSAI#Yi7q-KYnA)SMh=4~rJaxl6swKTVARQ=d9 z6KW?{PdgP~Is3$%iuYFLtr(CJn0E5`#>hfx2QAwL3lz|K7BotC<4UXupQPbTI5Qk) z=u=!CVSXBw`e8UuV4XO=%CfQtVM;hobc@qXUL{;z!i-v_()vY=ix66O^pS_j29q24q#!s72IU)4ryqEh-Tr-iKbY*0Sks`JXawCaJkSY6_= zk7UBtHgX_cy-2AYfBa|Kw$&GNdO7uBI?uGWn2&5Wl&e1aqaFPlX8GzDd-@2Mk@IX_ zB1WYKmagkV%Z9GvqU$zb65_Q7xOxqzbX0gY z)Zw(vvSC?75GL7aXSb`^ZF_FfTN7GQ7BMn zZkH*N--mYBws4aCv609=E+NUgIYzcSoRPh6gywMx11pu_Lk3p1v&0^-d(rKHtugHZ z+kgi1L9;y|x5gf@v&pjOFN>oS#@T)=MVRsV<@ zH8;0X#HJD=G;ODKwlw2(f@mrsy)qh>w6u$Lt1P`Ni&RUf7L+$ z__=v~&M4{!r1YyBRy(SC?5XI=2`463ad{}6AZM{X9VbmVQl(qL48hF0fk5KWIWwL=9}D^V|KwufXz=(x1V3$Xv@asis7t*n}J zV}wH=s_MW2X6d96{>P#k%Y`0zg8Yq1eyrFYZS1qca|6yeNN*FVS}P)@*^p*<+?#D+Z9ICZy&J_TQ8(4yNNCaM(ExO z+YhL1#ZAwgurpz5#bLX8MGBc%mQzNbi^AM8#W8)QNw{4~{Ina3Cu+|WrRXy=aHipD=;xz;yIp(XG|fq zhiH9iJuS4JKa|O#fxfhiphm^0QSs{r;q@}oTdp?B@uc%BoT!~x=ojW!lDl%!9@Mrx zHmnwUXMS&|CRNTL4eSqI)zqz5_D&#bi=BGZSvj1X8Ch3v@`XlsAyLby$-WfqY_;EfMJ=sfOq}vbV7j;TEV?C~txJgNz?Tj9zy)=4 zA;z85UYG2{VdOp6$bv2r@u?Rt+5hf*GT1s!?gjM!fC(#)-z282)dl!}z{rb-r3-I< z$P7zYX=j6XWBz>xOOB=;67LS#MA0W{JU;DFUBCyAF%1v7+@PgBSVp;K1Ur)M*80)C z)unI6z;xZsE)no=-BO)tqk9_27O5PuL$*leiBz^o<&9L%_(0hr`auQ6+O)j1{FJP+ zjgiJ?3-nemCO*7{o*4+}@6=iaUu%1LF4?+N(pn9?iBs+mlJ|{r$omW(@;=`6X`FU( z$oqh{+Q&dK;(sOYI|2-%r=EelZ{Y+}5li@M>Frr`#37^Gf472FQ>dOT`^*l{JR{SiGhYH_!h<3_ycKQ)(6p4+IP@g?v(bO z_;_#N5v-+ybIUrUefuHp`$&@Z?UAH?pG(rd_h6mKA?^EIlJ>o4lkJj|OnJi?*K541 zR+9F4cS!rt7E3D5HTf!JiCT4P7@?<_62`&uU>Z~Kp@Elo$odA{k@e-LdD$4JtgmHH zMJfYXAMe^B>kGPH)<;WFIAncB7f8AM<0M(%$o(?ujziWb-C>tV@`tJW*J{P!^f~<=BTX2tr&%OAGP7*#VBz*4j=ON+C zDt#i2%2*iMJ4sTF?@0J+<((yb<#LCFkG6?Q_@vqRXtR{=wXxG+OOn$M){I_Z&inUZ=@vOoAE38-iVyX z9wgtRxhx677e7h9r#&P;6b$L!w)>=eG}iVYe31-vO83?)`$4+*(k&7K>0YHI-J@|b zgCKA0zpUt7$^_G~FX=cAX~B6LNcWz(Bi&nfUi_069|Go|J~l_MV}#y_J$|&s^H&k7aw7ln2Q6%%8z-4wda~TZI!`+D&5aZ_4&8 za))g1#V3C)+550VvbV`8*-N`4*}K*u*>l+3f!yxk!{>fau6O#04yoQpRsAw_wv-+Y znOPBOj3QxA~oJz0>_W792eMc29xiQe{n!9&rlL!#Gjl}rBp5={zA76Z`lSHrU7qF!vheR(bv9@r8H4L*n zW%{#Jq9;Ej$@7X7N4n6aY%4PrVH@{!Y039WG zG>*JH!KCY+Rgh~a{I;Xqj~nLQLBN#Go#AX?PzQGW8}Bywjqod`dnju2)-PiFA^KI* za`T!8&Odrc@}elE!Y@Ll?Ug<;LNK&AWFlKf@9F)WUl@=GAceXscN)YXPTCG>|7Kii zJOu2l&A?Kil7_8+&0`KfwN>)3e)v-4H*MqS8MJ;zii_wtMeE|U7QA%K63L43(i2l{ z)Re#y@eMPG$W^n!M&W;nI9abY!dhg!47S@vpc6OQLzR){r0|hDZTQ@- zGc>$X-8$9qVF3eWKEAe;EsPi5sZ~)Me!^7+)7v0MpLf=OUp6#3S#NV>vuIN4jN$5N z6=U%Q)qRj4U=jF9hoz+a|I;)wEI#VPA zXPx6~QRhuI-uFDtAfqqUjYN!g_93v!rJg&F)5sbXQwVf)^la63)aymFm}+BjK5=Oc z3AL(ITkOINB_k}TA?nmdd#F`Z)M$D1ru6+%>djE4Xslty85$-St+7!AYFOYDnvtr- zhSoIMi>&Epi?@O~onEqEI9JsjT$ZS2Dk!?Yh)tK zEAz1&!wWYEJpqUo#$vYk@5f+?h)b7pp z;2d6cUMDWDmGQB)h%aWq8l*;se8lD(BoyteVe+kNMGYE}Cj| zg>(2BKjX}LyPbbi$yj2Q48K@`8OyuNWIVnRTcX|ZE%^`|YFVExE-z>4ENabBS1Xvj z9O0}6_*0tGg+K~w%P3Ot@3a%%dk?viofO_Muj*WaX1kaa&KP>^&%@fJ&L3+KllrpEeANt+6b^~3Od7rTcxiSrO`Kkg^^xh~g{$Q% zVDF;NK3GwF^?8zaf1P{C6r#}^XZlr)qkd}CPi$>u#i~ZONO3YlS()DN9s#Ae_AlevEIKczcJOYr$Ee^N%$J{5PF98l)4J5WZ@20 z>bW@why}e=n53qo8M8yG0dHzV4Vv!Mfcp5kTc_SjTXk6-lpWvU^rfRCxhdMRa2XNWOX zST9wKm{r0YGh3>#dfv3L>MaUJJp~8~K#}KtN*UlxpmjEIB5|gg;Z+ye!O6mHSg6WT z%P614nrXp!$eQi>IpT7aPPFf3#oE1Wk%!1VEK_d*q8@VNFJ5HyCShp-3ErYMVb#n4 z0?C2`aEJ5u;4PuD!kN6#0R5I5c6BW3;ZdL!7hENjUtc!!rWRIIUS+`zWV}o!JCFrj z24+Bx@a7Gox6pNBiNdU1jCH9>Ft5)F#X0o?*g*s>X(YU&OiQ0KS?TN2gG{`#QOiFA zPRJE#)6zvNdLX8Z;TxO5BTJZc(P8leU!+n3SK8#BL|qlmP%W&H39tU4*^Z7iS*FT4o z%e%C~cU7JaPT82dLa`hALA#+JB>pg+5tg|sHkD(y?msZdqKvZ7GYG@3vn|8aa-$u3 zG+J?O3K1u~EY*$gz7lmiagbs!8*TXN<9}%YzFM>2*(`Eno7i&$P)JH_Qm!jqN$v`@ z>!o+Q4)0sQgfYXo;gF?<(GZv6y=-FhTg<1&)1`7h2~?xp%LbvmnQbvxJdE~rW^wH` zJh6WvC1!EUFF^A^nOv^6mu)i2{NzzuCa?>XDAW22Ng9nZkzeLlxh6G-5)IG@8V!3b zhQ|F#qiKkXp>2=Q6vGJFw*rOf*B-ZI-NI9~J5g({F_yZXg#W&ZY*VUh%?v*ie19^1 zrq#*R4`F^{vkV2k7>8N%&WJbx`_Jm;i61D=THM(i0jW$<5D z%R=S4M6tD6w%#OibFgj;5uffcEXu3S`1#lwH6T8plCLfDD2x*?+KD6R7oOtym zvN=nbaf-B?gojSC!crTnw~9d;rf7}NT8qh!{R*tNc`b)j8eBI16cIM0V#eEu-fA&j zw2MO!bIUtxMb4)6Ud0cxkshnsrU;7V?&8=}GD|g{jc=Wj`ItnH$!w@RYL&3`8WXx! zZMuTBDaZ5v8lyIyvxlyQ{6;56pOO`Eg-J98I1b{ET$OJWmKGz0h3=fB6vg;vf}PV^ z?8Va6Rt^@9czLl-UC%M1`wW(s&0%@><1*gkA}p!6Gd;JwZ57^{0sNxi&FYtw%zTS( zPQpXt!ZM~vA+}dAt=U5Sbh6tl{AD`3=?Kc9BQ#YmqoIP=bXI7q#TQv$B0j5O^f`3Q zLf7tFE_BD;6zDu$d>AsLmLbB#6Rzs(?-J&?`nsKDh6^eib{W7eDrjNat-H-?fNxOS zMuRA>l;)<{qTsan^8Btayv9>)tzj(R4k7%E>r8sGjl&A|{>cnCvCSLyz~8M@{3PM5 zyrZZxi%n(ZUb|R>owzFr-i%?7I4rf=w9P!h1gl)`HLmG;L0;o()Hgg_b1lih81`=+ zmHG`3WmH%LjJ~VkLV+bK8 z(ZWU0`?CO%9xYss8L2Q3-qr*>vtW}Y8`?#O6>>{<4bwF_%AB5@r1vi1V!X`~rcg~Y zNzx0c9E1FairG5|-`L7Ha!xYDNp%7rQe1kM(YFC})Zwp^d`5lC9*Uq6ePoaekYDP; z8H%7Xp?q>_LJx=J+j8sHyMZh7RtB%&mwZkv;Fr*x#HnL&%=BAb2FVkNy9+-nji|?g z4^MxDu>cLlvZ5#DnNhAePlf)X zjpo>+d{@e_6pO?)dle*wC4pyH>wa86^c)?4D7WE?H`!X3`Z7{ED^XXaN&B+i+Rv0@BNxKaNNT*^7q zFjj?g)n*{}RRdKC>rK4&J$8D{jHt4(B4?#MiRCk5p*_SgS8~LRcidS z=dluyrlpY)uQoG9s@*xFX(67-NSm?+>8=sWDWqE~rnbt2Yd{B_aUfg$t(+;G6}-ig zdeh#rswLeLBWH@_3s&u3D=JKEzjZjRhmw<79?y0@xrCuRko8&E2Qj0p>aRJZ71;*t z5N_IUrr*rqlatvZEs$AZ%YE?-x`g?CMdR9)6klH1;< z7Y^sj)%1-g8>1WrE}&5|$1-TkqrhQy{4s|qzlXzwr`e3r=@}NFmWkCh*!K$xZ>+-e zL&Yp5Gt%tHH_7mN2Yn=wm*g{sx9nHfgfp}!0#hw`r-a7DyK3(2ke|$L zNy3yymI=>nv~Xv22~on=^vi!0`1in}>oVHHg(G;=Rn{C3>6>m;HJOyYEK$u3)b&W` zt9BqJ)qk28F8dfd03SmKU>ik=?>&P)gA+9B9K5q_21l&E&fLtf)Zj_xl?+WLSwJ|E z4KNaQEZ*ho-I<%T7Mq#~-;B3}8Q4YQJ(&yd-7HvYrwIyJ3?cmS;K|*YKC4+ zRt+my&dUU^t1{u?$*{&(%LrZbN!pKmBXWtuUONs?W^i_@PsN1)R4_3d+6YAUR}OZ| zs71EkacaEdCU{#mqZW8uOWuZ>y^oshHj-Ip3;I{*RhZP4Olx={!%};L5qjaNG50tT zFJeb>v4AXz5=FOl~4X>8}@{{fVe2=(<|5lHljOiu=wFwT-tqnZsY|w;a$ypDDykLV_W5S=@oC56znXn`PFenm1C_f@ z1=ohu1)dpPe|Z&sOQ||47>j)iAzciq_w-%rn=>>SIDwZn?#h;BQRdo14Zf}IMKSXh za9oBmq;}WZq~R8g3)6dsI?4sok_63>>dF&!mDQ&z57re`7au5HlCB=4kuJy*Y?R)*UxF)`YNmCt>3IhyJ( z(Or-w>rtYc42h5SvX8L2l&jKwMBol)2jsOC(`Hcf`WBrA;|3$ z`t+A4*n;7|Gy#6aNZY(msgRz z99h3Z;3$wuMdN)}-9Y&Gc$8I6_7^~IOgw#qfL8~bo0^7oHSL$*Dv_tHnzX0NeAs;2 zoHo3{tURASeCqzBFyrvZ{rrsCl*=%a%n64+JVa~eIreTlpE~{ay{GC(DDU+BmCxz&=|!iT^#oK zcFPp->k0160yFWBZO4g}@7aV5Dj&>4?4Mb2<+n1?v>38Rptd4UGj?x_nTN71kd^6P%d@H#x9uU- z;`MTJE|!N>ut;h78t2ll7@7ad^m4(^03G$#DIn12(>vQ;Imf@e3F+Gp0ujFNe8Qu+2_UCwnxiS2C z7d*{&kicfAMrEA2! z-57DuRpN6r`;^GO$pjDO(-E@&BkYOWi1@{PMtrsxb0FI?7HjB-zd&|nVMJvE8@!%3 zonxu=N=%m%4>qIn8>qn4c8a%FsBJeBlQ38HvoCwa$u!EE`~1^Zd?=7$9Rw(^#2 zU%IFak%=n?%cvbiKI6FT%KD=9!qp>8@CJ3QE5j>i!amR7Q)=Ze7{wo8lOt3Wk|U;K z+}%&h)Y!v{%Foy4YeuVGY%OCf|3qt)y|7;|W5m50^m>tEUpC*hC(|c}_5we6A5&!I zXZK{b#qxVmYqy_BP>k5cjn3b{p>OtfVfZ~eNW7JQ)r|>?<-6=4)f-S&ehm>_m!g$* zgdc=-&-{bFQ3ltO3G2muZ!?3}i$B!C-sA*^UtYl;sODFEEu-IHcx5p=)*6VJgSx(D zV03Z2a&)uRQCMxT@V+aDUl0R%Tr3mHiLSHQ&@5gh;$0z+RmZ59>Z}1)-eo*yR}3?D zUEypCQmI$mvh#~0m;vj=1qP;w<4qT2MOnQ0qKr!V_!ZY=&~laCT3fUhnomshdi6i$ z%-9Vm(F5sjINxJZ1U6JPIEVL$#|kb&SsqNk?7`V$@=GWyn^am5AH2XKzh&QN;TL5C z1$hhXhQ4j(6;I1}GsZmQTbX5o2eU9cI$M-qlL>EDGnH%A6Y=%nwSF4|H(OFL|DV|n ziEdnmn4T-8AFw%8@piWO4BjowPcosK`K|>-bbp<>Qp<-x*1MvD5%YZ*@tOUE-}4dS zpZhBlmCn!loQMbJFnq`nW>}W^a|NWTKaho4{GjvXp)88CEAk5n&+)RL9Qqc|2V>Pj zj$KOlFH;#lzl0Rk@y&Q*B+tdH!EQ1BC=t_wWb4<7<|{IBSukYD(@4`6v2_jJgD$Mf zUu&skncS>>Yby2KV)E9ApJkEUHQ8IlX*Fb;Az#^EFHVagyU&QtF(k*6(R+oDGjtiw zDUL16=ZI(KhmV%mz{qU?`&kD0ltcbkc*4+I;1aa z?NkTs?G?>-pq#ocG;~Ex78+~{Cb7*Yz~?&!wXu2A92`@myftP4p0A;}M-r*Ezju@^ zxX#n-4YS9cDa|R0Hq?z9Homqf-mq_c;Dnsg^%GoQzBPRIh`JHOM(!IKYo^Mhir8*wRfh zSiGUt?^j0Bf9M*%TGb<6m{>(J^}MM``{B;zDk|yVfO~wQfLG-cS$`EQ0D36`1}N;` z6?ifOvSs}gZIUENRjcKF6wFC;SG`5WaLmvi8N%p8kSO7shSpWl1#w%$#p)_()K%a1 z(s$j-XY3`izV3J@8bu(PkE$a4Lzwe;hY8ralVqw6+blkhl2xkR+0>c=r)=m^)?TWo zbD;{ez|y*iWR+4>bs@QljW%Q|5oR;Mo~k$q*vLoXVSQ=eQ6BzQ>Z@oqsI6s^tgfS9 zj5uw!QI(`m56>BTVyIEkHF=@pMRU%fOxO&|Z*MiECm*Ot!gsQ2gWfR7+yrU`B^er6 z<=Kur8ozjNMu)#m^ON}Aj04WGY16Rf7ry8(IL{H2NXncOXgzL5q^rvHdX~GNImm`T5;VT z*)-PRcvA4-Od++R5<6HtH)uS5P!qmS;QI`|vfxRAv6^oXgR3#VgL8_kL1#khxv(oS z(zs1f_8f$-rF5l*)EC8Ya$nze?yV~@?vZX73vcL+a_9NLs|3f!Ks$$XsvotD+6hR zp6>jG4K>8OIbFXgL-=PC@iK_Y>)N!PrC2vc<;aYi1w1Db71ofKEMUObaewyGUf)-Er0c zE5@CV0;k_hS46gWfHEfG=j73Q8 znwX%deO5lT29n-p^nEor^EAU1eNf%LEIt(@VngnOTFI{LN#RThn$2?}e~_A@S7 zH3?TYAvq?A>d2dR{;fwCe%3Wo6cZm7koyR;@nB_)J~BV@%)xUp{f1=^+gR+dkCO0` z&~1i%P1J#G(bkGDr+cwhZbuqY4SXc&F{Hm^LZ zwM55gnec>_;O9AxIob6`X-KSp@xG@NXp_=gokhCwqef$-r6Z>5{ni)0mm1 zbY`~EZ^OL%&zPB|*l(okljzJme(%h@5-!cmolUpt%;e29FAvC>MiZku{}Of=4|J%na=`Gm8vVN;N4xuzXo`k)d16wD69ZS!tLbvCj&f5Xa24RbgiKiOGu| zP&YVB z$&@Z)+(V4m7zeq2-}9M`A+#zjNmqm)m|N21xwLA@vex>~XD_b=G9vr$Y2uzo>H( zkDtuX+yniNa_O6BgS%=g+7X8QQetuAKoe5Q(XJtK0bY%@@aKUv^GhfumUSW;?m8;yQwSAzX>mw-N&Vm z-R07X4lbQT23Tc}DxF-qTuUX|r!(+Pc@%OO{j-xxyDC>99=LRM3C=N;wR=5)OPBls zmo5XB7K2ZaZ!&^URO*Yu*_bskbk8L9FJ_&XkNKWjqYbVbT#IjQ*BXf>UxT^WCuW)+ zZ+}`*S)&a(BR>ie-n&qZ7r#m`YQ{G579 z*z>vLd5q^kC!QUc_TgsR?E$&}Xu^5$lYb`SmT%FY?cj7J%!4_d_^c=L$9LxP zHPLKrsG-upEAiaN`VseFe1p$-9^bdlOXGViV;Y{;(masHm*3ln?;z`nEYE1ruh=Iw zaty4im|x%X-dwc`+;5p3@4&Hy8@(oKte%c_pO=Cr3!^=}`SWpvpX-D5i#0qKb%kyN zTr%}v!e2Zv0|wOfJTt$(L9IFq{fx-{dj$>jD8V1~XBO5!vzK3vTC&iADuA4ENHh_b zUD1Ws`qU+j7Fr>zFqdd81rI|zVWw7ujt;-#s&4EVao=J>&jouB%jasm*;eSp3*(`c zGeq}xz2)KKM5ywROS3DrM9c5RY*Hz7p>=pd?t!hX2;o`{Q9tWLM5S6M#_dJ_TqWt| zkTbAMV^brvUWaejre^Kn`m`_jnX%wa5optSrh!pin|tZ_4T}sM-_L^;x~bTAew(-E zTy2l~tfTdTX+9})FL|_dZhM>U_fv2B?EjO#srFF)pXi&wwE0nw9nSpgi{4ZtmY-S0 ziiRpyU{s2EF%EgPNVV@w&Fnml;9aK7fpwnH7|3#cl}x}+&fXS1b?ZI7%c|-VY}2A# zN|;9_$*yfI{8dj__?Zhdg(r?;$#SG#Z%E=wpicS}}!n#;6<@Rmx-X<{yg@t zbhSF-U5VyTrQ$8t)Sgbc{qi`HoU4MR=m^58#OhQc=9Ck$$%k26n8}@#cH|w>cualNCL8X>z4P#L@+nI2ozJ^$oH4N2~O;{$Jt|5as>|w)O>_J&n+q!T@VbVA0 zkOU~Q%<7sL?SP85mD?|-hj&-0@%FziU8rhdGYxcAbyrz5kCJ?ACJ=##+iq7SY>y6$D9&rze^Q>C`{ zBSF@LXz3dYzQHtXEN!2ESLWlin@#O#=NaB{$s0rEJkSA3q|Y=+bPavRQO%2-gJTV6 ziu)OB4^A_%<8zAFjH9O)yBdrIj$J)lj(5n&IGZI#&rs_}2^v@rd3VXYd1gzhhEQ92 z>T#`%qIv-205k>F8shZ8{1{uU$c(q7Dh@)w5MyPDHjw$yIKRRLR}4Nn;0OyDS?{<6 zZ%C&|kW}jnX1X7x7O3vl@*Vl4RYit_#d%}!UV|FmCp9w46kF@f#ZvIIDK0`>XrQ7j4K@8 z56~BbE7~+A`$vTPg~wtYb=QRyha9y)zie>P;3JT_SiQ-BQo5cXX-RHN!YpLoQ2B)> z_bau}^U1(h$}023q6XhXRL(*zt7HWex`Syk2V#y3^{w45FM{1qZHU!E^}dRmeT0~^ z@@WzC^_2!obUD*a5tU)dHsH&|<>YQEy3Z4#+5SyN(2?NsBE(U*E+j%%MK?9}%+U5w z<#to2>ZN^rzBMnE+lF^MoR_~&Sj1-xH*JnxQBnk2iTA$~GP-8fQ8C)}ChUpyvYkrE z=Q6SLQ85iYtJ*D_`;o2<>4q$`P~A*24fM(K;a1q8VI+wJo)9C@TMomV+Yg(ed-LCX4*SR(9t}3 z#1dV~bW^F(Zb(rut#V+qHW=W~~8J{381oknuj)@;vJ0fXX2k*{(!k#&p>m}b1lgm<*vqI#vPvkj9ta>1Xr9VJFNY*RVxp;`^VKG?OR+j1>UH7u*6^> z;hD&Q?(mHa@NOYzMh5u6|6+g!|Kt4*f2s33y>ZgSsxQMQ9{w_N;;}DBPCU6Rk=7Zw zAByEemnC9g2}}hM{Z!$tx$|dDea(N?oBn;LyVCIRIn({;#{0)DjuRHVHES;L<{iKO za~8bz+GB(qc;0T`6=Juq2T`{(ZFJtFVG;0u;=CRUcjBL*&UyV$_5Xl&+hjWEKMgDI zbgvuk1v>9P0(YR({|4NJe}X#7c#ykxoTJ>c$VU!8z3!m<>bUM)zN%B%G<++{qhY6<G~u*-;l7 z?tkBJ;C;WyQF=0KPCOZ<8%5?!okIpb6~sUNOz@y*pPM>Om>w5T$Ng@YE_7&EILR@czowaC7Wj536t*03l9G!k zS*_jPZoh56VZUTQYd>gDv=cjNhw{}8a*3QJ2T3BqZ=nC}f0NNRYpeoIAVx%`{l zTG#2zzN-A;%BgOBBfoz#`03Fv?XGyW?~s<9)~{cUWpYjX560AOUzWRVPta4%r{q@} zg1!!#=T{l<&!C?pS5J5@WSi=xU)rO*GH*TC<87hu(5DXmII_y;~RO*GWx1Ps}J;koUP{_yV3z#%WYT^W|N{U_i08T-~g7yi*hpB`U3 zWL|;zVcL?J2L_CI`MZ(D2i9ga9Ue0Bg%_6Y3x2$7QQPf`sVQEIj{g1oAyI`pKNzJ| zPd)VY<8eLC#cFIPFAs68dH;sf4>azA2oH9Kl;M|$;dhJv*yftYl%Pc zzw0HqO~U(5Cqofu%;=XQW8n?}aiAWc1kl~zr6CUgBU*<$-r;J^4tMz>hdcX*@b5#(3z@HcAN$=hF6F z4_i|;QgQrJVp!|2@5GYDJi+>3FGOgB{SGnR-AJh9Q%3V9k)6C)a?AdG4x7-|ZK{oo?kwLu%-i%nZY{K&eZ@&A@ zXzvBLSKI9yH#w+F=3PGxEAMo#8}0=_=}pws^b+=YLFI?8yEyLOGE+_T6>4nMu_ zp!?&mca}@TL)YC~-*e9E^BeAlFYVNZ`}69!?p(gAQ`t0pE6Sr`r<~;;bh@oMcuu0c zd{D5n?y6^M5P6pS)E?$PoSQQnwNg1;*biUW~^Lyj&c3!Xl;%>OySN9^`j4r3n&qHep>rPuTxB^pMr^_^%o{7a8H zXf51@PU=$u9^1)J!|C-~oruOcU+17Exci*6@QmHwaZUX+oL=wkL^PZ*EQ^D}vW}I( z-S<=c!B6?${Hgvg|2&-wn0b3FVU{w?U%Ik{hWUbC`_gWoEOSJlVNZba3-J7KhB@y1 z=l?%F@Sh&|PY?X32maFo|LKAMsXg#7mL%f2o%ki_e`*~WXT{w4V}F0T+v`pLs^^H? z|J2IPMQgq(i=`%43|=(la|A! zwAx8Ia4Btd(oVRPK5^1sxRee$sT?k)6HcmyOX;kW&cmg2$w@chQi8x$A{AUpo=)E~P{#Er&~KwUct-QrhaI zop33A;-tNBDIIiDIb2F7oKy>!(pe{+hfC>_lWxGJL~vG#lFCV*a4GpZ$saDI{!SVQ zm(sIN(!!+_;iNHeDaAVJ6}XgUI_V9#lomTF5iX_WPFf9@QjU|h!lks+NuR)_wAV=o z;ZiDh(h0bfYMpczE~WEMx&)Wf4JQ$3?NCxV$rCOmUnfBsC6Q8pCk=#4=~*Xf;Zlll z(ipgu01710D{v{zbkZAeDJ^zVB3w$#owOP*r5q=1g-dCtlRkk&8$k|$hBzE1LoONoA`_`To%>-YO4YW>fT)%w#m)_$$^ zUwd5ZFF*FjWWVP}2t#x)4ULTaov!+$`yEN||K>A>c5xylS|lMXF$^6#*uTGFRMcbs zg9Zc*7)bhg5h9n;%b6w!WV%=tjwBzf)%tfxZCI7^TNcUX$_sF0a&Fd~w+O4^Zepv& zddgp*4x^ZZlq{oqjXEs-CBF3UX(SE)ysZ0Ba`{ghVcLmEm{qw#kdu-h$6< zJB_}b=0@E9MGM)r3tl;qx6#7?PLs%?6#|ni^Wp6xm%ob!a6T{ZsqJcX=lFkWBNYP?7<V5oCa^~qF{}315y8Z+8R&fiCoi3Wc(=?${8c)q5$etU@_E(`S&Htj&^wOPynvJx{ z2KEKqd0KM}MRSqToo6+)JGtTPDBO8o6GB@zilysOt7)cPHd=}nrm@lt#z=P}G#6+F zFS6s1W`t%hEoYn*ZH%Tny@-;UGfoppvtG>NlpKlmrE{2D%F=lo!T9>of)d!#xEjIu zdeh94*f>Ny!}=D}a#LA41JAO)AJQumI}i8pp6nr~iw+EN0q%NJzlWSoNU6(LG#9i;-(+t++=SI@~H0LmQ8lA+U!Z z?z?kCm?WA3PAp^WB|p*3qn)UeE)<%#>77spCPhgXqM}YFLYy`1d4e0yu0bzrKB8$} zW+^)-n$a}PL}|3-ny2WUNm4A8=0!RplUd45AJGW3qEn<1j?nC@B zl%^L^Ne@)aQ|I+xE^#r^TJ)pK9Jr%&K>VIY0&Wp-j8RvqR?l{%@Fl%oLOVU=G~^+= zAf=gyfT8ev$myzlh^~>2S^BCJJOTeII#ZJ1k&0%?!^i2!wzHJUJd7E%Msw1|L}A_-SLMz-@@Og_aWq^6e!c`9fJ{6 zdA1_hLoNlB(sIs8-T|nws)1(N`#Ds?>0OMbJH0DuVu@?^zKUcn>!;JWf5o562AWJo zvl;K=Y!^d%zm6RLH+$a#=T%khe}2C?GYrh|8eo_g<2dq`86NWR!L`vy$q1DcVPGDR zq8Wmc4@3nb#7Al(<~1UQ%)Dg&O}%EOW<+XTuNghAnR(63%xmT)GbOI+|NC8Que100 z{RWs(to#4hd_HIPT5GSh_S$=|z4qgr-#I-ue-M=T5t!an|#*W_=*#slS6qJn) zJOYK3jQ9hKz8LJK!=%}3ky$#PV0<&w_P&U7?V!of5x)xky;rjx;y)1lq*V542=rci zIH|uNcAg#|3?f_cQTX>4T;h9g zM}vM3_<#dgmp3z{A5ezc_ReMrkN7%UWLV+pfNe3H+4O2}OoK~|jzXf5ry6!Iuu){V z1#4$!WkwW^9^41f2Xz|V8vw_}=mG#Q0yvl~W9os8Y2d#@@vq_i__qaSH_QYu3Dz{s z1@Kt{rvfNMlQk>_z(rrf3II60h#D>h@Ct!z0aU>5hK&Fw0~muJ|3{5?kc`p_OOf?; zAm@?iI{A#0uYV+JfP(O8nyr^g?BdG2H*e!_X1c(;2{8)64(LY zMgmU*_#J^40lY=vH2`Db^003tDzXK@B%0p<?v4g+uz8OCk_bjxR(>dpqTjyzum z;TrPX3E+zaz6Ic60{;f!*986pKnBj#@GAhL3H%MtI0)On32@MJ_I^@)GQRaUN zP84u_0xt2?B>{Cp!f*~4-c+%3z~I1zQRXj7TzFOjUT{H_c_gL@6X~jxzRM~!#8PBi z+X925iR`#Z6PbIMH8%LTfc}91J_>GRJX1Ytiz z(Yl~U3P%$;g2BH$%3LqG(d0wULNDE{tY@L`6r9N6rv`p4Fwntbpo7Ig2aACY76TPl z0~L-YX5f93oFFie)IDkGb75%zZRIqO; z#)+CkCHfTj;^;cW=A4s~?2S!ze3s=VXmuwgc0{5FChzj3M5fZcos^KlPD(fhclo4* z%y}mz)V7~bN~8wvq=c}Yln}O)62f~uDWS0lb@?YHl#EK+F>nhHCmfgPNeN*)DIshp zC4}vygs`2I5Vn&N!gf+Zcz>Rhup;|DDPgHyKPge2T{|fe&G72uQNmtNN`z5QN(gr6 zq=fwMXCh zZ2t>SN@y0tGQxgWPD&iRoRkpW$4LptQg~9Lfv0;XB`oH>J1J2M^G-^{&~BcT(9ple zNeRo@e7M_%_=HW>R@$jUCcy~`qD1(y{COj7Gsd#rzN+{9wlM>bmPTko_2^GDY zlM($vw3F-Umq=dTO)k%pc z*xx55YzKEzB9;B$ds0I4_H|N%yT?(cQcg;2F`U_SJT_`0&ola0u=^Z&zF{Yp;-mz7 zx@wX6Ca}?Dr|?dcml;xc@VUT$gp7mF1n_49?En^Fe>{dP4Xc1PT*-f*#lOZa`1fDP zZ2T&Kk)+&%f0q#8F~=VXJcfT)VmsCNGXVDzcn-j01bz?TWdc0i=!G3kLl)TB-uPFH zqnZIIzp)I+2a(lS3*dAB(YS*F&4$sX{Cp@g)4aljL>)Jd0>t z4B$Be%K=2#T0~ zKZcp)k6|X$^QQ#IFq6V#n8|eIDZw$!l;9XfuS|hqZh4_JBFFeu>p!dhBEBuR|6G}CeyvA1jjH_f@7E|!7>z7kiDx%l^XRJa03G4B|}Q%UYwh>{DY z4+DsYPmX^HX~_$)u;3K($8|haAv#CUfu(WjY0J-!3g!x0l8H-Z<7}y*Sqhc-o{fk(A{G|CL8{E%|QxTD%W;m}!%p61XMK+86>=;4op zx%Xh8pP*VnHv%1aG*ykDs`ul@15l_E^cqE>O3+7umQAA#BdF?ql|Vn3ppO9^IE$)A zQdMh}pim`fhoVp==+J7&@(x^PBvpN$=tWc|=+|*`dJxX6N3pTW??9V2qqzsSl7Gxg zphe}pDf0;s%SwgF5>Fh$3@pB*%MW^LQ~x_07`M_Sth|jGM6B; zOyYx}&k>anA?P;`1S(NN(8q{MplCcDs(wjSVuhe@6P0iwXjwf_i5P+|02)=i1}o6R z(I{8}6A>jv@u!$sel}X==yb*nA~kYzQytb%QCm9mD;i!sFlnmZ2I7idq?|ZPB<9Mu4dDAZ=Y6riX zfK?+PkSg)e971)N8&%Y7QSU;oFQF#+G@@BPm5QABb+&jr#ap+A=b<;9<@Bkxu z@OpMoBaYaVUJv^FK`-MjKhsFV#y0|eI6}=K(EWj*{2nauJY9Hjqst zAklk>Y6K)&G8U*tK%%uoeFPj&)Xyfg&jcEkUyIVS7;AwAmypj}a4k`9 z!49I{f?oseJO;l`Mqhf*aX@|PH9)Z>LFpH#OCL)9_T(xZla7Y`6EE1@?9vomX31+0w`89c>s^%{>)zt$iTP?~srHq~6=zKD<>1R&?#b3p3D2}U$AHse&gD|`QA)r-13!{K8LtYfV9$0fCB0SD49>|2vxu<-|4nq0DK};eO0uKW)g};*q60TRif|b;%Y_P`||!)Nk(5YP-O|VU^OacpxW|cLSc6NRJbpVWS_Zf$xABEjNzTqiVe#}Y0F3pwExr21 z$M--nvYU_R5{&CySI5l`jY~dExp@vPF8K)2`GWTAS1Nn`xTS?!`({dIuOGJxnu$sy zSjykV^yX1`zj(%Y6d_ywc;fc1}Sd=M)5sF2=LDRUOVRNXfJeI;w3EoaAFbhNJfe==w(lbw@9P7pdUUbf^&` z*f!{B3XY)Q3J4B_|BR%`ndb7#;Xge=AABe)a&RA1HM{=osC+Bv2PX6}Mz5FvTICY* zHi-2V@6RQiltZWr+0nGJ(ynGtNSC9hmp~$p`1Ggqx<5ewYS{PUmz(O!!1(-te|TNW z>mE+L&YCE*sTHl*ZLgz{^E!f=Hs^4Hv^s}74LSeEJDkXE72yf)+YY#bG&ws;Cfi?GF-foQMLef0>}IK;cvBaW(lK zcRDzo#~p+X9X)RME$VU4;V|wWagHO>#krHwKpN+)iQa3Ey9vGLLR^xfFIH$#I%-?br z=yY0;J|X`QG#BzC~H#sn1MPSZC)LQm7%zYH+y_X}}3lC6z0n|PB?f*i>*wGwbs>o9=)2)H|MAj;sz zQ*_FG16eNC5q(2ZF1v`1or2|&POx);7Oda7(j71`cN=ouu{qJ`P(c~>h|UG-;-1Q` zUgb^{m^=S4Fwf$V`$(c+Q53R*z6o^DEY8m(RrcCd^x#pfSLO&T_Rc7bqFFvV_C<>o ztlzQ<8)RhMh>S9Mlzj|!zYhXsJ>gjyK|ezD{Jw^sPV|~2_adN}=%MA0)S}1i)UpW~ z727}$H2;#aUh|}>K)vR#5cQgS{S!1tuy&9n{~81{=JTzSwvMjAYxF*FpUv(8~s}aU1FTBi;veY=Z7S8t7#r#oW)l zALy47^vPp^p1__E**?>Oemlv15JSD}7fEjE44`}xLYdz>0Vp3xP;}ynKyOLVX|vHP z(_tQefZ~o$Xuv|y-4O!Oou>fRBLt#v&I7847erUI0M)~rb~MG+MD+lJ=zT=>_=Ms4={Eq4 z%5OyJFQrTWF8TBbg*BYK2&gapM;`;~OP~626zA(7)cttm1f`!t)R(>)XjFbLN?(X8 zsQbT@&zJrT7-Kc|d)wF96zk>7OH`uk|B9qw->G`uLlmp!Da-=S%%mN9kA60zH~yH~*P@dVEFn{g;rB56AHroB`igkrD9S`zi8W z3m%^C1bp$@6yMoE(cj?7V)hOA9!T@8T}QrM;2WLhTXl6x-y#P6@^RqVN+WI7hl?Qx$U=r)wlR3fOcN?XUXX6yd7v%{w&Hq9A#H| zzpe5<83`5yl(q-R7K413YuLJeoxAYr8 zz4!eJXb`zOFZngf_>vF2mnH8)$yHbo2eqDwjG*L#ZvyotKXV^YU-Gs0ccJ7jfhj0? z2hgaz0)290y5zr*&)4~`2T~jY zOCPiisIPa!cYykOe;w#PTm1W!@h$!*piy}{NrJDKZ@qJXMipn5V6CMOS#XBfOkz}VBdBF>!01dPSJZcc zTE-u+D*7X$9kP;S?jMN$Hp%V(7*IZ=s|(AMfMOYZ%^gj3V*m^XUzOg=83weP^x**9 zeH`jrMg@8whv+(@dLM`AMxuHjhv@A@^*#>m{{v8z_9V2{19(45E89-f#xl3x4?wHo zbGucZ7}cDXLn!|~s{d7rwy+7tvYbT_E&Es2O3-ygzn7r55M7+0j{rp|fR-a5TBT1z zu(~yM{ebJuAZo4Bry&H?n?VA$iN)N<)nq6T8e5h_7!u}2m2chIR7W@FFRAsO*;p1l z=yCLFzf#cTewox^ENI%!g7*3$P-$mDzfDxySD2*x~zf0Tst1Qi1 zIg+_G59C-{^Mf2hW%0i@)zyNvgiYbwy2`h6m2cyqeOHS98cO*>qZ&Td8xqn@Q}HbN zWAO96*@ej-lD8h-f@c)bJ-9EELym%|mbk!JZ9Rf^i=)%gDelmv5*1kuyBER!CiMCw zRN`G6x`YQUSlnv4IA}Q?usdiW*&Vc82QWBjc@wBRXdxKaB?m1IwSyLi+Cht;-9Bg; zj%INOEtjD*chJHWU(|0Gz4joItz9yk?m^SZK?})p&_WSh5EVRbq0C1r0e*7(1JSl`z26c z$7w`;9nT`_>sbFR%D~%Gpz%M_MjnNnz{n*;y^(`{MX|FXR$7P*-+w0|BM@6d)Qjz= zSPdW29wM>2kFP{63>?CwfbUH{Fdx`8O{KAI;3N3}i&RK|{=_;d!T7DfIp=xdKP)Tqux){SM+Pz@JQC~vMZ&*S! zcneg10`p(xQW=g<-iP6RvVgZe0I*ty_w}T<2>9H$0ZtJxXZ#-ljf0nC(&ITvS(C7E zz@uFk@5TH@jb0~oOvwJA&E4%=i)z?C0(5x3x-dFm&M17^-AnGe! z_aabV>Hh$V(r&oFscsg4KlDJZH}o|!dqYqBFQDGgi-1N|b!Zfdj=`Qf5d8{yy=dV} zDN%U{wCY}nJ_yl`6!mp%0dMuTbR93CyszW8iTXPJk*Kd@&F_HvI{pYKI$|p{{wQta zPBMBUXS@v5*YA9wQPs!?o9a#gz~k~~AN^~nwtlc4c41itV@LE#S^7iT z;w}9(QE%xRM7^aY|IIp2!$4w7pHEHR3CAEaXs)82Kz%2T0~%Frg6K2=ccw)@Mqc02 z52r<+r)c#K4EM4^8H~e#m;C{*vJ12lgn*#s=Yt;9=TV}*KBvA4)Ys>?K%?q@XqCXN ztN#evIMVbvJWdIdKnvXZ5~AL%?hv#h3;&)Ml9fcJ=@tFz&f~HO~m)i#nD@69k-KN1s_=rhFiYVRJR-HYol^^ zGV&I_KAXiwKc1iB z9o!MEkpB^~%Ina}KZSLAA9Qpz!0h_=sG=6kmHI>;3#+P>p?EM=R?6(6pbS9;W%wy5 zL+@ZV75wNGc)?u&YP`0$Q1XyNQF4vfTKfi2ulXvXUi)u|`Vv053#c#UO`!O5+wNKx zEY5)S`K7qxXkA(2oR2x@+_Jr??qvvl;NX8a=boK&8=Z3~z0le#v*|oEY5$LbOrNd! zGaOW(V;~(q$?Y}4>Bs@f?KRP5K;f5k#EXH#$p+w;ha;$Z6S4-)fjhJ#qx@f4iBxW`)G$Q7rF6$f%IGEa=CGN^BPN zHlh-r1ugs^XsK+0hAOY2%1c*y$to`uRaePGGKz*&zDa4BL_}qkOd<-(B%+{9BBR&> zm5+6|xXS;egiHpbWN=l!l0&EtbEC@MC?=#-*5(q%<`Amu3K2}41dEEJT9LO|3y z8oUEdUnA3m3mzvV193<=5bs4vaa1rc8Hi)ihpVCCs_!<{or+GqX$-vLUH=+4`~~hx zXt!VBE&(jZUWHRh&iMuIGa%_~@GgIWn?XffpuYw>HPFxh96+6i;_0Q}aBsrr)57Ni zm6GGR1mik455>(6wWoz0YEKIbYV%OsG8Y9T^HAI>DCZ&fCVhKac#D}A&!nYdUfeza zVASt)j;UcJTaRQmZAGVX9va5Vv|*6wTr>h*1z6@Hg>^0(Nq(J+1pF-|bS@IKFIElu z^!P}cKZ~e5Juc{GpabOOY?P>xQ!@cY%`8R|L0^!luBUUT*>Q_MAx6YyBcoZ_f)rQLX7v z@flj;tJS$tfoR{iAzAaxcbn=)0vIA=_mE4_dOTaSr|xUnL-sR^|Bg9!Hw;R~?(J^u z?nLd5L#r-r6v21;fS|49xa_+Cm#i$qv+BaBB)dU-9l!z&6#Vu4GeF(godqx%K?QRJ z^*^l;)c>?X(D0`fbfCOr=)AF;tReT?*cC(klm5=GoW~L48G9SMUo3-T4ZRH2w;suC z;!Qb@-Jz_Pj@#j!sHUR(^>AEJ4p9C8pX_=#F5ns90*Wyw=q*6?aD2oIVB|7V54lB5 z54Z{9%_KbUhS*4=R{?cDNu)nr3RB!q5{VAaW+Hi>kcJQ54PP1xU^R!X9(b!$wnvp` zz|Fq}x;yZuYCG^IYzN+i-R^P>;oqTvsB#;GM_`NuJIqq-XsVtB-R&^RJRCH)!z6k= zQQct@{XJ3LVG{j#3{-cRtVu6^I{~i{Da4x3}8ciWZ5m#Og^y^vG2V(IZy@^~jZ=?g|?TUPU7+x1c8f z#td2bOrSq)K}OBh)Fz9c38F$4KMKm?N5S*xrW4p;)t^qlnkA6cyTy_f)vU@P3<-0i z!5h)aeNgbNVAG$TiQL^Zu!dh`2-(xJwbA!9>Q&1xtS2ybB+HcpXjrnT#Xc*Jh7ZPn zeR+s|?dFMbKGfNERDN3I0)ssu?H+{A7D@^F)U(^5xaW)u+|$wg%1x%n5b()YZn9%e zCb%2a>@orQrt9o_GRV7I3r@=n1zZ$oZ}|>V`N~ap>kS0?m7DBWNR5h{@b5>sdXky% zZq0t_RY3BUo9vgVP2b&`z4a!5?khLhuTn(5a+CcUceCy*H*xuVAo`V?c9z_K}d^x;onMJVk`=hceln<-T+Cy zauXk>2DhUr;={EhzPmL(g0Q~3HJ(aX-`yJj6JdRKYkVYOeRpg8KEnF$*0_nVzPmL( zig2BMstxxS8n1qma6Y=jTd|xbp6UrypR>=S8k}P`1AP3%jxVJe-ViL%1wOU_khS( zZsPL^>Q`>!3q&(CG=Ze=ZjHbG1|kT*aueSpoczj7{0(8`yIbRX3F^CB<8K}dSif=; z-$z)#aueTw6Uxx9+{6!%U*Fvtf0q^4uiV5Bp9Q`>!AJQ`Y%1yk3`t{wd@lSpRe*MZ#{8K)oqF=d*e@0pT%1!(f`Ssnc z@h{E;tY5i_pBaRppkKL(pZg2w`jwmbd5#DD%1!(m%HrLvpGHFVf%1=)8aNB34P-W2 zvkqB*7!r&W00d?xrt|HIUe;ZH~2yl&Cz$a#wSRQ ze&r@UF*^e?`jwmbBw^Ecx5g(+b@VGY@$&3ja9I7yO?+{de(Sz+6JL@&7MT0WP5jAh z3-r0K+{Ej$1*rM6`jwmbvh2r@CttalgOwydXObCFxgg;)Pj`2mQ)T{82&lD>w0}g6LOn z;?uGlVU2#}CSH`i6^MT2CO%!t(Ra7TXNZh`w1S1<|kE#ES*d zuiV6Ei8j2um9D}fr9trSR^lvGaJ;*f_@&dSD>w0Z0_#_9;`6hwAOl~y zVU!^#I`HmRHY%On;nh3iQ)Dd4S8n1ZS$2qgQCZ6|VqW@DAqOQ2WMwGs}Sa_;(pDwOYP%({u7SVB>+kz~A%!(~&1%x#{^J+1yud zsH<1SGaz*RD>uFBwo-w9P~H?*dQlUs z7}N+I1^VTh0{wE0+pHGomum|2%QeM^fsZd}llH-TQx^c1FU*v_nIT=iFjJb%5+259 zsC(a;Ei9<{SyLTKMUm0-75JZCoF0zl?Nk^MO~g9T{a|nZEmE^RhC#La6k`iPE>a7Y z3CKli!Fn>-2L^aZw66~gOb5@;ami;nUov=0mrwhs&twhs&twhs&twhs&twhs&twhs&twhs&tP8O+uwNEj! z)UJPEfQ@qiM)Ow?V)ykaM$rsjy1`yQFd&TjfdPW{fq~-z+ou=_clIep^1qiK7@+>{ zd|-h5@ALx$l-BJ~}8ijk__2L=f4j}Ht`kNd!YfLx>&|5`x(z<_}I zfdMX6WRcqQ^Q8I@46t6EePDoeS)~4d^C?CKlkiiFY=_`ej9po}9);EDXK=~r$I^8b zVEZ^C>Gp9%!oz;Uliu&hw^eOQ7Cl6*t#uB7zBIA_KH&DW4n#F?a#2Y5~67lW_RMeS`omEMO!jpWH@MDT}$$xkx z8|LrRBfW>v<3^_)^k8$)G3ub=nea<;c@zi!>^pIA zFT;%`M!klUO6}Y#ZS(4XG&94$w)%V1%xrkvN!IqRVS5juW4@C}{QsPHyNPkn-c5IA zvpaY0)VJNLh^}7lS+j^TgU#71LT87Ea{$1@wdp&Z@xp;0uEPACHhcXNe;Z$0?7yti9F9h>yZiq+A263sgiIiPZ*~_g%`=hPhgvz$Z zYKC29JrQyu0#+F0g_|meHPtsQjIT|3y*rhIrnFnDBPN|5)&+ zUc)*F^CvHsPnbVyD2gma4~rjS4lMfjWHKT zZ;YvaBkCZ5y^@LAS<$r$GPxXAQM5W*35A4NFK{vG2a}-CS`;9($REy#BX(jYYGKLj zKY-SC0IkJ^&7onEEJU($Fe=P4zT$yOzb`nJMJSJ5FwwZT;fsV0B zsVwgq0T+~^5LPb}wK1VLfY+P?RPzT=%@shUZEp$hY$iuai?o?O6|`lK^O2%~OZi4g@4>q^cknuy}no8s9Yt)FLl=o{BdDJ`c$&l)ME-Et2H zun-q|62JNvl_-TWTSTUH8u(ddRDt3rh#84;PQ+bvYWh^*cyzjnLP{!p640B4)Xanf zq7eSvG%N`@WFd zJ4l_5Ymm#i3RONoswWe(O#xlxap{P&m~hM$B6c1$7WUN${1?s;H`iFx|%T3A2DA{QU3gRaHsBeL!R3K?C;!%ED1F z6G|3hDnQSh5}=vD5jZDI5P@Ve==R)V9rPlAUAThy#OIJSCMD|ofHYfz$^s_L?ZNRK zx+kMFe_er*#^h`P69=3DbfJ)1n5h0_IG2M|Be|{hNJb0TLN$~NhV#)tX9}r}hO`Qp z3}?!!nayTq(3_ko28shF<=zU?PSMfEgt>Y3x(gYP2+uqwsv&8a7eIPba$A^aZc=ON zzgu!!??bX(L8^IDK_*lYRPkw`FKRAr+9hC{SKek_M~$kcg~`jfir|YEVGI!NCsm!t zgjV%({dGw&)+#{fx-BT3v*mOlwVsOP3wLUGsq{bqfqsuxa4mRAX}IdPVB_Oneg|6e8Pzx$S1r= z%FzWf;iMeogI)fHgRb^rHQK%*HagS0aTP_cuBbuE@@8Sg8V)r18wkkkB+Thma4f7T z_dtL@1URu9`Gg;n`~@3g;I#Y5z;0wEf71Y2yAtN2PH@=Ga>9Pg?I-H36201Qgp+=P zJlkMKkWV=2r=VRxj<^B9Du4-_2m{o5161n>P+8{abd+QJvWeiY)>4RD)<^)^K2Hln zE343q3sh?rh&90ic0}OuTt}ZIGR;h`60nVHj=L4K#=+ut78Fu3Vw^P*sMOEa09cQN zjR6KGQ>Cb8&O^rum_&wR=w>fqZN@|wzU?fkkLaIA{rs&X7?`XPu$>755@yFIkgy-X zz(h-Jx1Io%oj}LMRKw&60o$HIqSNCNCfXRu>gP--y;k(MQf7(Bv@%(ai+hx-Bk%r< zE37eBvanqKtOdB=oahP&_nr%(U8Dcv$q?nJ%0y?G^i%-a?6Y?Q)V7{Y88$NJ;bO>W zRYhFQUu@zP065m+No-2GL$Kf+33R@Yl5QX~yE@=n2vk>$%}kivBl=`|uDcGz8*l|~ zL^0X{e_Mux96|1tKsRYF6D=}{e71+<@#TF5+FK_+B|2bvX} z$eT2mi5isD-pkHo0h*i0t^rB=KAE+-MSchuN?^j=yc*DnZxo)S;+!wH32D9=MorfV zsfEn9DaeG(fm7T8^a0JaB7^!-RyDUWp+SKxCv*noz#TY0s~5L&5F9SKiJ_d9IgAiQ z%up^F$H`EcHvtJ(pF#OmKpTbB%3KaRl+WZ)rJ5SX5hxLYmElQKhFwm5ZVw9Yj}4?gDD2s$c=P z5$F~nExiNDy#g*_!h(8X?ZXA>XRs3?PSdgNFtezdbw)H~@|=K)m(j}dbX!G0%Y@W! zI(CAqSV&37>;g$kN*aKwU&9r2(2GDRj2>me6@O9m$yFC)<3O0x91oPZk+8B}03Vej z<{61>u5XRR{yh#?Fyxsv5SPvMgva4=a$7?&-~MI+u(b!_dj!|ROTrHa`Gj8!@(KSr z$R}J1zm{^aMj|{;a9u+YPV5NQP!N;(my-m`BwsjT(5{nkk;arfnP?H&rpE%#LPE`; zB2WIt;eQjzMbR4hG_$c7?%1L+09Zf|oJ4Tf-eIkfiB4rf+rvB}Y=xd!V^15_>+K#@ z9c+ZxLmnb*iGar%A}NEWPZQHmHM>w8gygRj|DV8>iRLhQNx(%+iXjIo6Y6AxFs)NE zlc54G8jfV7QkgLPx)$56R2I8TESR$#$>j?6LmSpgJ91i-Keo@|xH8dPCR1_sh%Stp znuZ?OLF71Gz0n+{Z@=9)suD6u_u$Gzr!jd(z_~9VVPk>HBo;g5Yp1LNsMbm-iS6^C zQoW(4c|%Y0hMopp@^=;fUxSN{!c;A2y$NbGl($mVY^iAL93<@uQtLVeMGyWhcH%|& zkSo6jPIHb1i{VtHj;#46cLo5Ok@Pc>Ex52Qqz+DQN!}SiI9Dfx)j+Na3D*L-J|u9K z*&Gs}TK-rt<6I_M%H(nZPiLa7u#}~@;>tv)Ghx}_Wpc4nna}{X9#b|On3+5;;8G^{ zNT6B3`nO7xEoJMiQ4pocAB{O57y6OO#kdlWSqnr>YNJUy)6Z=Ns3x^}ljfR92$|lZ zxwPmZT%bONZk`s|Xb0gsX&u5}eA3v1;g=W+d8Sb9{#_T>+|g*iu&ZF5z9uk@$HDwWA<0h2bk9q5C&3ZqM-@xwX@(n}D| zPlDMTXaHF%|L#HVc3ef6FD^mP66Q@0Olh7wnRytsw@7ZQ<+8G>DvH?px=x+Lc79Uz zJcC5nS#!83+bFiop$|W#pow1#MyH+PkBE3HkKUhFkec+~*u1MCN);@gsSAS-0^EiR zKEp%@$pR~2HRN9wRV^1IS6gMa<+6C)kBfHAO*VXtwY=wqeK8XTxtzNx6@tA*eHXHOL~oOR`#+ zu&83ZiKuDVh3H~p6{0$+Tq#hJir@oOO}I{3xaS$EAZmP|JRAgI*Da9Y+-5UAPcecO${PN04gk6*SY!9mxclJyKb?)tsOp zOWdfS3BC@sTBD^*W=rm3Cg`nt)=t^Nbi^)B>dZPobimEP>O}oGUN6tmKI8s(} zqyS!w3tM?6OK|m>RWFayr72LOEgOEQs!XSy9;9|nDQ;4_~I3hV% zXVjMo<#Swhvm*y;9{`DyP~fUB0(Gl0Gx1T($8POoB&M8|?683FHo^6V3gO2D*Mon; zZwjvYgx?PG36~){+hGG?9tN6z!d&NAKG>5#wL=dJQg-05U>mr8h|3Nu2q$(R-`k<` zDLatw?a=&`9XW>)T!L_}--eWY;j)8vSw2(pU~5gb%ccDnU5A7<%sGsx$B?l-09kIs zWw?2);Y|>qDUFogV2(jyG@u7&Wx8sIwGtLtH01R#k1bLMvl3<^LvaNs6GTUbJVeH% zd5BI3d5EySfgYmkP$AgitDmg0+q?D0xn`g%fVn>3I_IO zAC!SMWx~#6r&yp;-!EZ|FiAIuX7AsyB3wH*}6SG+7E?52ZKYVx5_8 z!-d1-+o0+msdEceZIljZ@v4#~*V#^{C|WBA8nj_8xDBT?UDj~0%im)BXW7Xa1(D6T zT!V9)kmM}`!W}|FxDv<>Az>qs%^~3?AX`HMRLdU=-i8a|jJAFN7eFRw2zWY^3zW)a zol=>wRJIe-O+s#E!lK-P#?4A)!WIOT2{$7sgH3UxG-NW51TmF%tq{8wGFgo)@tCWC zY{P{W9c`X3`WBvwge?Oq6E$?9844=xR5KPbc}sa|#tmXdoA1vyXqP`S_CYS|$zEqH zfj@AnxX+P|^%elzaN#6^Qs)cje5$`*K_=8;v4`;8n#F`V%`FJefSW)UqZ2&_pp|rM zQc^ohDia;;OwJT=9t%}V+wTJCj&7LH=z?fPrh~wPxUgkmQYs}hGbzW#>T(m!5dsfn zLOXDv&yA*5cy6s@gH#^I8q00I+)-ooS<0b7~O!qp3_4?DLYJ{wmt z)|?+6%DpSGIk>os;kgCj<`f69>u|w+HX^x0LAK%33OpM^9l*$UYK;HS9IBTO_7wgHWbaDmE%0T8N8<`|&IX)cq+0=6(Y8y8&RypH7n zRtmkD35Q8=|7z=(G(^aP;k0d}Mh-SQapOnrt}wBn#n}G>Zu}6w5O2Dl9@xUy15#8b+cS`Z!o= zS+ISgvQ0utZj*C_J%}rq&F%r}f|%(diMQy3hU2Nq3?XstAb(k)+-?WAt4Puse@3c9 zxR0>RrM}S$GNGWaS*Wr~n3681oZH(Q*KXM2;$29}v6x)7DZrr}}- zEJp_r)_Tfg5GMdF=EH`=E<#)Lu;UC|L5-V$t`rhuy!=fEx=2XLK8&TT6;e_!l5!f9 zzILNC?)#ok#HQ>i}3E|PMZ?WRP> zT(2V;KQ|+HE3W=*rVkCRzefHy@CFFU_u)DqorV23_;51_{~Hb@qg8+-jl1Wdf$suJ zd-|h;C~%%vPx2$U4oGKVw+}w-jq=n#4d$0|^~QGhu%USJbX;RtI`y%wve983R#C!c zozFiu$UnA|{P97)f5L_GG=WdOFx9dS33v}l>3SYK#b&BJB>N&L2-!?n51(l!`t5hJ zh=p{&%gfruZhfGB_7 zau|TRB$lg4LJZ7U1HrYp(CXJCxj{irwxzhjc4Jj;!$sO%Nbhm*eMomZ_${U)H(u^3 zv)oX}-({uICdobJ3N#2OtFTe73i7W3Odf0}$W|naq|>j$o7Fet0`)#5+Z3c;{>{gA zD~7eLy~(`;m*G?KuA^pLhKmsX&B4X8d0$n|0f=bfbD2DcE6F4BBCe8X{cWp?n()}d zswz3p=fs+D*<76BVnvRWb<|ul4GRvlDp-5Gfbw6&#l~T(wzR&6*!DUugbgp>>gAJQ zLa(HZ-9Kf)tEFM|=?%hX6wzGP;rL-4rp^RRr{T~if4Ad5jY~GAMAW)w7Q#hMl1GG7 zd8!Ram=$snnV-u=!orY?$l_cs5|)HqL^#o>N+f|txQSgv*pw+Q5_aRl@VCYQXzdV$ zVlv)dtbIdQq#wc^A9ub6kS_NGF7_VN=LMe7L1o9`0*f>z{_&(kPioqjuq6wk^*dIw zkSif32m#tu5G~uWk^q%R&Pf31(BUB31wC)#!koawseD>g-UGWK`1DEwZ{i{ok|HQA zCcWsOw^wxt1_~blBdvaXO-C{CX}BOj3+})riU_a;XaUooS_T1D9xnDQ)Mk>Fh%v-g zb+Ap|!UcUyUO_zU8I@$WvAmiNqPuZ%MZmNQbqum=fwD1KsP&MlMTOx902@Eo0s?=HXFq10B!$AMfF71yndYB~tFjYfZjfAJ;LZ35XDZbOJ zAY-=DJclo^-3s)XXc+mcg3=}_qm2p6ky?cORSTOhqs_|5>2uSH-d*D) z(dT5|fh*{9-Z@($3yWqZWq9VJUhk4!5mjA?(*)cu#?4x6-2mdQ7^wUeqVR!te6)V& z$|4ZKgZ~b}afM3xOfOmwv6;9g?MakEytP(a-2bXCRD&QPlMxu3PRLD`L$xg zid7V&2`g4rIV7dPGe90Z6sPFAcWDCUw}=UA6BE|1s&Yum1kV5yz(W%#x&$wg$M9vc z3D>j;jF+z}qK;jtQ?05ah;s^;#~j=gg_;zrS4>T{#neWI3(+r-KvL^LXbbYFEkMZ% zZAfS)HPwl>E3`l)V%rs~svHPyF3)VsVTCquQyVo+z=h>1lM`?ah^|<*BC1+}WhK&)!8zrTA5snPR&FgXHpLHG1Qn0#Z`>wSNJ%5eFw3TxQaj_PIxk|-ng3~l~Fb` zig%Osnb>wFvr$St76y2{1|#-TrfY!KVsHUuOKZQ8uNBwugm?XF?l|_uPu?}SFs8u= zC0altS+19sw{@tQ#Nnu6d034{#f;=dZ=#DSZ* zGC&*vJuC<=5NEi643m@s5=?{RfeJ#@kqR!*LKO%ci3UUzQmMd!V1RsnaCyfjFt|K~ zYZ60(GXc>cF~L!3f@gpUF1S$i2@$8nT4_Z5PsAP7nm`#Su8m01wGx}=F=0dzLtfKB zt6_-4}iTMkw#Z7 z7i#$7ibF`OhI$bBMnW5AHzpjF^*D7!P{BA|u3}e1Oh^#R8NEZ5mjkjB=G<}WG-LR6 z!kjZGyQZ1LZ>zT%4&RApH`d5^H?Hv)lgREW~ zHMvoqX4#WA79pcN&F(d(Mmd-`Y+;Cva#FOaTn913Gy)CTp|P`39r1$>Q(?l9E<^iP0Jr19kZ1Bb`X2O`R}x?Z!_zz#dV+_gj>M3EL`Hub6W!!o&BYML z`Ep$p(Y=Jk>ZxbtZF0baEH2bV4x1ctO2q+sQEqZlTa#Q-DsevDi8w_k<4U$B5JzmG zkOUsLv$4`a)6!l1q3Bdx*zz&auyrw`9T+a;`%W&9O`VWnv=bvA7Y#$f0ba(ZPMGt< zmT)6Lb;6t%wz{I(Rt@!P2ck?TnqBN+@OTQB@pf827b(ccXn{>D+#5tR1pbS1N4bDO zCdow81VQEn5k(B)*nlVkh=@80MSUhjU4Wt3K#NaalvNPwstSZqQON3zp{65oP4B8U+Y99s?ln@|qqs04nYdMw?$z8XNfEA+0O=x&5CRz( zpa}pYaj;6#T(^9Y_~~`HWs#^tXQf%awqTW%W?}sFlwg&#FO8}A31-Gmu72DqiIkjG zlG6yjkR3L57C%E4ji2v8qs7mW2y^lsL)AFhP3jbS6I)@D!6;3Dze?Y5|j% za1Fs2#J&vi?oy2#+@xKJ9j^8nS#&Sg37e2uTjlk8IpfuZyo4jF&Ee->&c#ry{-Fen z_@4+704_r|VerLKlo3t0f(UUC$N!W#a1&Pshy&<+2L^e@zLWwIOao!?Kt*ndoD{hY z7P1i$6Ag|^1)c%&IZ+cQOsJnz&m>V`^gWwku{7C%!32cPM1$LQQGo-s3PE^vYcrUT zgv>;o0H{{JGN1-Q*i2#{SY6mm#1U0UrMLsNbQd~1i+$t|V;^vg;j|(S97kbyIBkr5 zGjWBnZ?D=oYPq6wJ8T3-ucNlrq7l8p zLS3f>XJ}5N%P<>r*x3cTzNNP3aN)5^CS0VBup>2H-!6~1w$(#6E=ezq%oC+x#k4j#-|1)31u+Df$XN>s4*brfEFko=BN=#(N^vR0 zv94BN1e1=Wwu4mqdOxljIAoBhjEw-5p-Y2K4-rr1u}OY8cCwoUt_cDNIElcHJdP;+xiny0_Ba&0V(<5&pFwb<%f%Aqz;Sgwr~Z7Gfw-%@Vm zSZ#xWL`fS<<03bRoTM9BR@aE2~l;o_!QP=%?+F0#=nKqWk zaV!UI>qfTKGiRXFS{v)#m$X<=;f616;c~cgu<oeS5C$r`vBfXBB&cz^OlgNZ8HQ0{qTxq%lG3G2d z`1=a{o{@=TUcD+{UcD-0X8+=Mz)T$TtD)vsR~mB>)G?akH)Tv5^O{iennd$)U|u0+ zv@p@>U4K7Hn6WaM-f>!zIExbDEF?|?7hR$>iHoF~layGzBhf-xn$?`6#6lEV=@?HX z<-;*ZB!R&N4yFef>@eizOy4|#aFM4r@fVc|qDJB{GJR9VqF;x3Oume{j7-v$>3sT5 z1U+^gQ)E2Y`>xzlW3r}cwprFfmUIbL(dF;YLri;f4R&4&g5}X_Tj0yq7;(bfz&!{TN5`FL#OM|h&GV^Ctl|+jHNUU|J zjU7tb@EIp9L$zHk(}tIy7gZ9YEG*NZHuhMiMb7R^+VJGB)fUN^o6p2%RP?qC5q7uD zsH9ou zB_i06Xpsif3OE^5NVSL}GZ0r0BwFZ5v#x`kyg4W{kg<}$co6RHc;`>&CN~X%nO(0p z^>U^mD#8F&85@U~Qb1?tgN~&0U8Krb_vg!4|I0MQaxfHB#vC9&$2@>dzEPT7e#E#1 zAa{{$9l{T37L%Xi;`R_(_RI?2(%(Tc*B0C!A}jq+ONVXcDx{*FJjRl&MG<6Sx^TE2 z&UF*p~biDDZ4=@Cn8(>-p_0k`V+4%;!%{>CmZu3QE2cml9HLvNKX7i>%GomAV ziJBegG}|rdF`S&(gK9b-ANb7nDp*K|z_WVpe7+^|YbW z{W5K6$wU&Ai4hjo)1fx*Xsr#s?n~OxiH7i{WOO9akVG2> zKE#n~?w&+L63wsEtn^=cSP~7%YA)w@S7;k_TXIaGyDRTQiNp9EoRctrPzmn=Nq6U! zVZE6rVV&hSYOW0Hi@XeLYKFSorKuMf=}MAx+qQ?D7&+Jwc>fn&EF$9Yg~t^QF6bA8P<&~i;JyvfQCwp z(0xnVfb_vqC7ml+nM{MuW|{c`S|y#Un51h!N0mC74|Tsx^D!T0wM^$~R;G*0=76-; ze6ahH=A(4HtgN1A8;MW-b~z@Hnf=tIwJ{5tpoKBf(;0bwNA~tr(1YQR6A-M8@oY>u z8-R#)5sATU03z2vq^4#A(1jSx1_3K)1G;>2IzxF9xFFE-;kP7`a2z(NB@tZCl#)RI zlKU#W%jNP?k;mOWgG_$pp$r^{`f8J%B_dCbjCqB`7s{aHRmOTfKgYU|4c$i?dI1x@ zGlcJU<9!vvjhe-T{m@6V&gT)#WmpcAHXB!erP~8m%pzHDq;&EGR{jAEZufQaxK;iE z4R1)IZk;?^mG}UH6FA@ldA#Zu91i9h{um{X+4&2(&1I4UniR7;pn)5Z*F33fn$5$K z1Dcd(*Y{4dIiA)Jj+f$Poz)p>h52KBwT2G=BCN940ypoN7AO2kW1A3mr@ou z5#CWUe3vD7$COpAN9o&?vY;tze#lV@wG7L0sQEpmEMRu8EE^VM>=p&e!pI2Aa;S|L zmSsbxdr~%>irj#}EoBY>J4j)OAk3z=gA~%N>1CZ57?!jyR(-w^x#YA4lyzb#VQrKr zVa*`R!BE0#nwMdfVE`D8D|lrSAGF^4c?mhXd|qPe@M<%&2B4LHG|FBfCDc;}PE8wX6OYc%2^)GQT9{`cw3+Y; z((tpH(335T@G{L}!Ux3Qys2l$I_#-29+E)a1#*Mjp8m=^B+2Kn(=R(j00*mrsoow$ z0th09D^~*S;v8N?dgBG?c+C~;D8uPxpf_g1j@w)$(Ckh|$m~GJYo60J&E`>oW<)!7 z7BxH2X*Nd-c*zNmGn3W%*cRr00WTu9>2;vfYtLRu(5JhQPgl%=05hDNw6;BCC1>&Z zQueeGL~d%$+jiz=vv`q-!UW1jBXdcE3y;Oyf9p z1ZBE0Wo5cd8)@P6(S1o9jK^R|ohc*iV@x#a$r#Fydhmf{1SC<9M00f?%1AYrPNE)( z=DTTD^U);gk=2|riFzc`>*yCr)FaUx#UFs66*+&IANb=8myw#-=z^}1laQAuVV&g9 zIh-n+O7b$Si5bKeN)w-Mq$7cHzQK>dE^WINO$iX(qM5i!u%)3K% zyHo1Ad|I*+ns35|-z+h?6;}g)wTV|=$?Z>s#!h|*3M!sIl=otFSd~pvfBcM;IV<$N zS$r>+X+FYbbw|Gx624q(9ZcLP7Pm8DO~*#-Z$`L5q5J%esM>5N>xbkCYBZ4J4?bIE zhxK8FZ9X|V5vCA0Acg;l21mt_pFKSV1`O&@m(4e6U6^CQivKBHz)hDjKo@|dBW#c! zo3e{j5R@@VX(PeZIUeXElqj_E?Tzzi`N@OH(Cw(y<{6+&A57L3x3I9^jAKOMX_Yt5 z#cCLoJhCh>tDS$pKp%Kj|s_i)J;4a6KyaU``Kbe0GCGDD`>sXlNi24jX;uij1HNTgx#u(Si6dY5n3=deS) zK3=WuZqeJTrxwoNP|gY4gMsyqXx4ik4lZDc|Joej)#o%OTGI8fQ}6Q4`W*J0wzu_w zSHEAa=X}Ih0(kXqVSq&1UVrvM&{^;D&H5a6Sg+4JYui&b=Mkv?=}L*6IsETVy-k|$ zk$RhSuE7j&9WHyRbg}1I$~_9?o+lKZxr9m*wnM4t+Cb`dycgfca@$ zc=(A4Psz?n?6%)6)^~DjrWM#%%}m1{6==;^EH~<(Ns8t{4vN6R1peF8PdGH`-o(Ki9E;+=y#JJB_U!>K z%dM@HL*Ig`K0&4za9!OQqxq=y=zHxGV!jM9n)C{;x6)?)wGH}odaVBS+ktJsff8p{ zV{}X4a3lY(-4rN&_20TREMzq8u{Ba7{%;mS^4scvhh2VrF~*I z861LuyjPuKbk|#Sue#nd`+Uo?RXKZ{gqFpd1ByBuv#DkXy!3BlJBD>)s700kT^9P* zwdD|hKfD_kj!T%hJ^fbQ)7$TVJ30N;safuY~dwS@0RBH1KP_~CX{r)k|P6@H6cM9DO3gq zy)KGlb4y)0y#U;rO&O>w=mlE_R17q_~E08D@PBdyYQ@yY=_N`e3*2)MGnMTivcYeC-383x^jj!>rF?hxL2d ztv{LU*7u+KV7LBWsJAfxJYxGxxca*j=F9vJhve6B9gxntQaC=Te5u`fA56+qabefX zB=ranUKA4E$H2A@F_lCMr?@!*A_F6-78B(@2IxYx1Isk4MX2Nv9?IJx9PVR48i9jE zJ331q;UUq6kaA+^kZ8wLDV=mzzTzasNdg@Ww`<*dO;8@R;G?7NG)HdAx|gi6CONlj zQ#sZvY)LM~`EEu&s6)607k+-nglkK+0+SqG%OX!694h$>m`LkO%{51StycT+j8^(eiT*4T@8a8p&SbT7pT9DEOw=JIlDlx>moIvtQG ziMSeiJNn6T>h91cgcjZ@rX^fiVt$uN~$i8PCqW`>!RmtiGx z6gEkT$w!DdZrz>0J^VJ792D%*&t1vP-oSUCm^jVXtTNN^tJ`am9~;dA^Gea&#>7Qm zOl*h&ct1!okP$dQ#Gob7My$UzOsb8{DFm@T=p6NOma5gpG`W2>tqgK>%oNd!4B^Jl#78q9HFj!FaVl$ZK6)d^^^`9Z+zmeb^Q zpwnya5%5wkdf4=;%TTX*O~AWHd(D{w-aYEIcjzF9s&kPO0U}?(oR8Mn>vIr9JCh=j zq0lJ_B~w9^F6+v(#i^5YsJS)Ew6GvSv|Ezq`P_3~Dek?PNh*e*#S=eHVhD-mus$%5 zYL1!25E9J;)2!xc$#^HLxl|HENHpI`VhD-mBuQi-(Yzt0likjaNpV_F`KM2`g_98C zA2M+n*3NkuVKXk1W?W>XnLu6q-owvt$U$2$Gca+?Z-oz(yp=pqLS}}jF1-k09T@Kx z<`yQrwO*tzw$1*;{)AM0gX?ot_44-ZdpMPhb?-Z{6I)46+D6q*+Y# zmp7ffaX0^$H#lPLnnTnJ>{nZV?A*HPRZOUH*j(nK`gKe;Rrl za$i>MOrDZ)D(_oOerkoth2I0gIdIG+Ly~7#G9*D3A_?p~8InAXK(8_{H6%f2M}p3t zOAkrPpm$Wpx(35IN5-081|DV5$|{o@lBpbPGgg!XjK6qeMF>BN3qz6#S5}rq_(jcP z!gk@iLLjAYz+EXDT5B%;PA zKg&@R{@gmT5Dle+pO2biQDcKv|}F2qn!)x?iR_k*rv#RvVNDacmtc6DTvy z!&s&{S@$K)3F%o)=t)eWMtT4wH}CG@xlnSjbGr1@Cz_6sBNJuoqbs7-dJFjqJ)g_xwYu`X(z9^k(HbUeaE-;c(pXLx zUh%Bw!xZ9@t|1h}?TAhWVP`ifx?P?v6jSBl4nrs9<=%H-3`mRd0iwKEfw+*|m$9%h z)zywJsgW1|Mb=UBB1x#lf{JNz!yF~!u7YSuhXVS&#u?-%wphq%a<-(j=%5jeGHmi9 zR;bBtb{y|Dacnt-;jIoG{%Pw%Rt&>XvBj*9bWgF3ag?(c0D~3GP6U%;0oDI_oOo3!l3q(;QqM>Wr~_ zK}{l?L{%zegqs;%9^v<{%+PS!pa#5Cy%sfR>|5_XW2v{6ahUOOe_LxYw+q(pGZK4i zAA+TfuU*l)uR!g!TEw2W*Ouj2=yn|Ug;+q}dm*U+-PJJf3$b|Lw%3}Z3eh3nwOPOy zWYfWteH9c2XM}whu3cPlhIGD~4JHX+uFV$9_D8v0nnQfqHks_b?EM+2ec7CA+Hvi@ z?3^j(UCltgY>T*yFz{}~g}19Rp$qUl2(BaBmE@F%UB0JN9_FRClJ|}F zmi24*q^!@`k@}^>1x8xAX3$p$-FzSyZmR+45r$p-Vq zKX6nci*u*)4OTspd}VCCc#StEm2YBpw~>;N=;Jh33UvpzLrhC0(KAURdWe*v6S++d z>FiU|lBA6{UOgGwR~85z>D{MHyTHA!Nec>8b>5$&glot#-k-au#O;#TcNm#Z%qPOEuAe^C2oS;z?H``#PDa8za<$OO# z%7OfgXjon{^&*;=L@>25l0(FAk=)d!mvS_lvMTGAB{9K5Qd%oPZH7u8;V%GeC@J_k zz*{SFb8nw*D^$!HSJBTYP({N&C0WqNR5)+QwCOJtW?6R&`6-$zNYrpQotd){IWWJ-{v^rJ7-lbEd)Vk6Td5UWoTMGs=NtQL`4N9{;2ntVfc&vQOscY*dN7|g=K>h$zT+75BZ~2Ca$yV zm1?pOQPN%05kX@O-mg22+XGAfsgjQ9m1S_|Biap}NTn75m`6cu9<40OW>HwwZ`3Rr zB*S=*c@jyDZfbpIQDgeCxvaY?51L(LZ&`OOi3#SA(zci$iWk#UT_u_oXw~7C0!qwG z;&%BPEnb0jRl22*S7@`S=Z&5jk)ZCHm10?6Auk&|#?6eQ^7YF;FB>dHSAEBPWk5eO zCbE8hbE+_ASVXX_x=m_kOd?Y=?2o*~f7wlc<@E3iTS*-8!dAjZJa;Zb zcsoF6R3JZbBajyN4D)UT@-reV98%2GjA%?hI+t}ZrCEX8 zTTgr{Pc{OJ?xPH=T{M$RS<|P;bZ;dREP~z(}%(&lRSV0 zkuc8^Q2~4V_#e$E#gIKVO9xGM9il`@4Gj5`?NrIASA~A!; zc&;(M0;Qgt(kxzPy4fQg5%f?aTl*6Am2so%`W%&9hq4BfR9GD zAAGUB_p;A*)9=WFI+q~4-{o;ZU|j}zB`}HKPStM7Zp%Yoev2*XkCsN+8Tc=lT*(>u z>kz&N;BTKOI0!Jw+;02l{srEMxbmpRI3`(O(KaHE;O`Z?jUCs|WL`dA@ujF0eJ%v< z-AKYo7Dn>hGEv4$QpE2?f`9M=;N4{%9Qp9st0$}ilI(qtAkYHDf1jZ~Vit*C3&YZq zu1p;5)2}Z=>#9Z6?I*FhBa_*$4Y+T(#l8#pXla!FSdMM-+c(@2Qgcp^E|2`L3z!Sc z9xWT1ea<0dgDt%?B-?YrD_Y(m;VwBl7636+KTq!9z_|)KgQ}PjcT2gv& zxpykP%(Lu0+ArydN$J5OAHtKK0eBWw@CGmx)?BP8)OT4a5FC18XWjG?dn@Io-&Inl zRs0uwuL;G6)mo_z@3gQROPgOMCsQu07Qb<5kv-pl(w$v<%NoS*RQhTCdL0jXpZBw9ujAu$4AoVmScb(zl z&sU(LYxH|DC;mrPmqC&D%T3b7S#)TiLqw-lvenVrkb*y^5Mrg#0;fRyJ&LR&_7Odx zOIVdSqW!d)2&z)-5Qp-YK}x&I=(KpDD13DM8L9X)#)zMnil0{!f40ki-iSgKUm4Xq z+qQ%ABen`mg@vgs7LLk-Dk_I=mnt6=+#RPrH%^i8=8nOuFX3HIdMTvvDwlP$g6n{) zXvfYGAvYLbfhjt_B#TSnD+`7DooGI2_XOk%jcUR-{ISJvKtL-NC>&s)bgkaR7U5FJVE%J$4AG{OT{ORlBBOs#V2-A`~;V0{fNRT z01c&J8sO|AWV-Pcm^$-Q*(El*Wn2{94%BeSsJ<@!8-#C=asn~cQBC%X(XJuMoQ4$}jKzz`?BtED<0i&lB z9|?Mw2nVHKqdmsELYo!H?1|hdGgC@8k5-y^DZR+jE07K)>Bm%xbfcAm8I+PG-vZRd z6v~`TCJLrFbiMSPZd?U3fU4-Cog+e|C(=P(%q1mP8dpIRpsW?PI`&!x?EsEmF(N}> zVtfUA9e;S|h>+`yui&6V<0-COY56}Vr9+(_hJ40Y3VsSyb6`|`L-=#RFEK7)?5G-` zk_sjORnZrBjtH4zdgW z5)Qij>PMa-oIk<%p`vGl+*=`)S`QGY7*Lh6l3YMlNF7TA(4_=-Fd~B9NidnV2Gyu@ z2c?Kha0`Wi-cGP%yhHCJc+}8P>N1d50A2yVMbPLJXu5*HbZI&O`ij$~NxGcG7xT!T zOi=06YLX2m8akO^nW0klMne_c0#rp`*y$`X!&Rb5mAJ`OqDhsQ=qk~qN|*~YsS>xk zN;D;vXi6#(|IYelX#Oxz&4NUZA^d58CDP4tP1dOF5{}yYk`j(g_$0t|s6d{ZD5AEPVG~Yb=4M%23zH;LhQA#kFS*KA z=j6=_G-D=m@|Xi9ocp0B<3ovz`rz&o&OWG{OE_}3drLU?K^-XJs1MiCnUb8bq`OY0 zx{W|(G;ibqq$DXk#6J#FPs7nUuOiSN4$}ak@E&8US!H7+6v((?n2}jw>m|0V0(u!i zJJrN(HP*-m5|$lQdn9B4RU32{f$A#>g*Hg6Q=m#CaVLRl3#!1BuOCrWw*#;h_->#; z0~y>wtwG*n;s;Ktu*tsr)d6gHqc`N~W--`fKy#}R9h8Iu;6CK*D zAP0;OgI9Jdk9Zoct~UXVQ@1;G!vO*tQ#Yug)yib1;6)(AMEy}WQNBr?L}f>W&7?X< z^O|BuG%Y)#sbnEw(ZX^7xrC9~a*=OrcmA7?)+^8)J1N<7Uggf7e>`qLnSZ(yvCm?5 zxDA4jYhDw32JpUU&z<(*lZsTt0)Qor0+mwFd?-nGxZA%i*t5o!7q)5l_~PAT(+RN> zvy>W`Rh$xHHvlMcw<(c|RK)4Pah$VKv@6-aNJu}11Vy$mq z3pfW6`&JqA$03&+Nbt8K#_wf-iHL5Y9TSVwragWkphO9wi5`J<|*yDi75q2nx6aRw%g)2}QA1@ONRwymFtV2t|X+SW7S6qEk?CAi-FHcu0-Cw6N z+-3o7`IYw9ep2oRLjTn7V_%=5Zv%feMZW+(j+}yguyV+U-Vm|?4XHsxLeP+=NM5@D zdS;Slz0%xn+#smT2LW{|g;E%cD!9y{u1x)QH(Ui@2V8#@qUyj`puD|W2aT)XAwXFx zeB7~n6g&aA{wme=Q)9foR!~j#tD>*$91$X0z*jKMp>cmLS6cRGjTh?F0J*}k)+^Bb zcxdliL~J7vnm^Se#a;%)-j|9Ke>uS4gEr43h$j@+gB05gU>^n2V(ys2N93ieNZtel zHEqsv1&Q4X#9o?;3nn>0{F4C6DA1gq3}L$>=iJFeD`|a?J&8F;z2ypbcW+L`)(5o5 zsVY}QZWi+vaPf+J7QpcosGw{VY8bx_xAI&^+z};n>*J*OIS@ty|4u*M-O^7Gp>hfD zoOn=4c*&Necy&PfiDMn~r2vLea5*rBVZ_!_np%e!;)D!nuKtPPlv}&YVwB;;zRz%oNYAK7$gv|n&ALbLR_7NW)(F3OTDnc1y z-=gGUA#7cgFvIRe2~!WJ+Q2Ab?t`H{j1p$p#wcOxq5eR*q#kkggkK^VobeUxs}psT z{2?UYEj3_;Q+X_)d}m2TW=W&R?kRDkUloQDCLpLaR3rOqyvgh$aTu~Wv*6Yz>bQZ3X_$l*X=nSLHIG`rFxXkz0A$Xxn zY>(H&;FqN6Yr!8%(T{<@nxaDqAs;+8WC0pdgNB4DmtIRgod6z@q*<>t*BLjRc{40I zs6r`>H!J9Ks4Md#<0{wL9H^d3&{PGp>R=0cEZ5KF2O9H~_fix>SGG_zGTj z{3~~k2$3x~DC|svfhp%uO3VJKCaH%!9hemDa_h{L?~ASXYm+iairZ2L4o} zBIpU?o5+D_9Mr6;&SM(Yq8h0eVsTMHCg@?4sgF=gT1X0qLiNgqJ*FB)nvW zC*I{{X~%lck?@lI5?+#@-j!$r)$LST<@7P}D`(+?GKHZZmyDyA7Y zv>z%~Z#WL)hk6fqKQM-BV(V?|;rviF8;=Zrs9>5ydlh7Xbn_nPdHA8CW&yzug-cER zFnKK*yJV>57%tgNqIO^`mlR)_9@ZsSB5)yqODZS=X`Pjac(|m3K_IxK@U1Q?cFEn4 z(x2ts69i8i`cr}z41JMct$Po%PQgZdC6l~{iMK|sLhvq^W}^aSI!>>Kvs0#g`1olf zuRt$wi8m@(1EixxH+$YiktGR*q~$`NS84kIEf05TISGCbK&=(1^ka#N%QpokQbI@} z+!R_L6e>#*bTYQrYT8Ipt4unr*&R-kyaH*%ELkxU)N=33vmbT_nSc(=W(uT^lS}l< z2fad)ppfW`q7TQKg!rIBD3`3?qno`F22t+lr|# z1-~{$-vs_tivB5hB{>E8pjF6+7n30i(2yE5Bm@mu+vFyP;HdZYjU-573>Av*&HFNq!uy+(h})=2@V3vPob5(QNg2tTf|F^ zmjPyb1#db2uAL)7WES`eraJVHnyM*M`;Kq2U#?e_DmeYVIlKcEKiKSp$ejdWGX-@( zIJ_fVZ-Hk8^$rzTDCMju!qvDqgr=z|u`zyl|aV3F(Eu z=;(`GyzrM(@xtG5^stKub(hpy3Q!vbQiF2|-FEgQC{+`olskyM8!7iS+0=o3Z>zup`Zy-Niid# z6huM+P9({GB;<}r$XJ6%KS0-2pqiFs%-KEhlsO^_Wc+fG&>$rRl2ir0U`Z9c0@O-v z&W92!Qk8Y7d}E0Z%Uz+;GP`PB1WdXfBiiK_X3*r6&^IU z0%=Dk!7Amgt8xz2`b6>3l9FGb;29tj{cFVqBf``rh~Vz7Dco-bIDzsMfh0hKV7k z^^0Rp91;FaM_asb)6n9D|3fNXxQbz&RDH29An$?z)WAv!LGuhzUx8s{Ew@C~@&+4SRtCWg*W>(qE9IzaZ$3M@n_u zZQrvoWF&RuD72jdwGDZ-CwXm1^4g%h);L`@C};*GOd5CPxQjs5=|s(NlCAWiRH!X9;Al)Pm|(SWmjx^$H|-RJ48Wxl>1; z2Ytz66v%QuMyO>IZ>}nv1AscOz7P;@g>DS_gs6~N4WcTD2Z=bpjU;o|E!-akZ~+C% z%AN97W*Jw54GNS}N--8BnQTDDU5{`#C7NFbwRHIjK3!^;bs4PHfJ~?`{rYDkbjcYv zWqlo>(fw}1CtSk%kz6I60!WYgvxuJv4@XyUIuI6H!j+_2>mn9!!p{a$v&&3Uw*nYJ zfxPLc=%QV(N3L5QPr1puNmSNxcKW4}sO2RxqE>Jk}I_W_itKw2h+1f7$$ zoU~S@5m%rJB;x4nt~J~noX`bh)UuUW&3R;@K+_yA&`iN`(c)<%;-rRh)wEO~)O~#9 z>+X_;`j^TE8;p;<4V-MSL#gb3O1c$Liz<8s(1>yLh_J^1bbgjV=c+&zsF_VBn8v7J z9mJ@PyRPMa2f!qv;7$M^-!URYj)jBXM&@?|kz36)&ZKI8wus2CH=XB9Q%RMuPdHY9x9KKN~ZyZPXpZI{REJ)McQ-8 z)eu_rDbyI8Ug;H~2LWuWU^k%8=jPAQdtp(RyU6tll)hH|(_*3ArLHB{PiGr?UV1LM z4QW3t_>?Y~&YjW~$j$YrvTj7!VvFD&Uq>oCkrY#b)cS53WTnd}+S=CT{uq6nA8 zpEOAt=&HOfm(?yuxGerp(ZJ%@ej}Hy=NwYFEdF zrT@RRg!q>a=CT^^Bv?H8JUXslBQ4))LnQ zJOHG}74iCjtCR+~gEV)g((NVgT3|78mjmIt1N`T}OTZf`ewueOHmL{Few60PmqNb_ z`KEbaC;oci2H*go1MlHV$LUP{U0x={2cFVAo=T_f>^@)+*paH|t>CKrJwOiI%O}#~ zyYj68#sQN7*=PV$9UI?VesdSutU2#i+a4Ego^JIWYBAO22`gu^OIhhwWXWJ)#X4la0N#`t^~rRzPKB>6wsm~TWfuYrtDTxW57$_6?ZkHg7Xn24zW}@lyaMRkyZP1lDG;u) zWZppTO(26@H83tEKUUln;*SHS0@HvQz)64(!mkF_0O2~EtaMuntOS|>9d!?vbPjPL z&mhxETnEsZl27x#4qpeY_od>~yhq_b4m^>HPxCSy$JFUqowp5Fns<7NFT5S-04@aj zfPP>Y*beCU^DZDnSH>1KxayC1#SbvmCoxj_?H7$0%N7Q1AaK<8q%lJsI0Wi z0qBFk13SaDYoIg4@VBtXA+qaSSum*Q>#ZUZ#0h3j#U z7lF5c+nN6k0O1fp$g2^**AcM0fpD!wt_f%cwDt{Gn!hW>e;izM<8DCDHsP9yt}15+ zaYXKeImSq8t#vd+?A2U;ZB=B_x+0_@H)Irj4t%je0t_E}{HeB)nt>MGL zk-%RC??Rv(=m)|j*;@cTZ#b(}OVKN}vf?2V4eR4ZHz_3$r@jQ-m)DCZS9v zS@E9%!WGuHGhoaD769q>t9T~^TGxiSvGNh`R^T?^Uf=+55J+FrVInXYmkwQDEC*Hq%6knEt|G{lfcm-W z5U%S$?gpM9FKq}f1}56OQFxp;SOcUEQ3L|8x4g2HJ*aZ)$6s)7{ld5X~8G=@&kyb*QVm zePGT&S4Y=yVfJ8eZ})(gZtW_z^l$U5-qs7}Y+bk@zhM6C?ylm{*4b@^;$ZKJYm?h`_qJ`W>%=Fc{NT2}!hqoegYE5w4saZ`zkt^m zyU^cX?2RSJ2ONhUDt3{;_=8<(M40H~*NQC*ye7U!8Pz5k{W7Fbn6s6sYj>oti z^y-veyvwZACUVsuj;r8(4E>|(hhMC%B&bN;XF9yHc0Bw{ZH9Yg?R4(dj=!_E#>tCc z;bN=Y{q3l>2Xr zH$dSXpMqjZJVyw|h`PDjE8&_Iuo8i3E z_@t7n+z9dh+O^>6F=?F3&0>#nqtPZeGTO*g<;ETx?ZUXKaq|ncQ(T@l0_k2++sfUI zE`9_~kI9v_i=Dh|Q{zWdjm4EttAB_TU_J(=gKkjz1Fe+a^|EQsKySz3?2f+Dsqmd< z+o-*3xV>YZO_DwbrY>ft_THh^Zq0FS_AGAd?k#SDa*N8ND)r*B>SL;pYPHqXq{i89 ztMi0_%Q`i(a#Wf5ST!@;tf->e=C;6DnC4V6nj=EoF_Nxv=manZZkQheqY1!x+oR@D zCSX$?HaX^f7!1XTtul;Yw(E z9N2t^aa`ZmOEomPX<(N3N5D+^kH&H*#B#EP$;|*e-Q_nE%xpIc%_mMj5l-p~f+5&eCzr+T_T`v3FmBwRKX0RnvL?bXSL3`H=O#W5CSE zG@>nV(aDIW-mu8=CdG29O@rf2iFqf2^*f#`WuimhqyA;Jd58XWbk#QBzm6{JRT=A5 z^dB?iDKYkI>`BzYdeR4(eJkzk`LAn5(9yMZs5sExG0^p{R|Ptbq~28RR*Bo)&|%N0 z6%J3Wr5NqT$*VB3-8CMXt50S;G#5KT5{xPc&j!OyxXU)~5$+4lHsAUcS4;15y;S)8 zV29sR80hGm-P6+6*;UjsiG@+g`swpSE!rz6T|F@_>WN>+vSg>DU6tHO?VqaM*v{Bv zX2A-`P+{{y?lwD2PAq3#M>CG~TCF6^aW!{Z?5E>cjqw(%8PhP$n1-DfV;c93r&$y= z)H*W1drl{cLH>>Z8|L3scn{34Q*UYW+iFIVYA=+h~V4C6KwXHO(NjHJlbWDmHC+Yl5&;smfgHqhq1A80(5L_U(P!^~6{) z#y%fo{T{2z>F*Y1R*b6$xibyF zH}$X*RS(Nm^)TLhQxDW8N3(CL9&QxbXS%vYECDMS_^8c!|EtYk++xevz7X$(C|R**tUXnXq8jPp|+-XsN1Y_ z>3sM0Top80HpRsfJUdtoFNmKVtOr-A!=rRHLx9zyncPVsz9l(18BXSkYu!*?(=hFf zSY~=gr(Eu4e9nFQaY)Tz#?+$0FzuO`xwP7|ZoU%C)X-|ra@7jZ%%3!#Vy*OKEx0;P z@wqsK_ED^vv}Z!j+$~+{>ceWP0ma76C1BQoeP9-w0gH1$HsP)}X zD*C8F3y2z-G~OqWUzAQTYP{0@Q8Rpv+TAvHYGZpaHaSmW%&FyBz$9x+c-GJf&*fun zu6%6ope!FVyV4j&pA2oG_Oa9&46Q&-YbKZsh7;k*1FJH(RK`iPb!myi=44goOY#Q| zX;qo$h067+GXE-6wXMp$D%6@^;~-4#Raf-# z8jG!4HiKEN%^DreLz?3!mS$dz1YU5yW_yi66*P32a^hKK#0yxOC;zC-oXe)A_4p>a znGMYDF+zJnRhdhuyN$b*na^2Hl1u7jH7UTOVD46*UN9?E4=+|TJvYJQZbfg2Wd^`3 z$8BIHJq%`fZ3nX!|00;#<{~g_kR4!F<(**G;)+#%C67t2QkGi7ZKI2KPiJ)wy)0-} zmAO1Ye^01VRb{S9&^;a{PHT>;%r#=D!d01X3RNAdGB*lUWvep#g-Xw=%zsW~Q`~#R zwSvBzpjWCpStt8laV_7+giZtqy7SKNifg{oTN<%6wU+5@k zng?7fR5Mal<{Lsy^Xr9LVc$%+H)~W4FHiEm93|9Qgw3!zrQ zdxR#wQkD5{o@Q8Y}Am^~qtVo3T-$OsvwE zCHeiH=Mra%UzvzqF4Qb`Rg&T>LM_WZLah#ag_<3IU#KF>A6+9x; zlI>3f{!pk@^Ol7BEumJ;+Y|187fR!Bw}O5khBeNUiP#T?njhVeaQ{T86?9j^{d1vK zfddKmLC=j-JT8X0#or6nLwHr@DWNtPx-xych-XTX1LM{NpQ2Mfja_KxHYhMm~4w?yglHiz@xEBNHS>O{SsKy`K^WDM6EJSO1`bNb6;a<)DWw`V4pSL3tXm4L7We z{`l9~n1lU8#kRqY_V{JsFVmJU9}L}w!Pi=ms=DX;8LrkP`vb0hiLYgM$xK+w{!_rh zDG~9^jIR6Hh~tNPvl&_FfqAC2zNP<&x}|1-%FGNfYvf7QbRILm+XA+Dy}P$WdY^BY zHa)F7e+Y~bjJqkJ?rk#a*qWs(GursIw$#?1rJD|BrG6}ql_r*p%CrWo@m?*|HjR-+((TWzxigN zxBEBWEQBvx#{9tH2)GtWj-3{?Cl@Sb`=LB zeT|e?XU_NaLKpg@e1A)^eg48IU+5|HZz>eqwnh2&mTlc#n>q)hw%(q;?!wlrtv{nY zCv4hV1`Bz{4oMBRMENak{e!(dt$Ds;8Z3w$aP&Z6y8Gregf9#8-K{(>ZZAZ9q19DvkL#|p?ZE&pw|q-$SCr55)mTe+AwL-9ds?aT zmbOsi!R^JC9!!xR?8y%l+M;}0ckcl7Q0q`fly7YjuDH(LA*{HiEp5L103yA`d|_+X zV7{e)(*UV^dpCC}$-t)WA;OOC7O}eq@@-pX|8|J{va?p4NmCXEI0%v79G!pOS^AQV zFWb=F-PHJbzD!ipb@Qnj`3?^{g?d`mVzgV(pXziMik`9>xApY47rH5%FDq4eN0Hk= z*QO%(!FJ~jn_7B$S{x57$`^b1xU!eZb6l{m(8gDqh4x^wu3|^8Gl9({vZtG`WJ&Kv zn5DDT>4++n*VSEcbI@>0Hx^&|S!StT_}p6uQnjQolq$44Utjv!0T$wIgORy^NnD;r z*`B8}M0wm6W7k`K$le*HWuQ%ypAlwOG)AdtN#j}hvsSE{*RU)q6oLw43=<^~X&8T}4cXbCF$v$SwU{>M-(zZG{#*ftDUpD-9Kg1~8WTWm4Kw zZ>u&MBJW$Hx1+=5)Y!F2&HJg9=V#BDJ2!i3T|-@cc6N_7+G#z7_Lkx{=$8Jr&eMYL zi*D^Y&GmrMvYWEA&m907EbMUo4*mItR$t*}XLl5P^}T7^=GlGyy@LgOxF2R=Yg>WN z!zYbSg0CBKg4re9;jV$M)~@cZ!EL8?cJYCw8j)w;j<~yZXqUmv(xWD}=81S2i|Oz_ zq6XT#+PjKfNMQjPK0l1f^TTpb7C7eKYQF8gMJ(){N`foSJ>%2))n}e@{_6A2T6<=G zjk-*WS$V~(1@jYgGrA4*GEf%ValA9m$)9uP(j_ZDCtbJj8}#Z#MO+wN+crA|)QF6l zV$nMr=$>*+OSt0P&nDxp)VI#6&RBF^r-yH8LVwHisVk{zdb~&9-*n9bYwIqw6o>k# zOUqW*;oUlph^_c-e(PM_C^WxS!t@c169a_;-q_LCJ0J~PyEnVRjULJnXL;jB?OpS| zhYrUss+20eeXhJ!8g?=n!1%lh`#go=%!9p~^W80sBh+!#S!YmC(S19s+^h?-;>W35 z+LhJ$D;S8(2!+qbQ%^FF+hMQKvw2uWVv_t;a^pjzR=Q|cPv1~~Ax~F|&R=RHoyMWw zA^8GLvBfoo4VUn{aH9d$TZZUfFu%pRHG1Ydcu*%zUvHo5d^RE!-4I~ikjQ>jyI(dY z>#l)z4W4fBPeusE^r)DAW>Sq1@}{LSAOB;DI=D zMzdKRu!vzi8XdJJ-*yDY+WqeCocI&KMybrr)H{FWS?8|IFC9DoLe$zdh*}-}J+hFc zShjk}8Ts>8pO>FcSM6%sjBZlSv6n1enxB_%D-~RWWIMme;K~T8#bogn5|W=d1Dm`0 zMl(lo7(m~7$O#pXzZuGFGUxLlm)$w%uP_%~D!1Cw#bn$T+H&kTDiy2i>uC)ci~D@G z=UMtuv6!C}(R!F7h%>vbIX8dS$~8_tdXBuNCEs-9S!;z)Je)cy&z|r4k-Axf z>t^$!HNH>fSrp{YIA>Md!_GSIyt6*Fa>+{O*LR~z_<$mxcbHc|uJ#$s=+5^$9z|&Z zyuHxho3|d8=4^Wxl@H$x9J#r|Idh%>bmH9U_2yX9RDHyYd;J);DU8))yqd%v(xzkfG@mZ+X})^0X*@ucO(;ylDaUZe zKAgH8hf$X})Q#)T7;+Ysx7jLXM(=ki-Sm)ZXBbn-&pW@7)NS)37G@3aqMyWvAxTHA zSy#hJ%}D2+dCpn#Jk2h|n1P*9k{FskT@C3`Rx`24v|P%@-m=_S#nR78n4@OBq-<*r z4ZsYNXRcn!LaDv0qeHq{?j=!$5NB0Q6!PYqEAzSAyr|gAG&f2@weWAC--VTvch-G8 zTd@%D>FRIci9-Xgy?cE(nT0gGuQiLFdybnTwC&(#P)~Pnk08%%T65;grFn=W9}!C5 zS~6-UZ!t%=PU*rl)iiQ~IvNo+{&JApCNBd6|4% z<^K3b_~rKQ2@@*^$C-j-$-atw_!alT2@^ZK=%~6V-z@w6;TPQxC%Xz+{Xv8Ad_ALI zcW<0mFQ=S(jnfrOvF4 zPd5Ir@u|iiEtU4=x-X;*{SsmLh4{t^8?o(*FITO*ta9bW6|yj`)sJO2Ja{&3wT!k} z`qz!l5aoHPZf}y84tBf&e)fdyjzigD7V)!qOQI7CFM`vi%fDQu+FYHf+&}Kys~=qb z*rCdqfqXk@^$K3UCcJ7w{n>JWWfxaeZXEaRWpb;r>MH&83)6btt6ybXJ|SDRpwcuf zuZ!phk0Tmx(1^_laQ= zpc_3sn{aoEo)3Kx`gtFJ8sRNfx$G4br1WP)FF1;}bZ^8eOMcBy<+l(YF43J3SJdXR z`t?wy=T8zuPeC_(dI#Zxap>dozXW>gF}bYtko;E(Z-u_a(;91@rhPJm75uLFU4&PU z&t->w{0|i2FO`1)eBZIT>=Z)f_rJ%8Z<>(A-&+>{fX_>T^3yL2hD-Dxr5Zr=_d+D0 zX#L`2xJ3VBAP7aP&;ER3E~{dt-)n@gL$`ang8W-2CGp3Wm8W0+50~=OuO5a=^t3X1 zMj1WZ=w13X(+c`WOGr$p^q(k`KckH1@KJn8{?ldg=atbHl+lGUx(|9`LoRzMxyl~; zDE{_`b6LKqLBFc#ccBlY=xfT-UtdQ5VHvG4I$YBCKpCxbRN+$mV`X%?J$_Uc|Buj_ zMW(Ox|2gy&=-~hV6Z)i7{ABl6uV2S} z1$w5ZKLGu~|B%aOJ$*d%Lg=W&`f=!xelzqd(2x1}ZO{i# zXZ-Q>#n7uhnbhwZ=sxI`K7JqcebDmulOH9FMP!6C;BJQ&CntK1?X_ezkX3h zr~g`t;*Yi|&m|Gfheh!vn)68UC7P2(@g;gT^mYF|m(@HheK?gCUy47yj9yko^Hp7Z zNq$`!-Bw2PQBZtIzPx|)=}L6+V@ZGB4ZS!;m&^BI*X=uV*~`dP?Q^+LHcls{?oGfd&=nVl+h2D(NC1o&z8~uR7RJVUtYg|MSl4cNqydiZc5R| zXkze}^q*WtPkRSizf>JArJqwqFD#?aEThjUqt7p+*O$>9Wpr;Dy{(M?QW>56fm@q@ z-l=~3%F^FjM(eLBgiH1RZW;akGWzK<`e)Ejrq&z3D2uO%mz<{Wq%t~`tx)BEi1@Hx z6-R$LAx)oFM(eLAq~lx5=%F(D_n;rHu=Ueq`pY%YcV57A59N#A2feg8mtE%R{{sEU zCAqAgK^6aJ(0z~Ed@zae;vn=bdH!makN+F!1Eins=_jGD`i#v_O8*n+@ccHJ$?Kn> zkAGh-yWPv{7trrK*2ZVazXcth4JH2zme`L>&1LJny#7+de11@NgQq7!-}T|7ejkFq zoAuFhAAbV$h1cY=_jvl_&@Ze?>c0@W1Nmh>{!HjwDNn<&^f@1T-~IM1C4E|;@B30N zd%BPBl04}(o=UzSx}ExKeii*C=*8#dvK^lO3UoK?%YB~KUubCJc_yU45&AgjMj!tz z=v&a2z~y%@$bpNK`d$xRGtSn(lUV8uUvOb6Gw4D87Q@Z*S55Pru*j3D8UNr#>Hl9Q1A2FYDhs$R{U-Vbf7f4$xEz1h`bzTqp|hvh`cw36 z(5Ihj>mAX54*hVd{J({M;B&d`9X|cvL5IJRCw+g0J)fukLBAgpujfs**Cc)*`DN%g zvHy*X`^x{{pl_R!%eMObj-@U2gUTBePktYOE>b_Omn44z^mUIW{dF$%*=usy8+`n! z&{G)?^xP)-CD0ol%w;e4^rxU(n-Y7hguZpMt#>4^epF9;G<*4G;$OqxvD!>gUV`NR0(w8?hyMEz^mO`PXz%YskK4fd&!>MHdj7&(_EFXa(*HT=##H}(9eVNn zq&;i(K%EQy=a}eN=mV+t`+_=(->=X&Fj?X&v2Pf^ejEB~>hq{CzaBc>KNdo#$G;r( z4PU0ed;L~GKQS*EPc}k#o%F??7Mi9osLG{l5?W67~xH=_%-^ke}$~e**n_ zLoWM_r~d^y>}e|fYtYrSU+~vAp(mvJpBK7JTF><>-Ep1Ywd z$^T{_|6g&$cKTbVr@!pwt-p_p_CbgJt%>;GA45Nc{e!*kfu6B9q3?%&iTdD{&R_oq z`X*N0!dKUTTJpD5Cv(&%U)Bg+l;nj&fDwu!U zssE!sej@Z0^q=Fse|-SDgY~%fQ&ipw&|zOy_CE>wYQ~G8-#YSNO8VtqzMlALf1k_J zRia6J@~{Z{@wh*Yij@k-;e)<@p&!uF8XV**K>@Q_r~dKqm9JhiG9|2 zeK$j=*CPYak6q65DF&7P7b~9nhw)(^>9}_3HZiJ>t|C6{>8gHTgWkn>zl?aLAAvrA zKL&gJ3G~DC&){G8KzCyQ8D9Q-&<~)0ho`S$et01@UOY~G+P_X@eKe8z9&z*;7yXF% zduZP~efsC1!}@SybX4>bbU*%lwvT@kx*h*n?dhX1?7@`1?xeppVejca{v*V1A7=gI z?Q;@z{{`Qk+{|4HbZs6TG+?6Dg9_)jq&k+1A?0rZo9m&;bDy_w%%r#|(m z`nC~&GWOr+)AvE&n_6#ff!=_2K-F_i+N# zeY`keSiWy)kOQ5Z02tEoNkRoKt~k_V2=D*&OV`n`CFvQotOf>$S_jBirw|Ex+(|Ib z7;$hj-`UaMJJ9CPzHZKc!s72pwCG?i2Z7r*4@5nMmI0k#YwH`*fyK{90jX;^_0$E? zP)q+H$2fGpQRQ$loAarz5*!%KcNVsSceMBR6^cSQD%jBn!aKq~JAulHx4N!@{+2pk z#)~;rRI!rOk9N8PiVC;1bZ;iKvve_Hr@HO%Za>@}r6n9_?cXd~$LVBIjsO-pwFoxc z5gV5G&8#Aw=hx4VbWDT4ssVlq=A#nIXbVSIhfHxh;t7vecpMn@M?Rt5 z!D$J1I7~=K_s~EmNO${SZwp~TMAcrtkX!>~zKM^f zda!GO$hhzY3z9+>oEmL01Ng5M5KNAi#z)-ZBVWl8Cj-f0Y~il52nn}ZdcrlO$JIO@Ri^~)EHJw9^>AIo{8Q(<#KBaq z0NjFsq(wuBJGV@zvkAp6J}~HS*`}1G421g`eB2mRB7>)BTq@zE7$IG$m~q`$OGnN3 z$lVyIHqF)W#L09%chJ`iYSTRNUO=Z8oo}0`F%-BH(3}9)*=A=CC+%8=R0ICA2#(cb z40ozKK13EiQBm##b}X7>&~AXu56Cf;6T^}99GC4tM^A5m!3yKhHM2-t7)R5GF}&aD z6Aynt+aKr6njLxjL2>Gi~2y}MU+kx2lM37FLZ#hLHh)sx^)e-auSme#2q_)ow zF&nt1?W9&==_0$4y{m$ETfV_+8|v2=0?G*$-MWE!r;T%015)2Nm1_X|49WE)V!HhS z=zRB}JJQH;a|;KoKvxd^fe(iY{c*lDc6(cA!F}|ix^(q*Z*z8WUKol)sebI>NdM(e zJ4TkXY1z~tzE?0;c9~N-x4v=3rp8aXHlI?#ws@U>{qPsX+DX>MD(}TVI;W_8h>Q4;6gZ76|ws5>CrG)*UlPr69Y2e{&~Em zwY9%694M+6&=x*<*;F78OH)emXB<()Vo*AurXUZ3M|gc0Ic-nqSvZPvSvCaNOG+-q z={f-ja@uPeMDFDWU6i}ARphSU<}NusyX%Zq=MULC(Z-Fx*aC3Z9PU9*XRoHcQ2N&~ zLw=v|a+1}a#KHgVlE*jkbu9sedwSQQPlro#f+j$6%1?XncOs{Kq;Q3LVy-pua(JN{?*Fp^$?kgyE%n}M!UaO8P%sM5|Z3iCU?gzyeB(VDeMYz_d^N~cA4?h z%IGCEqQ4X;_*)-(b~J@U6Q$=UEJm{O<#4_Ezbd0F2jJKWa_7X +#include +#include + +#include "platform.h" +#include "encoding.h" + +int factorial(int i){ + + volatile int result = 1; + for (int ii = 1; ii <= i; ii++) { + result = result * ii; + } + return result; + +} + +int main() +{ + FILE * out = fdopen(STDOUT_FILENO, "w"); + int value=0; + int res = read(STDIN_FILENO, &value, 1); +// FILE * inp = fdopen(STDIN_FILENO, "r"); + //fprintf(out, "hello world!\n"); +// int value = 0; +// int res = fscanf(inp, "%d", value); +// int res = scanf("%d", value); + volatile int result = factorial (10); + fprintf(out, "Factorial is %d\n", result); + printf("End of execution"); + return 0; +} diff --git a/hello-world/wrap_printf.c b/hello-world/wrap_printf.c new file mode 100644 index 0000000..af23b1a --- /dev/null +++ b/hello-world/wrap_printf.c @@ -0,0 +1,271 @@ +/* The functions in this file are only meant to support Dhrystone on an + * embedded RV32 system and are obviously incorrect in general. */ + +#include +#include +#include +#include +#include +#include + +#undef putchar +int putchar(int ch) +{ + return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1; +} + +static void sprintf_putch(int ch, void** data) +{ + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; +} + +static unsigned long getuint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long getint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*8]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static inline void print_double(void (*putch)(int, void**), void **putdat, + double num, int width, int prec) +{ + union { + double d; + uint64_t u; + } u; + u.d = num; + + if (u.u & (1ULL << 63)) { + putch('-', putdat); + u.u &= ~(1ULL << 63); + } + + for (int i = 0; i < prec; i++) + u.d *= 10; + + char buf[32], *pbuf = buf; + printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0); + if (prec > 0) { + for (int i = 0; i < prec; i++) { + pbuf[-i] = pbuf[-i-1]; + } + pbuf[-prec] = '.'; + pbuf++; + } + + for (char* p = buf; p < pbuf; p++) + putch(*p, putdat); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch, err; + unsigned long num; + int base, lflag, width, precision, altflag; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') + return; + fmt++; + putch(ch, putdat); + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + altflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + altflag = 1; + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag + case 'l': + if (lflag) + goto bad; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // double + case 'f': + print_double(putch, putdat, va_arg(ap, double), width, precision); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long) num < 0) { + putch('-', putdat); + num = -(long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + bad: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +int __wrap_printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + vprintfmt((void*)putchar, 0, fmt, ap); + + va_end(ap); + return 0; // incorrect return value, but who cares, anyway? +} + +int __wrap_sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} diff --git a/hello-world/wrap_stubs.c b/hello-world/wrap_stubs.c new file mode 100644 index 0000000..0616f86 --- /dev/null +++ b/hello-world/wrap_stubs.c @@ -0,0 +1,15 @@ +#include "platform.h" + +/* The functions in this file are only meant to support Dhrystone on an + * embedded RV32 system and are obviously incorrect in general. */ + +long time(void) +{ + return get_timer_value() / get_timer_freq(); +} + +// set the number of dhrystone iterations +void __wrap_scanf(const char* fmt, int* n) +{ + *n = 100000000; +} diff --git a/riscv-bldc-forced-commutation/Makefile b/riscv-bldc-forced-commutation/Makefile new file mode 100644 index 0000000..c32284c --- /dev/null +++ b/riscv-bldc-forced-commutation/Makefile @@ -0,0 +1,28 @@ + +TARGET = riscv-bldc +C_SRCS = $(wildcard src/*.c) $(BSP_BASE)/drivers/fe300prci/fe300prci_driver.c $(BSP_BASE)/drivers/plic/plic_driver.c +CXX_SRCS = $(wildcard src/*.cpp) +HEADERS = $(wildcard src/*.h) +CFLAGS = -g +CFLAGS += -fno-builtin-printf -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -I./src +CXXFLAGS = -fno-use-cxa-atexit +LDFLAGS = -Wl,--wrap=printf +LDFLAGS += -g -lstdc++ -fno-use-cxa-atexit -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany + + +BOARD=freedom-e300-hifive1 +LINK_TARGET=flash +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 + +TOOL_DIR?=/opt/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin +BSP_BASE = ./bsp +include $(BSP_BASE)/env/common.mk + +.PHONY: all +all: $(TARGET).dump + +$(TARGET).dump: $(TARGET) + $(TOOL_DIR)/$(TRIPLET)-objdump -d -S -C $< > $@ + + \ No newline at end of file diff --git a/riscv-bldc-forced-commutation/bsp/env/common.mk b/riscv-bldc-forced-commutation/bsp/env/common.mk index 5548606..241f81d 100644 --- a/riscv-bldc-forced-commutation/bsp/env/common.mk +++ b/riscv-bldc-forced-commutation/bsp/env/common.mk @@ -28,9 +28,10 @@ LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles LDFLAGS += -L$(ENV_DIR) --specs=nano.specs ASM_OBJS := $(ASM_SRCS:.S=.o) -C_OBJS := $(C_SRCS:.c=.o) +C_OBJS := $(C_SRCS:.c=.o) +CXX_OBJS := $(CXX_SRCS:.cpp=.o) -LINK_OBJS += $(ASM_OBJS) $(C_OBJS) +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS) LINK_DEPS += $(LINKER_SCRIPT) CLEAN_OBJS += $(TARGET) $(LINK_OBJS) @@ -39,15 +40,24 @@ CFLAGS += -march=$(RISCV_ARCH) CFLAGS += -mabi=$(RISCV_ABI) CFLAGS += -mcmodel=medany -$(TARGET): $(LINK_OBJS) $(LINK_DEPS) - $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) +TRIPLET?=riscv64-unknown-elf +CXX=$(TOOL_DIR)/$(TRIPLET)-c++ +CC=$(TOOL_DIR)/$(TRIPLET)-gcc +LD=$(TOOL_DIR)/$(TRIPLET)-gcc + +$(TARGET): $(LINK_OBJS) $(LINK_DEPS) + $(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@ + $(ASM_OBJS): %.o: %.S $(HEADERS) $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< $(C_OBJS): %.o: %.c $(HEADERS) $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< +$(CXX_OBJS): %.o: %.cpp $(HEADERS) + $(CXX) $(CFLAGS) $(CXXFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + .PHONY: clean clean: rm -f $(CLEAN_OBJS) diff --git a/riscv-bldc-forced-commutation/src/peripherals.cpp b/riscv-bldc-forced-commutation/src/hifive1_io.cpp similarity index 100% rename from riscv-bldc-forced-commutation/src/peripherals.cpp rename to riscv-bldc-forced-commutation/src/hifive1_io.cpp diff --git a/riscv-bldc-forced-commutation/src/peripherals.h b/riscv-bldc-forced-commutation/src/hifive1_io.h similarity index 100% rename from riscv-bldc-forced-commutation/src/peripherals.h rename to riscv-bldc-forced-commutation/src/hifive1_io.h diff --git a/riscv-bldc-forced-commutation/src/gpio.h b/riscv-bldc-forced-commutation/src/io/gpio.h similarity index 100% rename from riscv-bldc-forced-commutation/src/gpio.h rename to riscv-bldc-forced-commutation/src/io/gpio.h diff --git a/riscv-bldc-forced-commutation/src/pwm.h b/riscv-bldc-forced-commutation/src/io/pwm.h similarity index 100% rename from riscv-bldc-forced-commutation/src/pwm.h rename to riscv-bldc-forced-commutation/src/io/pwm.h diff --git a/riscv-bldc-forced-commutation/src/spi.h b/riscv-bldc-forced-commutation/src/io/spi.h similarity index 100% rename from riscv-bldc-forced-commutation/src/spi.h rename to riscv-bldc-forced-commutation/src/io/spi.h diff --git a/riscv-bldc-forced-commutation/src/uart.h b/riscv-bldc-forced-commutation/src/io/uart.h similarity index 100% rename from riscv-bldc-forced-commutation/src/uart.h rename to riscv-bldc-forced-commutation/src/io/uart.h