From 27cad2f8196793e0ec2d8b9ece64da48df9bb4c3 Mon Sep 17 00:00:00 2001 From: eyck Date: Thu, 18 Jun 2020 12:15:52 +0200 Subject: [PATCH] add a few more fw examples --- .gitignore | 1 + demo_gpio/.gitignore | 1 + .../bsp/drivers/fe300prci/fe300prci_driver.c | 252 ++ .../bsp/drivers/fe300prci/fe300prci_driver.h | 79 + demo_gpio/bsp/drivers/plic/plic_driver.c | 127 + demo_gpio/bsp/drivers/plic/plic_driver.h | 51 + demo_gpio/bsp/env/encoding.h | 1313 ++++++++++ demo_gpio/bsp/env/entry.S | 97 + .../bsp/env/freedom-e300-hifive1/flash.lds | 161 ++ demo_gpio/bsp/env/freedom-e300-hifive1/init.c | 238 ++ .../bsp/env/freedom-e300-hifive1/openocd.cfg | 34 + .../bsp/env/freedom-e300-hifive1/platform.h | 133 + demo_gpio/bsp/env/hifive1.h | 81 + demo_gpio/bsp/env/start.S | 111 + demo_gpio/bsp/include/sifive/bits.h | 36 + demo_gpio/bsp/include/sifive/const.h | 18 + demo_gpio/bsp/include/sifive/devices/aon.h | 88 + demo_gpio/bsp/include/sifive/devices/clint.h | 14 + demo_gpio/bsp/include/sifive/devices/gpio.h | 24 + demo_gpio/bsp/include/sifive/devices/otp.h | 23 + demo_gpio/bsp/include/sifive/devices/plic.h | 31 + demo_gpio/bsp/include/sifive/devices/prci.h | 56 + demo_gpio/bsp/include/sifive/devices/pwm.h | 37 + demo_gpio/bsp/include/sifive/devices/spi.h | 80 + demo_gpio/bsp/include/sifive/devices/uart.h | 27 + demo_gpio/bsp/include/sifive/sections.h | 17 + demo_gpio/bsp/include/sifive/smp.h | 65 + demo_gpio/demo_gpio.c | 255 ++ demo_gpio/sifive-freedom-e300-hifive1.cfg | 34 + dhrystone/.gdbinit | 3 + dhrystone/.gitignore | 1 + dhrystone/Makefile | 25 + .../bsp/drivers/fe300prci/fe300prci_driver.c | 252 ++ .../bsp/drivers/fe300prci/fe300prci_driver.h | 79 + dhrystone/bsp/drivers/plic/plic_driver.c | 127 + dhrystone/bsp/drivers/plic/plic_driver.h | 51 + dhrystone/bsp/env/common.mk | 60 + dhrystone/bsp/env/encoding.h | 1313 ++++++++++ dhrystone/bsp/env/entry.S | 97 + dhrystone/bsp/env/freedom-e300-arty/init.c | 87 + dhrystone/bsp/env/freedom-e300-arty/link.lds | 167 ++ .../bsp/env/freedom-e300-arty/openocd.cfg | 30 + .../bsp/env/freedom-e300-arty/platform.h | 125 + dhrystone/bsp/env/freedom-e300-hifive1/init.c | 238 ++ .../bsp/env/freedom-e300-hifive1/link.lds | 167 ++ .../bsp/env/freedom-e300-hifive1/openocd.cfg | 34 + .../bsp/env/freedom-e300-hifive1/platform.h | 133 + dhrystone/bsp/env/hifive1.h | 81 + dhrystone/bsp/env/iss/init.c | 238 ++ dhrystone/bsp/env/iss/link.lds | 168 ++ dhrystone/bsp/env/iss/openocd.cfg | 34 + dhrystone/bsp/env/iss/platform.h | 133 + dhrystone/bsp/env/start.S | 54 + dhrystone/bsp/include/sifive/bits.h | 35 + dhrystone/bsp/include/sifive/const.h | 17 + dhrystone/bsp/include/sifive/devices/aon.h | 88 + dhrystone/bsp/include/sifive/devices/clint.h | 14 + dhrystone/bsp/include/sifive/devices/gpio.h | 24 + dhrystone/bsp/include/sifive/devices/otp.h | 23 + dhrystone/bsp/include/sifive/devices/plic.h | 31 + dhrystone/bsp/include/sifive/devices/prci.h | 56 + dhrystone/bsp/include/sifive/devices/pwm.h | 37 + dhrystone/bsp/include/sifive/devices/spi.h | 80 + dhrystone/bsp/include/sifive/devices/uart.h | 27 + dhrystone/bsp/include/sifive/sections.h | 16 + dhrystone/bsp/libwrap/libwrap.mk | 54 + dhrystone/bsp/libwrap/misc/write_hex.c | 19 + dhrystone/bsp/libwrap/stdlib/malloc.c | 17 + dhrystone/bsp/libwrap/sys/_exit.c | 17 + dhrystone/bsp/libwrap/sys/close.c | 9 + dhrystone/bsp/libwrap/sys/execve.c | 9 + dhrystone/bsp/libwrap/sys/fork.c | 9 + dhrystone/bsp/libwrap/sys/fstat.c | 16 + dhrystone/bsp/libwrap/sys/getpid.c | 6 + dhrystone/bsp/libwrap/sys/isatty.c | 11 + dhrystone/bsp/libwrap/sys/kill.c | 9 + dhrystone/bsp/libwrap/sys/link.c | 9 + dhrystone/bsp/libwrap/sys/lseek.c | 14 + dhrystone/bsp/libwrap/sys/open.c | 9 + dhrystone/bsp/libwrap/sys/openat.c | 9 + dhrystone/bsp/libwrap/sys/read.c | 30 + dhrystone/bsp/libwrap/sys/sbrk.c | 16 + dhrystone/bsp/libwrap/sys/stat.c | 10 + dhrystone/bsp/libwrap/sys/stub.h | 10 + dhrystone/bsp/libwrap/sys/times.c | 10 + dhrystone/bsp/libwrap/sys/unlink.c | 9 + dhrystone/bsp/libwrap/sys/wait.c | 9 + dhrystone/bsp/libwrap/sys/write.c | 29 + dhrystone/dhry.h | 423 +++ dhrystone/dhry_1.c | 385 +++ dhrystone/dhry_2.c | 192 ++ dhrystone/dhry_printf.c | 271 ++ dhrystone/dhry_stubs.c | 24 + hello/Makefile | 13 + hello/bsp/Debug/drivers/fe300prci/subdir.mk | 24 + hello/bsp/Debug/drivers/plic/subdir.mk | 24 + .../bsp/Debug/env/freedom-e300-arty/subdir.mk | 24 + .../Debug/env/freedom-e300-hifive1/subdir.mk | 27 + hello/bsp/Debug/env/iss/subdir.mk | 27 + hello/bsp/Debug/env/subdir.mk | 27 + hello/bsp/Debug/libwrap/misc/subdir.mk | 27 + hello/bsp/Debug/libwrap/stdlib/subdir.mk | 27 + hello/bsp/Debug/libwrap/sys/subdir.mk | 98 + hello/bsp/Debug/makefile | 66 + hello/bsp/Debug/objects.mk | 8 + hello/bsp/Debug/sources.mk | 35 + .../bsp/drivers/fe300prci/fe300prci_driver.c | 252 ++ .../bsp/drivers/fe300prci/fe300prci_driver.h | 79 + hello/bsp/drivers/plic/plic_driver.c | 127 + hello/bsp/drivers/plic/plic_driver.h | 51 + hello/bsp/env/common.mk | 62 + hello/bsp/env/encoding.h | 1313 ++++++++++ hello/bsp/env/entry.S | 97 + hello/bsp/env/freedom-e300-arty/init.c | 87 + hello/bsp/env/freedom-e300-arty/link.lds | 167 ++ hello/bsp/env/freedom-e300-arty/openocd.cfg | 30 + hello/bsp/env/freedom-e300-arty/platform.h | 125 + hello/bsp/env/freedom-e300-hifive1/init.c | 238 ++ hello/bsp/env/freedom-e300-hifive1/link.lds | 167 ++ .../bsp/env/freedom-e300-hifive1/openocd.cfg | 34 + hello/bsp/env/freedom-e300-hifive1/platform.h | 133 + hello/bsp/env/hifive1.h | 81 + hello/bsp/env/iss/init.c | 238 ++ hello/bsp/env/iss/link.lds | 168 ++ hello/bsp/env/iss/openocd.cfg | 34 + hello/bsp/env/iss/platform.h | 133 + hello/bsp/env/start.S | 54 + hello/bsp/include/sifive/bits.h | 35 + hello/bsp/include/sifive/const.h | 17 + hello/bsp/include/sifive/devices/aon.h | 88 + hello/bsp/include/sifive/devices/clint.h | 14 + hello/bsp/include/sifive/devices/gpio.h | 24 + hello/bsp/include/sifive/devices/otp.h | 23 + hello/bsp/include/sifive/devices/plic.h | 31 + hello/bsp/include/sifive/devices/prci.h | 56 + hello/bsp/include/sifive/devices/pwm.h | 37 + hello/bsp/include/sifive/devices/spi.h | 80 + hello/bsp/include/sifive/devices/uart.h | 27 + hello/bsp/include/sifive/sections.h | 16 + hello/bsp/libwrap/libwrap.mk | 54 + hello/bsp/libwrap/misc/write_hex.c | 19 + hello/bsp/libwrap/stdlib/malloc.c | 17 + hello/bsp/libwrap/sys/_exit.c | 17 + hello/bsp/libwrap/sys/close.c | 9 + hello/bsp/libwrap/sys/execve.c | 9 + hello/bsp/libwrap/sys/fork.c | 9 + hello/bsp/libwrap/sys/fstat.c | 16 + hello/bsp/libwrap/sys/getpid.c | 6 + hello/bsp/libwrap/sys/isatty.c | 11 + hello/bsp/libwrap/sys/kill.c | 9 + hello/bsp/libwrap/sys/link.c | 9 + hello/bsp/libwrap/sys/lseek.c | 14 + hello/bsp/libwrap/sys/open.c | 9 + hello/bsp/libwrap/sys/openat.c | 9 + hello/bsp/libwrap/sys/read.c | 30 + hello/bsp/libwrap/sys/sbrk.c | 16 + hello/bsp/libwrap/sys/stat.c | 10 + hello/bsp/libwrap/sys/stub.h | 10 + hello/bsp/libwrap/sys/times.c | 10 + hello/bsp/libwrap/sys/unlink.c | 9 + hello/bsp/libwrap/sys/wait.c | 9 + hello/bsp/libwrap/sys/write.c | 29 + hello/hello | Bin 0 -> 65624 bytes hello/hello.c | 72 + hello/hello.dis | 2311 +++++++++++++++++ hello/wrap_printf.c | 271 ++ 166 files changed, 16803 insertions(+) create mode 100644 demo_gpio/.gitignore create mode 100644 demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.c create mode 100644 demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.h create mode 100644 demo_gpio/bsp/drivers/plic/plic_driver.c create mode 100644 demo_gpio/bsp/drivers/plic/plic_driver.h create mode 100644 demo_gpio/bsp/env/encoding.h create mode 100644 demo_gpio/bsp/env/entry.S create mode 100644 demo_gpio/bsp/env/freedom-e300-hifive1/flash.lds create mode 100644 demo_gpio/bsp/env/freedom-e300-hifive1/init.c create mode 100644 demo_gpio/bsp/env/freedom-e300-hifive1/openocd.cfg create mode 100644 demo_gpio/bsp/env/freedom-e300-hifive1/platform.h create mode 100644 demo_gpio/bsp/env/hifive1.h create mode 100644 demo_gpio/bsp/env/start.S create mode 100644 demo_gpio/bsp/include/sifive/bits.h create mode 100644 demo_gpio/bsp/include/sifive/const.h create mode 100644 demo_gpio/bsp/include/sifive/devices/aon.h create mode 100644 demo_gpio/bsp/include/sifive/devices/clint.h create mode 100644 demo_gpio/bsp/include/sifive/devices/gpio.h create mode 100644 demo_gpio/bsp/include/sifive/devices/otp.h create mode 100644 demo_gpio/bsp/include/sifive/devices/plic.h create mode 100644 demo_gpio/bsp/include/sifive/devices/prci.h create mode 100644 demo_gpio/bsp/include/sifive/devices/pwm.h create mode 100644 demo_gpio/bsp/include/sifive/devices/spi.h create mode 100644 demo_gpio/bsp/include/sifive/devices/uart.h create mode 100644 demo_gpio/bsp/include/sifive/sections.h create mode 100644 demo_gpio/bsp/include/sifive/smp.h create mode 100644 demo_gpio/demo_gpio.c create mode 100644 demo_gpio/sifive-freedom-e300-hifive1.cfg create mode 100644 dhrystone/.gdbinit create mode 100644 dhrystone/.gitignore create mode 100644 dhrystone/Makefile create mode 100644 dhrystone/bsp/drivers/fe300prci/fe300prci_driver.c create mode 100644 dhrystone/bsp/drivers/fe300prci/fe300prci_driver.h create mode 100644 dhrystone/bsp/drivers/plic/plic_driver.c create mode 100644 dhrystone/bsp/drivers/plic/plic_driver.h create mode 100644 dhrystone/bsp/env/common.mk create mode 100644 dhrystone/bsp/env/encoding.h create mode 100644 dhrystone/bsp/env/entry.S create mode 100644 dhrystone/bsp/env/freedom-e300-arty/init.c create mode 100644 dhrystone/bsp/env/freedom-e300-arty/link.lds create mode 100644 dhrystone/bsp/env/freedom-e300-arty/openocd.cfg create mode 100644 dhrystone/bsp/env/freedom-e300-arty/platform.h create mode 100644 dhrystone/bsp/env/freedom-e300-hifive1/init.c create mode 100644 dhrystone/bsp/env/freedom-e300-hifive1/link.lds create mode 100644 dhrystone/bsp/env/freedom-e300-hifive1/openocd.cfg create mode 100644 dhrystone/bsp/env/freedom-e300-hifive1/platform.h create mode 100644 dhrystone/bsp/env/hifive1.h create mode 100644 dhrystone/bsp/env/iss/init.c create mode 100644 dhrystone/bsp/env/iss/link.lds create mode 100644 dhrystone/bsp/env/iss/openocd.cfg create mode 100644 dhrystone/bsp/env/iss/platform.h create mode 100644 dhrystone/bsp/env/start.S create mode 100644 dhrystone/bsp/include/sifive/bits.h create mode 100644 dhrystone/bsp/include/sifive/const.h create mode 100644 dhrystone/bsp/include/sifive/devices/aon.h create mode 100644 dhrystone/bsp/include/sifive/devices/clint.h create mode 100644 dhrystone/bsp/include/sifive/devices/gpio.h create mode 100644 dhrystone/bsp/include/sifive/devices/otp.h create mode 100644 dhrystone/bsp/include/sifive/devices/plic.h create mode 100644 dhrystone/bsp/include/sifive/devices/prci.h create mode 100644 dhrystone/bsp/include/sifive/devices/pwm.h create mode 100644 dhrystone/bsp/include/sifive/devices/spi.h create mode 100644 dhrystone/bsp/include/sifive/devices/uart.h create mode 100644 dhrystone/bsp/include/sifive/sections.h create mode 100644 dhrystone/bsp/libwrap/libwrap.mk create mode 100644 dhrystone/bsp/libwrap/misc/write_hex.c create mode 100644 dhrystone/bsp/libwrap/stdlib/malloc.c create mode 100644 dhrystone/bsp/libwrap/sys/_exit.c create mode 100644 dhrystone/bsp/libwrap/sys/close.c create mode 100644 dhrystone/bsp/libwrap/sys/execve.c create mode 100644 dhrystone/bsp/libwrap/sys/fork.c create mode 100644 dhrystone/bsp/libwrap/sys/fstat.c create mode 100644 dhrystone/bsp/libwrap/sys/getpid.c create mode 100644 dhrystone/bsp/libwrap/sys/isatty.c create mode 100644 dhrystone/bsp/libwrap/sys/kill.c create mode 100644 dhrystone/bsp/libwrap/sys/link.c create mode 100644 dhrystone/bsp/libwrap/sys/lseek.c create mode 100644 dhrystone/bsp/libwrap/sys/open.c create mode 100644 dhrystone/bsp/libwrap/sys/openat.c create mode 100644 dhrystone/bsp/libwrap/sys/read.c create mode 100644 dhrystone/bsp/libwrap/sys/sbrk.c create mode 100644 dhrystone/bsp/libwrap/sys/stat.c create mode 100644 dhrystone/bsp/libwrap/sys/stub.h create mode 100644 dhrystone/bsp/libwrap/sys/times.c create mode 100644 dhrystone/bsp/libwrap/sys/unlink.c create mode 100644 dhrystone/bsp/libwrap/sys/wait.c create mode 100644 dhrystone/bsp/libwrap/sys/write.c create mode 100644 dhrystone/dhry.h create mode 100644 dhrystone/dhry_1.c create mode 100644 dhrystone/dhry_2.c create mode 100644 dhrystone/dhry_printf.c create mode 100644 dhrystone/dhry_stubs.c create mode 100644 hello/Makefile create mode 100644 hello/bsp/Debug/drivers/fe300prci/subdir.mk create mode 100644 hello/bsp/Debug/drivers/plic/subdir.mk create mode 100644 hello/bsp/Debug/env/freedom-e300-arty/subdir.mk create mode 100644 hello/bsp/Debug/env/freedom-e300-hifive1/subdir.mk create mode 100644 hello/bsp/Debug/env/iss/subdir.mk create mode 100644 hello/bsp/Debug/env/subdir.mk create mode 100644 hello/bsp/Debug/libwrap/misc/subdir.mk create mode 100644 hello/bsp/Debug/libwrap/stdlib/subdir.mk create mode 100644 hello/bsp/Debug/libwrap/sys/subdir.mk create mode 100644 hello/bsp/Debug/makefile create mode 100644 hello/bsp/Debug/objects.mk create mode 100644 hello/bsp/Debug/sources.mk create mode 100644 hello/bsp/drivers/fe300prci/fe300prci_driver.c create mode 100644 hello/bsp/drivers/fe300prci/fe300prci_driver.h create mode 100644 hello/bsp/drivers/plic/plic_driver.c create mode 100644 hello/bsp/drivers/plic/plic_driver.h create mode 100644 hello/bsp/env/common.mk create mode 100644 hello/bsp/env/encoding.h create mode 100644 hello/bsp/env/entry.S create mode 100644 hello/bsp/env/freedom-e300-arty/init.c create mode 100644 hello/bsp/env/freedom-e300-arty/link.lds create mode 100644 hello/bsp/env/freedom-e300-arty/openocd.cfg create mode 100644 hello/bsp/env/freedom-e300-arty/platform.h create mode 100644 hello/bsp/env/freedom-e300-hifive1/init.c create mode 100644 hello/bsp/env/freedom-e300-hifive1/link.lds create mode 100644 hello/bsp/env/freedom-e300-hifive1/openocd.cfg create mode 100644 hello/bsp/env/freedom-e300-hifive1/platform.h create mode 100644 hello/bsp/env/hifive1.h create mode 100644 hello/bsp/env/iss/init.c create mode 100644 hello/bsp/env/iss/link.lds create mode 100644 hello/bsp/env/iss/openocd.cfg create mode 100644 hello/bsp/env/iss/platform.h create mode 100644 hello/bsp/env/start.S create mode 100644 hello/bsp/include/sifive/bits.h create mode 100644 hello/bsp/include/sifive/const.h create mode 100644 hello/bsp/include/sifive/devices/aon.h create mode 100644 hello/bsp/include/sifive/devices/clint.h create mode 100644 hello/bsp/include/sifive/devices/gpio.h create mode 100644 hello/bsp/include/sifive/devices/otp.h create mode 100644 hello/bsp/include/sifive/devices/plic.h create mode 100644 hello/bsp/include/sifive/devices/prci.h create mode 100644 hello/bsp/include/sifive/devices/pwm.h create mode 100644 hello/bsp/include/sifive/devices/spi.h create mode 100644 hello/bsp/include/sifive/devices/uart.h create mode 100644 hello/bsp/include/sifive/sections.h create mode 100644 hello/bsp/libwrap/libwrap.mk create mode 100644 hello/bsp/libwrap/misc/write_hex.c create mode 100644 hello/bsp/libwrap/stdlib/malloc.c create mode 100644 hello/bsp/libwrap/sys/_exit.c create mode 100644 hello/bsp/libwrap/sys/close.c create mode 100644 hello/bsp/libwrap/sys/execve.c create mode 100644 hello/bsp/libwrap/sys/fork.c create mode 100644 hello/bsp/libwrap/sys/fstat.c create mode 100644 hello/bsp/libwrap/sys/getpid.c create mode 100644 hello/bsp/libwrap/sys/isatty.c create mode 100644 hello/bsp/libwrap/sys/kill.c create mode 100644 hello/bsp/libwrap/sys/link.c create mode 100644 hello/bsp/libwrap/sys/lseek.c create mode 100644 hello/bsp/libwrap/sys/open.c create mode 100644 hello/bsp/libwrap/sys/openat.c create mode 100644 hello/bsp/libwrap/sys/read.c create mode 100644 hello/bsp/libwrap/sys/sbrk.c create mode 100644 hello/bsp/libwrap/sys/stat.c create mode 100644 hello/bsp/libwrap/sys/stub.h create mode 100644 hello/bsp/libwrap/sys/times.c create mode 100644 hello/bsp/libwrap/sys/unlink.c create mode 100644 hello/bsp/libwrap/sys/wait.c create mode 100644 hello/bsp/libwrap/sys/write.c create mode 100755 hello/hello create mode 100644 hello/hello.c create mode 100644 hello/hello.dis create mode 100644 hello/wrap_printf.c diff --git a/.gitignore b/.gitignore index 1ff2a48..828b8ea 100644 --- a/.gitignore +++ b/.gitignore @@ -152,4 +152,5 @@ cmake_install.cmake install_manifest.txt compile_commands.json CTestTestfile.cmake +*.dump diff --git a/demo_gpio/.gitignore b/demo_gpio/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/demo_gpio/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.c b/demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.c new file mode 100644 index 0000000..8eeaafc --- /dev/null +++ b/demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.c @@ -0,0 +1,252 @@ +// See LICENSE file for license details + +#include "platform.h" + +#ifdef PRCI_CTRL_ADDR +#include "fe300prci/fe300prci_driver.h" +#include + +#define rdmcycle(x) { \ + uint32_t lo, hi, hi2; \ + __asm__ __volatile__ ("1:\n\t" \ + "csrr %0, mcycleh\n\t" \ + "csrr %1, mcycle\n\t" \ + "csrr %2, mcycleh\n\t" \ + "bne %0, %2, 1b\n\t" \ + : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ + *(x) = lo | ((uint64_t) hi << 32); \ + } + +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq) +{ + + uint32_t start_mtime = CLINT_REG(CLINT_MTIME); + uint32_t end_mtime = start_mtime + mtime_ticks + 1; + + // Make sure we won't get rollover. + while (end_mtime < start_mtime){ + start_mtime = CLINT_REG(CLINT_MTIME); + end_mtime = start_mtime + mtime_ticks + 1; + } + + // Don't start measuring until mtime edge. + uint32_t tmp = start_mtime; + do { + start_mtime = CLINT_REG(CLINT_MTIME); + } while (start_mtime == tmp); + + uint64_t start_mcycle; + rdmcycle(&start_mcycle); + + while (CLINT_REG(CLINT_MTIME) < end_mtime) ; + + uint64_t end_mcycle; + rdmcycle(&end_mcycle); + uint32_t difference = (uint32_t) (end_mcycle - start_mcycle); + + uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks; + return (uint32_t) freq & 0xFFFFFFFF; + +} + + +void PRCI_use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + // It is OK to change this even if we are running off of it. + + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0); + + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + PRCI_use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if desired. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + + // To overclock, use the hfrosc + if (hfrosctrim >= 0 && hfroscdiv >= 0) { + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + } + + // Set DIV Settings for PLL + + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + if (finaldiv == 1){ + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1)); + } + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = CLINT_REG(CLINT_MTIME); + while (CLINT_REG(CLINT_MTIME) - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0); + + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); + + // If we're running off HFXOSC, turn off the HFROSC to + // save power. + if (refsel) { + PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); + } + +} + +void PRCI_use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + PRCI_use_hfrosc(4, 16); +} + +void PRCI_use_hfxosc(uint32_t finaldiv) +{ + + PRCI_use_pll(1, // Use HFXTAL + 1, // Bypass = 1 + 0, // PLL settings don't matter + 0, // PLL settings don't matter + 0, // PLL settings don't matter + finaldiv, + -1, + -1); +} + +// This is a generic function, which +// doesn't span the entire range of HFROSC settings. +// It only adjusts the trim, which can span a hundred MHz or so. +// This function does not check the legality of the PLL settings +// at all, and it is quite possible to configure invalid PLL settings +// this way. +// It returns the actual measured CPU frequency. + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target ) +{ + + uint32_t hfrosctrim = 0; + uint32_t hfroscdiv = 4; + uint32_t prev_trim = 0; + + // In this function we use PLL settings which + // will give us a 32x multiplier from the output + // of the HFROSC source to the output of the + // PLL. We first measure our HFROSC to get the + // right trim, then finally use it as the PLL source. + // We should really check here that the f_cpu + // requested is something in the limit of the PLL. For + // now that is up to the user. + + // This will undershoot for frequencies not divisible by 16. + uint32_t desired_hfrosc_freq = (f_cpu/ 16); + + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + + // Ignore the first run (for icache reasons) + uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + uint32_t prev_freq = cpu_freq; + + while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){ + prev_trim = hfrosctrim; + prev_freq = cpu_freq; + hfrosctrim ++; + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + } + + // We couldn't go low enough + if (prev_freq > desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // We couldn't go high enough + if (cpu_freq < desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // Check for over/undershoot + switch(target) { + case(PRCI_FREQ_CLOSEST): + if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + } else { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + break; + case(PRCI_FREQ_UNDERSHOOT): + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + break; + default: + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + +} + +#endif diff --git a/demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.h b/demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.h new file mode 100644 index 0000000..7100f46 --- /dev/null +++ b/demo_gpio/bsp/drivers/fe300prci/fe300prci_driver.h @@ -0,0 +1,79 @@ +// See LICENSE file for license details + +#ifndef _FE300PRCI_DRIVER_H_ +#define _FE300PRCI_DRIVER_H_ + +__BEGIN_DECLS + +#include + +typedef enum prci_freq_target { + + PRCI_FREQ_OVERSHOOT, + PRCI_FREQ_CLOSEST, + PRCI_FREQ_UNDERSHOOT + +} PRCI_freq_target; + +/* Measure and return the approximate frequency of the + * CPU, as given by measuring the mcycle counter against + * the mtime ticks. + */ +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq); + +/* Safely switch over to the HFROSC using the given div + * and trim settings. + */ +void PRCI_use_hfrosc(int div, int trim); + +/* Safely switch over to the 16MHz HFXOSC, + * applying the finaldiv clock divider (1 is the lowest + * legal value). + */ +void PRCI_use_hfxosc(uint32_t finaldiv); + +/* Safely switch over to the PLL using the given + * settings. + * + * Note that not all combinations of the inputs are actually + * legal, and this function does not check for their + * legality ("safely" means that this function won't turn off + * or glitch the clock the CPU is actually running off, but + * doesn't protect against you making it too fast or slow.) + */ + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim); + +/* Use the default clocks configured at reset. + * This is ~16Mhz HFROSC and turns off the LFROSC + * (on the current FE310 Dev Platforms, an external LFROSC is + * used as it is more power efficient). + */ +void PRCI_use_default_clocks(); + +/* This routine will adjust the HFROSC trim + * while using HFROSC as the clock source, + * measure the resulting frequency, then + * use it as the PLL clock source, + * in an attempt to get over, under, or close to the + * requested frequency. It returns the actual measured + * frequency. + * + * Note that the requested frequency must be within the + * range supported by the PLL so not all values are + * achievable with this function, and not all + * are guaranteed to actually work. The PLL + * is rated higher than the hardware. + * + * There is no check on the desired f_cpu frequency, it + * is up to the user to specify something reasonable. + */ + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target); + +__END_DECLS + +#endif + diff --git a/demo_gpio/bsp/drivers/plic/plic_driver.c b/demo_gpio/bsp/drivers/plic/plic_driver.c new file mode 100644 index 0000000..b27d7a5 --- /dev/null +++ b/demo_gpio/bsp/drivers/plic/plic_driver.c @@ -0,0 +1,127 @@ +// See LICENSE for license details. + +#include "sifive/devices/plic.h" +#include "plic/plic_driver.h" +#include "platform.h" +#include "encoding.h" +#include + + +// Note that there are no assertions or bounds checking on these +// parameter values. + +void volatile_memzero(uint8_t * base, unsigned int size) +{ + volatile uint8_t * ptr; + for (ptr = base; ptr < (base + size); ptr++){ + *ptr = 0; + } +} + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ) +{ + + this_plic->base_addr = base_addr; + this_plic->num_sources = num_sources; + this_plic->num_priorities = num_priorities; + + // Disable all interrupts (don't assume that these registers are reset). + unsigned long hart_id = read_csr(mhartid); + volatile_memzero((uint8_t*) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)), + (num_sources + 8) / 8); + + // Set all priorities to 0 (equal priority -- don't assume that these are reset). + volatile_memzero ((uint8_t *)(this_plic->base_addr + + PLIC_PRIORITY_OFFSET), + (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE); + + // Set the threshold to 0. + volatile plic_threshold* threshold = (plic_threshold*) + (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold = 0; + +} + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold_ptr = threshold; + +} + + +void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current | ( 1 << (source & 0x7)); + *current_ptr = current; + +} + +void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current & ~(( 1 << (source & 0x7))); + *current_ptr = current; + +} + +void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){ + + if (this_plic->num_priorities > 0) { + volatile plic_priority * priority_ptr = (volatile plic_priority *) + (this_plic->base_addr + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; + } +} + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ + + unsigned long hart_id = read_csr(mhartid); + + volatile plic_source * claim_addr = (volatile plic_source * ) + (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + + return *claim_addr; + +} + +void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; + +} + diff --git a/demo_gpio/bsp/drivers/plic/plic_driver.h b/demo_gpio/bsp/drivers/plic/plic_driver.h new file mode 100644 index 0000000..e7d609b --- /dev/null +++ b/demo_gpio/bsp/drivers/plic/plic_driver.h @@ -0,0 +1,51 @@ +// See LICENSE file for licence details + +#ifndef PLIC_DRIVER_H +#define PLIC_DRIVER_H + + +__BEGIN_DECLS + +#include "platform.h" + +typedef struct __plic_instance_t +{ + uintptr_t base_addr; + + uint32_t num_sources; + uint32_t num_priorities; + +} plic_instance_t; + +typedef uint32_t plic_source; +typedef uint32_t plic_priority; +typedef uint32_t plic_threshold; + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ); + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold); + +void PLIC_enable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_disable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_set_priority (plic_instance_t * this_plic, + plic_source source, + plic_priority priority); + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic); + +void PLIC_complete_interrupt(plic_instance_t * this_plic, + plic_source source); + +__END_DECLS + +#endif diff --git a/demo_gpio/bsp/env/encoding.h b/demo_gpio/bsp/env/encoding.h new file mode 100644 index 0000000..35e0f9f --- /dev/null +++ b/demo_gpio/bsp/env/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/demo_gpio/bsp/env/entry.S b/demo_gpio/bsp/env/entry.S new file mode 100644 index 0000000..1f5de24 --- /dev/null +++ b/demo_gpio/bsp/env/entry.S @@ -0,0 +1,97 @@ +// See LICENSE for license details + +#ifndef ENTRY_S +#define ENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x2, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + csrw mepc, a0 + + # Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x1, 1*REGBYTES(sp) + LOAD x2, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + mret + +.weak handle_trap +handle_trap: +1: + j 1b + +#endif diff --git a/demo_gpio/bsp/env/freedom-e300-hifive1/flash.lds b/demo_gpio/bsp/env/freedom-e300-hifive1/flash.lds new file mode 100644 index 0000000..6b37141 --- /dev/null +++ b/demo_gpio/bsp/env/freedom-e300-hifive1/flash.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/demo_gpio/bsp/env/freedom-e300-hifive1/init.c b/demo_gpio/bsp/env/freedom-e300-hifive1/init.c new file mode 100644 index 0000000..621a6e2 --- /dev/null +++ b/demo_gpio/bsp/env/freedom-e300-hifive1/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/demo_gpio/bsp/env/freedom-e300-hifive1/openocd.cfg b/demo_gpio/bsp/env/freedom-e300-hifive1/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/demo_gpio/bsp/env/freedom-e300-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/demo_gpio/bsp/env/freedom-e300-hifive1/platform.h b/demo_gpio/bsp/env/freedom-e300-hifive1/platform.h new file mode 100644 index 0000000..806fcfc --- /dev/null +++ b/demo_gpio/bsp/env/freedom-e300-hifive1/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_MEM_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define OTP_MEM_ADDR _AC(0x00020000,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define PRCI_CTRL_ADDR _AC(0x10008000,UL) +#define OTP_CTRL_ADDR _AC(0x10010000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) +#define SPI0_MEM_ADDR _AC(0x20000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/demo_gpio/bsp/env/hifive1.h b/demo_gpio/bsp/env/hifive1.h new file mode 100644 index 0000000..0db2f0f --- /dev/null +++ b/demo_gpio/bsp/env/hifive1.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_HIFIVE1_H +#define _SIFIVE_HIFIVE1_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. +// These are also mapped to RGB LEDs on the Freedom E300 Arty +// FPGA +// Dev Kit. + +#define RED_LED_OFFSET 22 +#define GREEN_LED_OFFSET 19 +#define BLUE_LED_OFFSET 21 + +// These are the GPIO bit offsets for the differen digital pins +// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. +#define PIN_0_OFFSET 16 +#define PIN_1_OFFSET 17 +#define PIN_2_OFFSET 18 +#define PIN_3_OFFSET 19 +#define PIN_4_OFFSET 20 +#define PIN_5_OFFSET 21 +#define PIN_6_OFFSET 22 +#define PIN_7_OFFSET 23 +#define PIN_8_OFFSET 0 +#define PIN_9_OFFSET 1 +#define PIN_10_OFFSET 2 +#define PIN_11_OFFSET 3 +#define PIN_12_OFFSET 4 +#define PIN_13_OFFSET 5 +//#define PIN_14_OFFSET 8 //This pin is not connected on either board. +#define PIN_15_OFFSET 9 +#define PIN_16_OFFSET 10 +#define PIN_17_OFFSET 11 +#define PIN_18_OFFSET 12 +#define PIN_19_OFFSET 13 + +// These are *PIN* numbers, not +// GPIO Offset Numbers. +#define PIN_SPI1_SCK (13u) +#define PIN_SPI1_MISO (12u) +#define PIN_SPI1_MOSI (11u) +#define PIN_SPI1_SS0 (10u) +#define PIN_SPI1_SS1 (14u) +#define PIN_SPI1_SS2 (15u) +#define PIN_SPI1_SS3 (16u) + +#define SS_PIN_TO_CS_ID(x) \ + ((x==PIN_SPI1_SS0 ? 0 : \ + (x==PIN_SPI1_SS1 ? 1 : \ + (x==PIN_SPI1_SS2 ? 2 : \ + (x==PIN_SPI1_SS3 ? 3 : \ + -1))))) + + +// These buttons are present only on the Freedom E300 Arty Dev Kit. +#ifdef HAS_BOARD_BUTTONS +#define BUTTON_0_OFFSET 15 +#define BUTTON_1_OFFSET 30 +#define BUTTON_2_OFFSET 31 + +#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) + +#endif + +#define HAS_HFXOSC 1 +#define HAS_LFROSC_BYPASS 1 + +#define RTC_FREQ 32768 + +void write_hex(int fd, unsigned long int hex); + +#endif /* _SIFIVE_HIFIVE1_H */ diff --git a/demo_gpio/bsp/env/start.S b/demo_gpio/bsp/env/start.S new file mode 100644 index 0000000..4e9f665 --- /dev/null +++ b/demo_gpio/bsp/env/start.S @@ -0,0 +1,111 @@ +// See LICENSE for license details. +#include + +/* This is defined in sifive/platform.h, but that can't be included from + * assembly. */ +#define CLINT_CTRL_ADDR 0x02000000 + + .section .init + .globl _start + .type _start,@function + +_start: + .cfi_startproc + .cfi_undefined ra +.option push +.option norelax + la gp, __global_pointer$ +.option pop + la sp, _sp + +#if defined(ENABLE_SMP) + smp_pause(t0, t1) +#endif + + /* Load data section */ + la a0, _data_lma + la a1, _data + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start + la a1, _end + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + + /* Call global constructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + +#ifndef __riscv_float_abi_soft + /* Enable FPU */ + li t0, MSTATUS_FS + csrs mstatus, t0 + csrr t1, mstatus + and t1, t1, t0 + beqz t1, 1f + fssr x0 +1: +#endif + +#if defined(ENABLE_SMP) + smp_resume(t0, t1) + + csrr a0, mhartid + bnez a0, 2f +#endif + + auipc ra, 0 + addi sp, sp, -16 +#if __riscv_xlen == 32 + sw ra, 8(sp) +#else + sd ra, 8(sp) +#endif + + /* argc = argv = 0 */ + li a0, 0 + li a1, 0 + call main + tail exit +1: + j 1b + +#if defined(ENABLE_SMP) +2: + la t0, trap_entry + csrw mtvec, t0 + + csrr a0, mhartid + la t1, _sp + slli t0, a0, 10 + sub sp, t1, t0 + + auipc ra, 0 + addi sp, sp, -16 +#if __riscv_xlen == 32 + sw ra, 8(sp) +#else + sd ra, 8(sp) +#endif + + call secondary_main + tail exit + +1: + j 1b +#endif + .cfi_endproc diff --git a/demo_gpio/bsp/include/sifive/bits.h b/demo_gpio/bsp/include/sifive/bits.h new file mode 100644 index 0000000..bfe656f --- /dev/null +++ b/demo_gpio/bsp/include/sifive/bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/demo_gpio/bsp/include/sifive/const.h b/demo_gpio/bsp/include/sifive/const.h new file mode 100644 index 0000000..8dcffbb --- /dev/null +++ b/demo_gpio/bsp/include/sifive/const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/aon.h b/demo_gpio/bsp/include/sifive/devices/aon.h new file mode 100644 index 0000000..63f1db3 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_AON_H +#define _SIFIVE_AON_H + +/* Register offsets */ + +#define AON_WDOGCFG 0x000 +#define AON_WDOGCOUNT 0x008 +#define AON_WDOGS 0x010 +#define AON_WDOGFEED 0x018 +#define AON_WDOGKEY 0x01C +#define AON_WDOGCMP 0x020 + +#define AON_RTCCFG 0x040 +#define AON_RTCLO 0x048 +#define AON_RTCHI 0x04C +#define AON_RTCS 0x050 +#define AON_RTCCMP 0x060 + +#define AON_BACKUP0 0x080 +#define AON_BACKUP1 0x084 +#define AON_BACKUP2 0x088 +#define AON_BACKUP3 0x08C +#define AON_BACKUP4 0x090 +#define AON_BACKUP5 0x094 +#define AON_BACKUP6 0x098 +#define AON_BACKUP7 0x09C +#define AON_BACKUP8 0x0A0 +#define AON_BACKUP9 0x0A4 +#define AON_BACKUP10 0x0A8 +#define AON_BACKUP11 0x0AC +#define AON_BACKUP12 0x0B0 +#define AON_BACKUP13 0x0B4 +#define AON_BACKUP14 0x0B8 +#define AON_BACKUP15 0x0BC + +#define AON_PMUWAKEUPI0 0x100 +#define AON_PMUWAKEUPI1 0x104 +#define AON_PMUWAKEUPI2 0x108 +#define AON_PMUWAKEUPI3 0x10C +#define AON_PMUWAKEUPI4 0x110 +#define AON_PMUWAKEUPI5 0x114 +#define AON_PMUWAKEUPI6 0x118 +#define AON_PMUWAKEUPI7 0x11C +#define AON_PMUSLEEPI0 0x120 +#define AON_PMUSLEEPI1 0x124 +#define AON_PMUSLEEPI2 0x128 +#define AON_PMUSLEEPI3 0x12C +#define AON_PMUSLEEPI4 0x130 +#define AON_PMUSLEEPI5 0x134 +#define AON_PMUSLEEPI6 0x138 +#define AON_PMUSLEEPI7 0x13C +#define AON_PMUIE 0x140 +#define AON_PMUCAUSE 0x144 +#define AON_PMUSLEEP 0x148 +#define AON_PMUKEY 0x14C + +#define AON_LFROSC 0x070 +/* Constants */ + +#define AON_WDOGKEY_VALUE 0x51F15E +#define AON_WDOGFEED_VALUE 0xD09F00D + +#define AON_WDOGCFG_SCALE 0x0000000F +#define AON_WDOGCFG_RSTEN 0x00000100 +#define AON_WDOGCFG_ZEROCMP 0x00000200 +#define AON_WDOGCFG_ENALWAYS 0x00001000 +#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 +#define AON_WDOGCFG_CMPIP 0x10000000 + +#define AON_RTCCFG_SCALE 0x0000000F +#define AON_RTCCFG_ENALWAYS 0x00001000 +#define AON_RTCCFG_CMPIP 0x10000000 + +#define AON_WAKEUPCAUSE_RESET 0x00 +#define AON_WAKEUPCAUSE_RTC 0x01 +#define AON_WAKEUPCAUSE_DWAKEUP 0x02 +#define AON_WAKEUPCAUSE_AWAKEUP 0x03 + +#define AON_RESETCAUSE_POWERON 0x0000 +#define AON_RESETCAUSE_EXTERNAL 0x0100 +#define AON_RESETCAUSE_WATCHDOG 0x0200 + +#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF +#define AON_PMUCAUSE_RESETCAUSE 0xFF00 + +#endif /* _SIFIVE_AON_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/clint.h b/demo_gpio/bsp/include/sifive/devices/clint.h new file mode 100644 index 0000000..cd3e0c7 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/gpio.h b/demo_gpio/bsp/include/sifive/devices/gpio.h new file mode 100644 index 0000000..f7f0acb --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/otp.h b/demo_gpio/bsp/include/sifive/devices/otp.h new file mode 100644 index 0000000..93833e2 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_OTP_H +#define _SIFIVE_OTP_H + +/* Register offsets */ + +#define OTP_LOCK 0x00 +#define OTP_CK 0x04 +#define OTP_OE 0x08 +#define OTP_SEL 0x0C +#define OTP_WE 0x10 +#define OTP_MR 0x14 +#define OTP_MRR 0x18 +#define OTP_MPP 0x1C +#define OTP_VRREN 0x20 +#define OTP_VPPEN 0x24 +#define OTP_A 0x28 +#define OTP_D 0x2C +#define OTP_Q 0x30 +#define OTP_READ_TIMINGS 0x34 + +#endif diff --git a/demo_gpio/bsp/include/sifive/devices/plic.h b/demo_gpio/bsp/include/sifive/devices/plic.h new file mode 100644 index 0000000..e1ca5d6 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/prci.h b/demo_gpio/bsp/include/sifive/devices/prci.h new file mode 100644 index 0000000..1a3de58 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PRCI_H +#define _SIFIVE_PRCI_H + +/* Register offsets */ + +#define PRCI_HFROSCCFG (0x0000) +#define PRCI_HFXOSCCFG (0x0004) +#define PRCI_PLLCFG (0x0008) +#define PRCI_PLLDIV (0x000C) +#define PRCI_PROCMONCFG (0x00F0) + +/* Fields */ +#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) +#define ROSC_TRIM(x) (((x) & 0x1F) << 16) +#define ROSC_EN(x) (((x) & 0x1 ) << 30) +#define ROSC_RDY(x) (((x) & 0x1 ) << 31) + +#define XOSC_EN(x) (((x) & 0x1) << 30) +#define XOSC_RDY(x) (((x) & 0x1) << 31) + +#define PLL_R(x) (((x) & 0x7) << 0) +// single reserved bit for F LSB. +#define PLL_F(x) (((x) & 0x3F) << 4) +#define PLL_Q(x) (((x) & 0x3) << 10) +#define PLL_SEL(x) (((x) & 0x1) << 16) +#define PLL_REFSEL(x) (((x) & 0x1) << 17) +#define PLL_BYPASS(x) (((x) & 0x1) << 18) +#define PLL_LOCK(x) (((x) & 0x1) << 31) + +#define PLL_R_default 0x1 +#define PLL_F_default 0x1F +#define PLL_Q_default 0x3 + +#define PLL_REFSEL_HFROSC 0x0 +#define PLL_REFSEL_HFXOSC 0x1 + +#define PLL_SEL_HFROSC 0x0 +#define PLL_SEL_PLL 0x1 + +#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) +#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) + +#define PROCMON_DIV(x) (((x) & 0x1F) << 0) +#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) +#define PROCMON_EN(x) (((x) & 0x1) << 16) +#define PROCMON_SEL(x) (((x) & 0x3) << 24) +#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) + +#define PROCMON_SEL_HFCLK 0 +#define PROCMON_SEL_HFXOSCIN 1 +#define PROCMON_SEL_PLLOUTDIV 2 +#define PROCMON_SEL_PROCMON 3 + +#endif // _SIFIVE_PRCI_H diff --git a/demo_gpio/bsp/include/sifive/devices/pwm.h b/demo_gpio/bsp/include/sifive/devices/pwm.h new file mode 100644 index 0000000..067889a --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PWM_H +#define _SIFIVE_PWM_H + +/* Register offsets */ + +#define PWM_CFG 0x00 +#define PWM_COUNT 0x08 +#define PWM_S 0x10 +#define PWM_CMP0 0x20 +#define PWM_CMP1 0x24 +#define PWM_CMP2 0x28 +#define PWM_CMP3 0x2C + +/* Constants */ + +#define PWM_CFG_SCALE 0x0000000F +#define PWM_CFG_STICKY 0x00000100 +#define PWM_CFG_ZEROCMP 0x00000200 +#define PWM_CFG_DEGLITCH 0x00000400 +#define PWM_CFG_ENALWAYS 0x00001000 +#define PWM_CFG_ONESHOT 0x00002000 +#define PWM_CFG_CMP0CENTER 0x00010000 +#define PWM_CFG_CMP1CENTER 0x00020000 +#define PWM_CFG_CMP2CENTER 0x00040000 +#define PWM_CFG_CMP3CENTER 0x00080000 +#define PWM_CFG_CMP0GANG 0x01000000 +#define PWM_CFG_CMP1GANG 0x02000000 +#define PWM_CFG_CMP2GANG 0x04000000 +#define PWM_CFG_CMP3GANG 0x08000000 +#define PWM_CFG_CMP0IP 0x10000000 +#define PWM_CFG_CMP1IP 0x20000000 +#define PWM_CFG_CMP2IP 0x40000000 +#define PWM_CFG_CMP3IP 0x80000000 + +#endif /* _SIFIVE_PWM_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/spi.h b/demo_gpio/bsp/include/sifive/devices/spi.h new file mode 100644 index 0000000..916d86b --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + + +#endif /* _SIFIVE_SPI_H */ diff --git a/demo_gpio/bsp/include/sifive/devices/uart.h b/demo_gpio/bsp/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/demo_gpio/bsp/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/demo_gpio/bsp/include/sifive/sections.h b/demo_gpio/bsp/include/sifive/sections.h new file mode 100644 index 0000000..6e1f051 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/sections.h @@ -0,0 +1,17 @@ +// See LICENSE for license details. +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/demo_gpio/bsp/include/sifive/smp.h b/demo_gpio/bsp/include/sifive/smp.h new file mode 100644 index 0000000..8e34388 --- /dev/null +++ b/demo_gpio/bsp/include/sifive/smp.h @@ -0,0 +1,65 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + csrr reg2, mhartid ;\ + bnez reg2, 42f + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif diff --git a/demo_gpio/demo_gpio.c b/demo_gpio/demo_gpio.c new file mode 100644 index 0000000..aee9b61 --- /dev/null +++ b/demo_gpio/demo_gpio.c @@ -0,0 +1,255 @@ +// See LICENSE for license details. + +#include +#include +#include "platform.h" +#include +#include "plic/plic_driver.h" +#include "encoding.h" +#include +#include "stdatomic.h" + +void reset_demo (void); + +// Structures for registering different interrupt handlers +// for different parts of the application. +typedef void (*function_ptr_t) (void); + +void no_interrupt_handler (void) {}; + +function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS]; + + +// Instance data for the PLIC. + +plic_instance_t g_plic; + + +/*Entry Point for PLIC Interrupt Handler*/ +void handle_m_ext_interrupt(){ + plic_source int_num = PLIC_claim_interrupt(&g_plic); + if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) { + g_ext_interrupt_handlers[int_num](); + } + else { + exit(1 + (uintptr_t) int_num); + } + PLIC_complete_interrupt(&g_plic, int_num); +} + + +/*Entry Point for Machine Timer Interrupt Handler*/ +void handle_m_time_interrupt(){ + + clear_csr(mie, MIP_MTIP); + + // Reset the timer for 3s in the future. + // This also clears the existing timer interrupt. + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + 2 * RTC_FREQ; + *mtimecmp = then; + + // read the current value of the LEDS and invert them. + uint32_t leds = GPIO_REG(GPIO_OUTPUT_VAL); + + GPIO_REG(GPIO_OUTPUT_VAL) ^= ((0x1 << RED_LED_OFFSET) | + (0x1 << GREEN_LED_OFFSET) | + (0x1 << BLUE_LED_OFFSET)); + + // Re-enable the timer interrupt. + set_csr(mie, MIP_MTIP); + +} + + +const char * instructions_msg = " \ +\n\ + SIFIVE, INC.\n\ +\n\ + 5555555555555555555555555\n\ + 5555 5555\n\ + 5555 5555\n\ + 5555 5555\n\ + 5555 5555555555555555555555\n\ + 5555 555555555555555555555555\n\ + 5555 5555\n\ + 5555 5555\n\ + 5555 5555\n\ +5555555555555555555555555555 55555\n\ + 55555 555555555 55555\n\ + 55555 55555 55555\n\ + 55555 5 55555\n\ + 55555 55555\n\ + 55555 55555\n\ + 55555 55555\n\ + 55555 55555\n\ + 55555 55555\n\ + 555555555\n\ + 55555\n\ + 5\n\ +\n\ +SiFive E-Series Software Development Kit 'demo_gpio' program.\n\ +Every 2 second, the Timer Interrupt will invert the LEDs.\n\ +(Arty Dev Kit Only): Press Buttons 0, 1, 2 to Set the LEDs.\n\ +Pin 19 (HiFive1) or A5 (Arty Dev Kit) is being bit-banged\n\ +for GPIO speed demonstration.\n\ +\n\ +"; + +void print_instructions() { + + write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg)); + +} + +#ifdef HAS_BOARD_BUTTONS +void button_0_handler(void) { + + // Red LED on + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << RED_LED_OFFSET); + + // Clear the GPIO Pending interrupt by writing 1. + GPIO_REG(GPIO_RISE_IP) = (0x1 << BUTTON_0_OFFSET); + +}; + +void button_1_handler(void) { + + // Green LED On + GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << GREEN_LED_OFFSET); + + // Clear the GPIO Pending interrupt by writing 1. + GPIO_REG(GPIO_RISE_IP) = (0x1 << BUTTON_1_OFFSET); + +}; + + +void button_2_handler(void) { + + // Blue LED On + GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << BLUE_LED_OFFSET); + + GPIO_REG(GPIO_RISE_IP) = (0x1 << BUTTON_2_OFFSET); + +}; +#endif + +void reset_demo (){ + + // Disable the machine & timer interrupts until setup is done. + + clear_csr(mie, MIP_MEIP); + clear_csr(mie, MIP_MTIP); + + for (int ii = 0; ii < PLIC_NUM_INTERRUPTS; ii ++){ + g_ext_interrupt_handlers[ii] = no_interrupt_handler; + } + +#ifdef HAS_BOARD_BUTTONS + g_ext_interrupt_handlers[INT_DEVICE_BUTTON_0] = button_0_handler; + g_ext_interrupt_handlers[INT_DEVICE_BUTTON_1] = button_1_handler; + g_ext_interrupt_handlers[INT_DEVICE_BUTTON_2] = button_2_handler; +#endif + + print_instructions(); + +#ifdef HAS_BOARD_BUTTONS + + // Have to enable the interrupt both at the GPIO level, + // and at the PLIC level. + PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_0); + PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_1); + PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_2); + + // Priority must be set > 0 to trigger the interrupt. + PLIC_set_priority(&g_plic, INT_DEVICE_BUTTON_0, 1); + PLIC_set_priority(&g_plic, INT_DEVICE_BUTTON_1, 1); + PLIC_set_priority(&g_plic, INT_DEVICE_BUTTON_2, 1); + + GPIO_REG(GPIO_RISE_IE) |= (1 << BUTTON_0_OFFSET); + GPIO_REG(GPIO_RISE_IE) |= (1 << BUTTON_1_OFFSET); + GPIO_REG(GPIO_RISE_IE) |= (1 << BUTTON_2_OFFSET); + +#endif + + // Set the machine timer to go off in 3 seconds. + // The + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + 2*RTC_FREQ; + *mtimecmp = then; + + // Enable the Machine-External bit in MIE + set_csr(mie, MIP_MEIP); + + // Enable the Machine-Timer bit in MIE + set_csr(mie, MIP_MTIP); + + // Enable interrupts in general. + set_csr(mstatus, MSTATUS_MIE); +} + +int main(int argc, char **argv) +{ + // Set up the GPIOs such that the LED GPIO + // can be used as both Inputs and Outputs. + + +#ifdef HAS_BOARD_BUTTONS + GPIO_REG(GPIO_OUTPUT_EN) &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET)); + GPIO_REG(GPIO_PULLUP_EN) &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET)); + GPIO_REG(GPIO_INPUT_EN) |= ((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET)); +#endif + + GPIO_REG(GPIO_INPUT_EN) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ; + GPIO_REG(GPIO_OUTPUT_EN) |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ; + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ; + + + // For Bit-banging with Atomics demo. + + uint32_t bitbang_mask = 0; +#ifdef _SIFIVE_HIFIVE1_H + bitbang_mask = (1 << PIN_19_OFFSET); +#else +#ifdef _SIFIVE_COREPLEXIP_ARTY_H + bitbang_mask = (0x1 << JA_0_OFFSET); +#endif +#endif + + GPIO_REG(GPIO_OUTPUT_EN) |= bitbang_mask; + + /************************************************************************** + * Set up the PLIC + * + *************************************************************************/ + PLIC_init(&g_plic, + PLIC_CTRL_ADDR, + PLIC_NUM_INTERRUPTS, + PLIC_NUM_PRIORITIES); + + reset_demo(); + + /************************************************************************** + * Demonstrate fast GPIO bit-banging. + * One can bang it faster than this if you know + * the entire OUTPUT_VAL that you want to write, but + * Atomics give a quick way to control a single bit. + *************************************************************************/ + // For Bit-banging with Atomics demo. + uint32_t cnt=0; + while(cnt<200){ + asm volatile ("wfi"); + printf("Finished run#%u\n", ++cnt); + for(size_t i=0; i<100; ++i) + atomic_fetch_xor_explicit(&GPIO_REG(GPIO_OUTPUT_VAL), bitbang_mask, memory_order_relaxed); + } + + return 0; + +} diff --git a/demo_gpio/sifive-freedom-e300-hifive1.cfg b/demo_gpio/sifive-freedom-e300-hifive1.cfg new file mode 100644 index 0000000..b0a8e26 --- /dev/null +++ b/demo_gpio/sifive-freedom-e300-hifive1.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +flash protect 0 64 last off diff --git a/dhrystone/.gdbinit b/dhrystone/.gdbinit new file mode 100644 index 0000000..f53f67e --- /dev/null +++ b/dhrystone/.gdbinit @@ -0,0 +1,3 @@ +target remote :20000 +set remotebreak +b main diff --git a/dhrystone/.gitignore b/dhrystone/.gitignore new file mode 100644 index 0000000..eb51a6c --- /dev/null +++ b/dhrystone/.gitignore @@ -0,0 +1 @@ +dhrystone diff --git a/dhrystone/Makefile b/dhrystone/Makefile new file mode 100644 index 0000000..5905897 --- /dev/null +++ b/dhrystone/Makefile @@ -0,0 +1,25 @@ +TARGET := dhrystone + +ASM_SRCS := +C_SRCS := dhry_stubs.c dhry_printf.c +HEADERS := dhry.h + +DHRY_SRCS := dhry_1.c dhry_2.c +DHRY_CFLAGS := -O2 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -Wno-implicit -march=rv32ima + +XLEN ?= 32 +CFLAGS := -g -Og -fno-common +LDFLAGS := -g -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit + +DHRY_OBJS := $(patsubst %.c,%.o,$(DHRY_SRCS)) +LINK_OBJS := $(DHRY_OBJS) + +#BOARD = iss +BOARD=freedom-e300-hifive1 +TOOL_DIR=/opt/shared/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin + +BSP_BASE = bsp +include $(BSP_BASE)/env/common.mk + +$(DHRY_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(DHRY_CFLAGS) -c -o $@ $< diff --git a/dhrystone/bsp/drivers/fe300prci/fe300prci_driver.c b/dhrystone/bsp/drivers/fe300prci/fe300prci_driver.c new file mode 100644 index 0000000..2d9c52f --- /dev/null +++ b/dhrystone/bsp/drivers/fe300prci/fe300prci_driver.c @@ -0,0 +1,252 @@ +// See LICENSE file for license details + +#include "platform.h" + +#ifdef PRCI_BASE_ADDR +#include "fe300prci/fe300prci_driver.h" +#include + +#define rdmcycle(x) { \ + uint32_t lo, hi, hi2; \ + __asm__ __volatile__ ("1:\n\t" \ + "csrr %0, mcycleh\n\t" \ + "csrr %1, mcycle\n\t" \ + "csrr %2, mcycleh\n\t" \ + "bne %0, %2, 1b\n\t" \ + : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ + *(x) = lo | ((uint64_t) hi << 32); \ + } + +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq) +{ + + uint32_t start_mtime = CLINT_REG(CLINT_MTIME); + uint32_t end_mtime = start_mtime + mtime_ticks + 1; + + // Make sure we won't get rollover. + while (end_mtime < start_mtime){ + start_mtime = CLINT_REG(CLINT_MTIME); + end_mtime = start_mtime + mtime_ticks + 1; + } + + // Don't start measuring until mtime edge. + uint32_t tmp = start_mtime; + do { + start_mtime = CLINT_REG(CLINT_MTIME); + } while (start_mtime == tmp); + + uint64_t start_mcycle; + rdmcycle(&start_mcycle); + + while (CLINT_REG(CLINT_MTIME) < end_mtime) ; + + uint64_t end_mcycle; + rdmcycle(&end_mcycle); + uint32_t difference = (uint32_t) (end_mcycle - start_mcycle); + + uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks; + return (uint32_t) freq & 0xFFFFFFFF; + +} + + +void PRCI_use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + // It is OK to change this even if we are running off of it. + + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0); + + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + PRCI_use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if desired. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + + // To overclock, use the hfrosc + if (hfrosctrim >= 0 && hfroscdiv >= 0) { + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + } + + // Set DIV Settings for PLL + + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + if (finaldiv == 1){ + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1)); + } + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = CLINT_REG(CLINT_MTIME); + while (CLINT_REG(CLINT_MTIME) - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0); + + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); + + // If we're running off HFXOSC, turn off the HFROSC to + // save power. + if (refsel) { + PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); + } + +} + +void PRCI_use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + PRCI_use_hfrosc(4, 16); +} + +void PRCI_use_hfxosc(uint32_t finaldiv) +{ + + PRCI_use_pll(1, // Use HFXTAL + 1, // Bypass = 1 + 0, // PLL settings don't matter + 0, // PLL settings don't matter + 0, // PLL settings don't matter + finaldiv, + -1, + -1); +} + +// This is a generic function, which +// doesn't span the entire range of HFROSC settings. +// It only adjusts the trim, which can span a hundred MHz or so. +// This function does not check the legality of the PLL settings +// at all, and it is quite possible to configure invalid PLL settings +// this way. +// It returns the actual measured CPU frequency. + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target ) +{ + + uint32_t hfrosctrim = 0; + uint32_t hfroscdiv = 4; + uint32_t prev_trim = 0; + + // In this function we use PLL settings which + // will give us a 32x multiplier from the output + // of the HFROSC source to the output of the + // PLL. We first measure our HFROSC to get the + // right trim, then finally use it as the PLL source. + // We should really check here that the f_cpu + // requested is something in the limit of the PLL. For + // now that is up to the user. + + // This will undershoot for frequencies not divisible by 16. + uint32_t desired_hfrosc_freq = (f_cpu/ 16); + + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + + // Ignore the first run (for icache reasons) + uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + uint32_t prev_freq = cpu_freq; + + while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){ + prev_trim = hfrosctrim; + prev_freq = cpu_freq; + hfrosctrim ++; + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + } + + // We couldn't go low enough + if (prev_freq > desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // We couldn't go high enough + if (cpu_freq < desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // Check for over/undershoot + switch(target) { + case(PRCI_FREQ_CLOSEST): + if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + } else { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + break; + case(PRCI_FREQ_UNDERSHOOT): + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + break; + default: + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + +} + +#endif diff --git a/dhrystone/bsp/drivers/fe300prci/fe300prci_driver.h b/dhrystone/bsp/drivers/fe300prci/fe300prci_driver.h new file mode 100644 index 0000000..7100f46 --- /dev/null +++ b/dhrystone/bsp/drivers/fe300prci/fe300prci_driver.h @@ -0,0 +1,79 @@ +// See LICENSE file for license details + +#ifndef _FE300PRCI_DRIVER_H_ +#define _FE300PRCI_DRIVER_H_ + +__BEGIN_DECLS + +#include + +typedef enum prci_freq_target { + + PRCI_FREQ_OVERSHOOT, + PRCI_FREQ_CLOSEST, + PRCI_FREQ_UNDERSHOOT + +} PRCI_freq_target; + +/* Measure and return the approximate frequency of the + * CPU, as given by measuring the mcycle counter against + * the mtime ticks. + */ +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq); + +/* Safely switch over to the HFROSC using the given div + * and trim settings. + */ +void PRCI_use_hfrosc(int div, int trim); + +/* Safely switch over to the 16MHz HFXOSC, + * applying the finaldiv clock divider (1 is the lowest + * legal value). + */ +void PRCI_use_hfxosc(uint32_t finaldiv); + +/* Safely switch over to the PLL using the given + * settings. + * + * Note that not all combinations of the inputs are actually + * legal, and this function does not check for their + * legality ("safely" means that this function won't turn off + * or glitch the clock the CPU is actually running off, but + * doesn't protect against you making it too fast or slow.) + */ + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim); + +/* Use the default clocks configured at reset. + * This is ~16Mhz HFROSC and turns off the LFROSC + * (on the current FE310 Dev Platforms, an external LFROSC is + * used as it is more power efficient). + */ +void PRCI_use_default_clocks(); + +/* This routine will adjust the HFROSC trim + * while using HFROSC as the clock source, + * measure the resulting frequency, then + * use it as the PLL clock source, + * in an attempt to get over, under, or close to the + * requested frequency. It returns the actual measured + * frequency. + * + * Note that the requested frequency must be within the + * range supported by the PLL so not all values are + * achievable with this function, and not all + * are guaranteed to actually work. The PLL + * is rated higher than the hardware. + * + * There is no check on the desired f_cpu frequency, it + * is up to the user to specify something reasonable. + */ + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target); + +__END_DECLS + +#endif + diff --git a/dhrystone/bsp/drivers/plic/plic_driver.c b/dhrystone/bsp/drivers/plic/plic_driver.c new file mode 100644 index 0000000..b27d7a5 --- /dev/null +++ b/dhrystone/bsp/drivers/plic/plic_driver.c @@ -0,0 +1,127 @@ +// See LICENSE for license details. + +#include "sifive/devices/plic.h" +#include "plic/plic_driver.h" +#include "platform.h" +#include "encoding.h" +#include + + +// Note that there are no assertions or bounds checking on these +// parameter values. + +void volatile_memzero(uint8_t * base, unsigned int size) +{ + volatile uint8_t * ptr; + for (ptr = base; ptr < (base + size); ptr++){ + *ptr = 0; + } +} + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ) +{ + + this_plic->base_addr = base_addr; + this_plic->num_sources = num_sources; + this_plic->num_priorities = num_priorities; + + // Disable all interrupts (don't assume that these registers are reset). + unsigned long hart_id = read_csr(mhartid); + volatile_memzero((uint8_t*) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)), + (num_sources + 8) / 8); + + // Set all priorities to 0 (equal priority -- don't assume that these are reset). + volatile_memzero ((uint8_t *)(this_plic->base_addr + + PLIC_PRIORITY_OFFSET), + (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE); + + // Set the threshold to 0. + volatile plic_threshold* threshold = (plic_threshold*) + (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold = 0; + +} + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold_ptr = threshold; + +} + + +void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current | ( 1 << (source & 0x7)); + *current_ptr = current; + +} + +void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current & ~(( 1 << (source & 0x7))); + *current_ptr = current; + +} + +void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){ + + if (this_plic->num_priorities > 0) { + volatile plic_priority * priority_ptr = (volatile plic_priority *) + (this_plic->base_addr + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; + } +} + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ + + unsigned long hart_id = read_csr(mhartid); + + volatile plic_source * claim_addr = (volatile plic_source * ) + (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + + return *claim_addr; + +} + +void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; + +} + diff --git a/dhrystone/bsp/drivers/plic/plic_driver.h b/dhrystone/bsp/drivers/plic/plic_driver.h new file mode 100644 index 0000000..e7d609b --- /dev/null +++ b/dhrystone/bsp/drivers/plic/plic_driver.h @@ -0,0 +1,51 @@ +// See LICENSE file for licence details + +#ifndef PLIC_DRIVER_H +#define PLIC_DRIVER_H + + +__BEGIN_DECLS + +#include "platform.h" + +typedef struct __plic_instance_t +{ + uintptr_t base_addr; + + uint32_t num_sources; + uint32_t num_priorities; + +} plic_instance_t; + +typedef uint32_t plic_source; +typedef uint32_t plic_priority; +typedef uint32_t plic_threshold; + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ); + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold); + +void PLIC_enable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_disable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_set_priority (plic_instance_t * this_plic, + plic_source source, + plic_priority priority); + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic); + +void PLIC_complete_interrupt(plic_instance_t * this_plic, + plic_source source); + +__END_DECLS + +#endif diff --git a/dhrystone/bsp/env/common.mk b/dhrystone/bsp/env/common.mk new file mode 100644 index 0000000..3f9ee0f --- /dev/null +++ b/dhrystone/bsp/env/common.mk @@ -0,0 +1,60 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_COMMON +_SIFIVE_MK_COMMON := # defined + +.PHONY: all +all: $(TARGET) + +include $(BSP_BASE)/libwrap/libwrap.mk + +BOARD ?= freedom-e300-hifive1 +ENV_DIR = $(BSP_BASE)/env +PLATFORM_DIR = $(ENV_DIR)/$(BOARD) + +#TARGET_FLAVOR := -march=rv32imac -mabi=ilp32 -mcmodel=medany -msmall-data-limit=8 -x assembler-with-cpp +TARGET_FLAVOR := -march=rv32imac -mabi=ilp32 + +ASM_SRCS += $(ENV_DIR)/start.S +ASM_SRCS += $(ENV_DIR)/entry.S +C_SRCS += $(PLATFORM_DIR)/init.c + +LINKER_SCRIPT := $(PLATFORM_DIR)/link.lds + +INCLUDES += -I$(BSP_BASE)/include +INCLUDES += -I$(BSP_BASE)/drivers/ +INCLUDES += -I$(ENV_DIR) +INCLUDES += -I$(PLATFORM_DIR) + +TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin + +CC := $(TOOL_DIR)/riscv64-unknown-elf-gcc ${TARGET_FLAVOR} +AR := $(TOOL_DIR)/riscv64-unknown-elf-ar + +LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles +LDFLAGS += -L$(ENV_DIR) + +ASM_OBJS := $(ASM_SRCS:.S=.o) +C_OBJS := $(C_SRCS:.c=.o) + +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) +LINK_DEPS += $(LINKER_SCRIPT) + +CLEAN_OBJS += $(TARGET) $(LINK_OBJS) + +CFLAGS += -g + +$(TARGET): $(LINK_OBJS) $(LINK_DEPS) + $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) + +$(ASM_OBJS): %.o: %.S $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(C_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + +.PHONY: clean +clean: + rm -f $(CLEAN_OBJS) + +endif # _SIFIVE_MK_COMMON diff --git a/dhrystone/bsp/env/encoding.h b/dhrystone/bsp/env/encoding.h new file mode 100644 index 0000000..35e0f9f --- /dev/null +++ b/dhrystone/bsp/env/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/dhrystone/bsp/env/entry.S b/dhrystone/bsp/env/entry.S new file mode 100644 index 0000000..1f5de24 --- /dev/null +++ b/dhrystone/bsp/env/entry.S @@ -0,0 +1,97 @@ +// See LICENSE for license details + +#ifndef ENTRY_S +#define ENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x2, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + csrw mepc, a0 + + # Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x1, 1*REGBYTES(sp) + LOAD x2, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + mret + +.weak handle_trap +handle_trap: +1: + j 1b + +#endif diff --git a/dhrystone/bsp/env/freedom-e300-arty/init.c b/dhrystone/bsp/env/freedom-e300-arty/init.c new file mode 100644 index 0000000..a6f4b39 --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-arty/init.c @@ -0,0 +1,87 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long get_cpu_freq() +{ + return 65000000; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + #endif +} + +void _fini() +{ +} diff --git a/dhrystone/bsp/env/freedom-e300-arty/link.lds b/dhrystone/bsp/env/freedom-e300-arty/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-arty/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/dhrystone/bsp/env/freedom-e300-arty/openocd.cfg b/dhrystone/bsp/env/freedom-e300-arty/openocd.cfg new file mode 100644 index 0000000..f4b28ed --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/dhrystone/bsp/env/freedom-e300-arty/platform.h b/dhrystone/bsp/env/freedom-e300-arty/platform.h new file mode 100644 index 0000000..d5d6dda --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-arty/platform.h @@ -0,0 +1,125 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF Mappings +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt Numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS +#include "hifive1.h" + +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/dhrystone/bsp/env/freedom-e300-hifive1/init.c b/dhrystone/bsp/env/freedom-e300-hifive1/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-hifive1/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/dhrystone/bsp/env/freedom-e300-hifive1/link.lds b/dhrystone/bsp/env/freedom-e300-hifive1/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-hifive1/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/dhrystone/bsp/env/freedom-e300-hifive1/openocd.cfg b/dhrystone/bsp/env/freedom-e300-hifive1/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/dhrystone/bsp/env/freedom-e300-hifive1/platform.h b/dhrystone/bsp/env/freedom-e300-hifive1/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/dhrystone/bsp/env/freedom-e300-hifive1/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/dhrystone/bsp/env/hifive1.h b/dhrystone/bsp/env/hifive1.h new file mode 100644 index 0000000..4c65f18 --- /dev/null +++ b/dhrystone/bsp/env/hifive1.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_HIFIVE1_H +#define _SIFIVE_HIFIVE1_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. +// These are also mapped to RGB LEDs on the Freedom E300 Arty +// FPGA +// Dev Kit. + +#define RED_LED_OFFSET 22 +#define GREEN_LED_OFFSET 19 +#define BLUE_LED_OFFSET 21 + +// These are the GPIO bit offsets for the differen digital pins +// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. +#define PIN_0_OFFSET 16 +#define PIN_1_OFFSET 17 +#define PIN_2_OFFSET 18 +#define PIN_3_OFFSET 19 +#define PIN_4_OFFSET 20 +#define PIN_5_OFFSET 21 +#define PIN_6_OFFSET 22 +#define PIN_7_OFFSET 23 +#define PIN_8_OFFSET 0 +#define PIN_9_OFFSET 1 +#define PIN_10_OFFSET 2 +#define PIN_11_OFFSET 3 +#define PIN_12_OFFSET 4 +#define PIN_13_OFFSET 5 +//#define PIN_14_OFFSET 8 //This pin is not connected on either board. +#define PIN_15_OFFSET 9 +#define PIN_16_OFFSET 10 +#define PIN_17_OFFSET 11 +#define PIN_18_OFFSET 12 +#define PIN_19_OFFSET 13 + +// These are *PIN* numbers, not +// GPIO Offset Numbers. +#define PIN_SPI1_SCK (13u) +#define PIN_SPI1_MISO (12u) +#define PIN_SPI1_MOSI (11u) +#define PIN_SPI1_SS0 (10u) +#define PIN_SPI1_SS1 (14u) +#define PIN_SPI1_SS2 (15u) +#define PIN_SPI1_SS3 (16u) + +#define SS_PIN_TO_CS_ID(x) \ + ((x==PIN_SPI1_SS0 ? 0 : \ + (x==PIN_SPI1_SS1 ? 1 : \ + (x==PIN_SPI1_SS2 ? 2 : \ + (x==PIN_SPI1_SS3 ? 3 : \ + -1))))) + + +// These buttons are present only on the Freedom E300 Arty Dev Kit. +#ifdef HAS_BOARD_BUTTONS +#define BUTTON_0_OFFSET 15 +#define BUTTON_1_OFFSET 30 +#define BUTTON_2_OFFSET 31 + +#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) + +#endif + +#define HAS_HFXOSC 1 +#define HAS_LFROSC_BYPASS 1 + +#define RTC_FREQ 32768 + +void write_hex(int fd, uint32_t hex); + +#endif /* _SIFIVE_HIFIVE1_H */ diff --git a/dhrystone/bsp/env/iss/init.c b/dhrystone/bsp/env/iss/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/dhrystone/bsp/env/iss/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/dhrystone/bsp/env/iss/link.lds b/dhrystone/bsp/env/iss/link.lds new file mode 100644 index 0000000..bc60026 --- /dev/null +++ b/dhrystone/bsp/env/iss/link.lds @@ -0,0 +1,168 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /*flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M*/ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/dhrystone/bsp/env/iss/openocd.cfg b/dhrystone/bsp/env/iss/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/dhrystone/bsp/env/iss/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/dhrystone/bsp/env/iss/platform.h b/dhrystone/bsp/env/iss/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/dhrystone/bsp/env/iss/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/dhrystone/bsp/env/start.S b/dhrystone/bsp/env/start.S new file mode 100644 index 0000000..b526411 --- /dev/null +++ b/dhrystone/bsp/env/start.S @@ -0,0 +1,54 @@ +// See LICENSE for license details. + + .section .init + .globl _start + .type _start,@function + +_start: + la gp, _gp + la sp, _sp + + /* Load data section */ + la a0, _data_lma + la a1, _data + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start + la a1, _end + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + + /* Call global constructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + +#ifndef __riscv_float_abi_soft + /* Enable FPU */ + li t0, MSTATUS_FS + csrs mstatus, t0 + csrr t1, mstatus + and t1, t1, t0 + beqz t1, 1f + fssr x0 +1: +#endif + + /* argc = argv = 0 */ + li a0, 0 + li a1, 0 + call main + tail exit diff --git a/dhrystone/bsp/include/sifive/bits.h b/dhrystone/bsp/include/sifive/bits.h new file mode 100644 index 0000000..e550f80 --- /dev/null +++ b/dhrystone/bsp/include/sifive/bits.h @@ -0,0 +1,35 @@ +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#ifdef __riscv64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/dhrystone/bsp/include/sifive/const.h b/dhrystone/bsp/include/sifive/const.h new file mode 100644 index 0000000..3e0a681 --- /dev/null +++ b/dhrystone/bsp/include/sifive/const.h @@ -0,0 +1,17 @@ +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/dhrystone/bsp/include/sifive/devices/aon.h b/dhrystone/bsp/include/sifive/devices/aon.h new file mode 100644 index 0000000..63f1db3 --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_AON_H +#define _SIFIVE_AON_H + +/* Register offsets */ + +#define AON_WDOGCFG 0x000 +#define AON_WDOGCOUNT 0x008 +#define AON_WDOGS 0x010 +#define AON_WDOGFEED 0x018 +#define AON_WDOGKEY 0x01C +#define AON_WDOGCMP 0x020 + +#define AON_RTCCFG 0x040 +#define AON_RTCLO 0x048 +#define AON_RTCHI 0x04C +#define AON_RTCS 0x050 +#define AON_RTCCMP 0x060 + +#define AON_BACKUP0 0x080 +#define AON_BACKUP1 0x084 +#define AON_BACKUP2 0x088 +#define AON_BACKUP3 0x08C +#define AON_BACKUP4 0x090 +#define AON_BACKUP5 0x094 +#define AON_BACKUP6 0x098 +#define AON_BACKUP7 0x09C +#define AON_BACKUP8 0x0A0 +#define AON_BACKUP9 0x0A4 +#define AON_BACKUP10 0x0A8 +#define AON_BACKUP11 0x0AC +#define AON_BACKUP12 0x0B0 +#define AON_BACKUP13 0x0B4 +#define AON_BACKUP14 0x0B8 +#define AON_BACKUP15 0x0BC + +#define AON_PMUWAKEUPI0 0x100 +#define AON_PMUWAKEUPI1 0x104 +#define AON_PMUWAKEUPI2 0x108 +#define AON_PMUWAKEUPI3 0x10C +#define AON_PMUWAKEUPI4 0x110 +#define AON_PMUWAKEUPI5 0x114 +#define AON_PMUWAKEUPI6 0x118 +#define AON_PMUWAKEUPI7 0x11C +#define AON_PMUSLEEPI0 0x120 +#define AON_PMUSLEEPI1 0x124 +#define AON_PMUSLEEPI2 0x128 +#define AON_PMUSLEEPI3 0x12C +#define AON_PMUSLEEPI4 0x130 +#define AON_PMUSLEEPI5 0x134 +#define AON_PMUSLEEPI6 0x138 +#define AON_PMUSLEEPI7 0x13C +#define AON_PMUIE 0x140 +#define AON_PMUCAUSE 0x144 +#define AON_PMUSLEEP 0x148 +#define AON_PMUKEY 0x14C + +#define AON_LFROSC 0x070 +/* Constants */ + +#define AON_WDOGKEY_VALUE 0x51F15E +#define AON_WDOGFEED_VALUE 0xD09F00D + +#define AON_WDOGCFG_SCALE 0x0000000F +#define AON_WDOGCFG_RSTEN 0x00000100 +#define AON_WDOGCFG_ZEROCMP 0x00000200 +#define AON_WDOGCFG_ENALWAYS 0x00001000 +#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 +#define AON_WDOGCFG_CMPIP 0x10000000 + +#define AON_RTCCFG_SCALE 0x0000000F +#define AON_RTCCFG_ENALWAYS 0x00001000 +#define AON_RTCCFG_CMPIP 0x10000000 + +#define AON_WAKEUPCAUSE_RESET 0x00 +#define AON_WAKEUPCAUSE_RTC 0x01 +#define AON_WAKEUPCAUSE_DWAKEUP 0x02 +#define AON_WAKEUPCAUSE_AWAKEUP 0x03 + +#define AON_RESETCAUSE_POWERON 0x0000 +#define AON_RESETCAUSE_EXTERNAL 0x0100 +#define AON_RESETCAUSE_WATCHDOG 0x0200 + +#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF +#define AON_PMUCAUSE_RESETCAUSE 0xFF00 + +#endif /* _SIFIVE_AON_H */ diff --git a/dhrystone/bsp/include/sifive/devices/clint.h b/dhrystone/bsp/include/sifive/devices/clint.h new file mode 100644 index 0000000..cd3e0c7 --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/dhrystone/bsp/include/sifive/devices/gpio.h b/dhrystone/bsp/include/sifive/devices/gpio.h new file mode 100644 index 0000000..f7f0acb --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/dhrystone/bsp/include/sifive/devices/otp.h b/dhrystone/bsp/include/sifive/devices/otp.h new file mode 100644 index 0000000..93833e2 --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_OTP_H +#define _SIFIVE_OTP_H + +/* Register offsets */ + +#define OTP_LOCK 0x00 +#define OTP_CK 0x04 +#define OTP_OE 0x08 +#define OTP_SEL 0x0C +#define OTP_WE 0x10 +#define OTP_MR 0x14 +#define OTP_MRR 0x18 +#define OTP_MPP 0x1C +#define OTP_VRREN 0x20 +#define OTP_VPPEN 0x24 +#define OTP_A 0x28 +#define OTP_D 0x2C +#define OTP_Q 0x30 +#define OTP_READ_TIMINGS 0x34 + +#endif diff --git a/dhrystone/bsp/include/sifive/devices/plic.h b/dhrystone/bsp/include/sifive/devices/plic.h new file mode 100644 index 0000000..e1ca5d6 --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/dhrystone/bsp/include/sifive/devices/prci.h b/dhrystone/bsp/include/sifive/devices/prci.h new file mode 100644 index 0000000..1a3de58 --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PRCI_H +#define _SIFIVE_PRCI_H + +/* Register offsets */ + +#define PRCI_HFROSCCFG (0x0000) +#define PRCI_HFXOSCCFG (0x0004) +#define PRCI_PLLCFG (0x0008) +#define PRCI_PLLDIV (0x000C) +#define PRCI_PROCMONCFG (0x00F0) + +/* Fields */ +#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) +#define ROSC_TRIM(x) (((x) & 0x1F) << 16) +#define ROSC_EN(x) (((x) & 0x1 ) << 30) +#define ROSC_RDY(x) (((x) & 0x1 ) << 31) + +#define XOSC_EN(x) (((x) & 0x1) << 30) +#define XOSC_RDY(x) (((x) & 0x1) << 31) + +#define PLL_R(x) (((x) & 0x7) << 0) +// single reserved bit for F LSB. +#define PLL_F(x) (((x) & 0x3F) << 4) +#define PLL_Q(x) (((x) & 0x3) << 10) +#define PLL_SEL(x) (((x) & 0x1) << 16) +#define PLL_REFSEL(x) (((x) & 0x1) << 17) +#define PLL_BYPASS(x) (((x) & 0x1) << 18) +#define PLL_LOCK(x) (((x) & 0x1) << 31) + +#define PLL_R_default 0x1 +#define PLL_F_default 0x1F +#define PLL_Q_default 0x3 + +#define PLL_REFSEL_HFROSC 0x0 +#define PLL_REFSEL_HFXOSC 0x1 + +#define PLL_SEL_HFROSC 0x0 +#define PLL_SEL_PLL 0x1 + +#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) +#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) + +#define PROCMON_DIV(x) (((x) & 0x1F) << 0) +#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) +#define PROCMON_EN(x) (((x) & 0x1) << 16) +#define PROCMON_SEL(x) (((x) & 0x3) << 24) +#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) + +#define PROCMON_SEL_HFCLK 0 +#define PROCMON_SEL_HFXOSCIN 1 +#define PROCMON_SEL_PLLOUTDIV 2 +#define PROCMON_SEL_PROCMON 3 + +#endif // _SIFIVE_PRCI_H diff --git a/dhrystone/bsp/include/sifive/devices/pwm.h b/dhrystone/bsp/include/sifive/devices/pwm.h new file mode 100644 index 0000000..067889a --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PWM_H +#define _SIFIVE_PWM_H + +/* Register offsets */ + +#define PWM_CFG 0x00 +#define PWM_COUNT 0x08 +#define PWM_S 0x10 +#define PWM_CMP0 0x20 +#define PWM_CMP1 0x24 +#define PWM_CMP2 0x28 +#define PWM_CMP3 0x2C + +/* Constants */ + +#define PWM_CFG_SCALE 0x0000000F +#define PWM_CFG_STICKY 0x00000100 +#define PWM_CFG_ZEROCMP 0x00000200 +#define PWM_CFG_DEGLITCH 0x00000400 +#define PWM_CFG_ENALWAYS 0x00001000 +#define PWM_CFG_ONESHOT 0x00002000 +#define PWM_CFG_CMP0CENTER 0x00010000 +#define PWM_CFG_CMP1CENTER 0x00020000 +#define PWM_CFG_CMP2CENTER 0x00040000 +#define PWM_CFG_CMP3CENTER 0x00080000 +#define PWM_CFG_CMP0GANG 0x01000000 +#define PWM_CFG_CMP1GANG 0x02000000 +#define PWM_CFG_CMP2GANG 0x04000000 +#define PWM_CFG_CMP3GANG 0x08000000 +#define PWM_CFG_CMP0IP 0x10000000 +#define PWM_CFG_CMP1IP 0x20000000 +#define PWM_CFG_CMP2IP 0x40000000 +#define PWM_CFG_CMP3IP 0x80000000 + +#endif /* _SIFIVE_PWM_H */ diff --git a/dhrystone/bsp/include/sifive/devices/spi.h b/dhrystone/bsp/include/sifive/devices/spi.h new file mode 100644 index 0000000..916d86b --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + + +#endif /* _SIFIVE_SPI_H */ diff --git a/dhrystone/bsp/include/sifive/devices/uart.h b/dhrystone/bsp/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/dhrystone/bsp/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/dhrystone/bsp/include/sifive/sections.h b/dhrystone/bsp/include/sifive/sections.h new file mode 100644 index 0000000..848c237 --- /dev/null +++ b/dhrystone/bsp/include/sifive/sections.h @@ -0,0 +1,16 @@ +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/dhrystone/bsp/libwrap/libwrap.mk b/dhrystone/bsp/libwrap/libwrap.mk new file mode 100644 index 0000000..313ed00 --- /dev/null +++ b/dhrystone/bsp/libwrap/libwrap.mk @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_LIBWRAP +_SIFIVE_MK_LIBWRAP := # defined + +LIBWRAP_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +LIBWRAP_DIR := $(LIBWRAP_DIR:/=) + +LIBWRAP_SRCS := \ + stdlib/malloc.c \ + sys/open.c \ + sys/lseek.c \ + sys/read.c \ + sys/write.c \ + sys/fstat.c \ + sys/stat.c \ + sys/close.c \ + sys/link.c \ + sys/unlink.c \ + sys/execve.c \ + sys/fork.c \ + sys/getpid.c \ + sys/kill.c \ + sys/wait.c \ + sys/isatty.c \ + sys/times.c \ + sys/sbrk.c \ + sys/_exit.c \ + misc/write_hex.c + +LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f)) +LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o) + +LIBWRAP_SYMS := malloc free \ + open lseek read write fstat stat close link unlink \ + execve fork getpid kill wait \ + isatty times sbrk _exit + +LIBWRAP := libwrap.a + +LINK_DEPS += $(LIBWRAP) + +LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s)) +LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group + +CLEAN_OBJS += $(LIBWRAP_OBJS) + +$(LIBWRAP_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(LIBWRAP): $(LIBWRAP_OBJS) + $(AR) rcs $@ $^ + +endif # _SIFIVE_MK_LIBWRAP diff --git a/dhrystone/bsp/libwrap/misc/write_hex.c b/dhrystone/bsp/libwrap/misc/write_hex.c new file mode 100644 index 0000000..e678bdc --- /dev/null +++ b/dhrystone/bsp/libwrap/misc/write_hex.c @@ -0,0 +1,19 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "platform.h" + +void write_hex(int fd, uint32_t hex) +{ + uint8_t ii; + uint8_t jj; + char towrite; + write(fd , "0x", 2); + for (ii = 8 ; ii > 0; ii--) { + jj = ii - 1; + uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4)); + towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA)); + write(fd, &towrite, 1); + } +} diff --git a/dhrystone/bsp/libwrap/stdlib/malloc.c b/dhrystone/bsp/libwrap/stdlib/malloc.c new file mode 100644 index 0000000..8f4f432 --- /dev/null +++ b/dhrystone/bsp/libwrap/stdlib/malloc.c @@ -0,0 +1,17 @@ +/* See LICENSE for license details. */ + +/* These functions are intended for embedded RV32 systems and are + obviously incorrect in general. */ + +void* __wrap_malloc(unsigned long sz) +{ + extern void* sbrk(long); + void* res = sbrk(sz); + if ((long)res == -1) + return 0; + return res; +} + +void __wrap_free(void* ptr) +{ +} diff --git a/dhrystone/bsp/libwrap/sys/_exit.c b/dhrystone/bsp/libwrap/sys/_exit.c new file mode 100644 index 0000000..7261891 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/_exit.c @@ -0,0 +1,17 @@ +/* See LICENSE of license details. */ + +#include +#include "platform.h" + +void __wrap__exit(int code) +{ +//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); + const char message[] = "\nProgam has exited with code:"; +//*leds = (~(code)); + + write(STDERR_FILENO, message, sizeof(message) - 1); + write_hex(STDERR_FILENO, code); + write(STDERR_FILENO, "\n", 1); + + for (;;); +} diff --git a/dhrystone/bsp/libwrap/sys/close.c b/dhrystone/bsp/libwrap/sys/close.c new file mode 100644 index 0000000..e4f8e14 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/close.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_close(int fd) +{ + return _stub(EBADF); +} diff --git a/dhrystone/bsp/libwrap/sys/execve.c b/dhrystone/bsp/libwrap/sys/execve.c new file mode 100644 index 0000000..6178a01 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/execve.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_execve(const char* name, char* const argv[], char* const env[]) +{ + return _stub(ENOMEM); +} diff --git a/dhrystone/bsp/libwrap/sys/fork.c b/dhrystone/bsp/libwrap/sys/fork.c new file mode 100644 index 0000000..13a3e65 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/fork.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int fork(void) +{ + return _stub(EAGAIN); +} diff --git a/dhrystone/bsp/libwrap/sys/fstat.c b/dhrystone/bsp/libwrap/sys/fstat.c new file mode 100644 index 0000000..6ea3e6a --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/fstat.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +int __wrap_fstat(int fd, struct stat* st) +{ + if (isatty(fd)) { + st->st_mode = S_IFCHR; + return 0; + } + + return _stub(EBADF); +} diff --git a/dhrystone/bsp/libwrap/sys/getpid.c b/dhrystone/bsp/libwrap/sys/getpid.c new file mode 100644 index 0000000..5aa510b --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/getpid.c @@ -0,0 +1,6 @@ +/* See LICENSE of license details. */ + +int __wrap_getpid(void) +{ + return 1; +} diff --git a/dhrystone/bsp/libwrap/sys/isatty.c b/dhrystone/bsp/libwrap/sys/isatty.c new file mode 100644 index 0000000..55eab0a --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/isatty.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */ + +#include + +int __wrap_isatty(int fd) +{ + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + return 1; + + return 0; +} diff --git a/dhrystone/bsp/libwrap/sys/kill.c b/dhrystone/bsp/libwrap/sys/kill.c new file mode 100644 index 0000000..9c56632 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/kill.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_kill(int pid, int sig) +{ + return _stub(EINVAL); +} diff --git a/dhrystone/bsp/libwrap/sys/link.c b/dhrystone/bsp/libwrap/sys/link.c new file mode 100644 index 0000000..9340cad --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/link.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_link(const char *old_name, const char *new_name) +{ + return _stub(EMLINK); +} diff --git a/dhrystone/bsp/libwrap/sys/lseek.c b/dhrystone/bsp/libwrap/sys/lseek.c new file mode 100644 index 0000000..46f58fa --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/lseek.c @@ -0,0 +1,14 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +off_t __wrap_lseek(int fd, off_t ptr, int dir) +{ + if (isatty(fd)) + return 0; + + return _stub(EBADF); +} diff --git a/dhrystone/bsp/libwrap/sys/open.c b/dhrystone/bsp/libwrap/sys/open.c new file mode 100644 index 0000000..d1871f9 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/open.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_open(const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/dhrystone/bsp/libwrap/sys/openat.c b/dhrystone/bsp/libwrap/sys/openat.c new file mode 100644 index 0000000..7f1c945 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/openat.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_openat(int dirfd, const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/dhrystone/bsp/libwrap/sys/read.c b/dhrystone/bsp/libwrap/sys/read.c new file mode 100644 index 0000000..4e57f08 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/read.c @@ -0,0 +1,30 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_read(int fd, void* ptr, size_t len) +{ + uint8_t * current = (uint8_t *)ptr; + volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + + ssize_t result = 0; + + if (isatty(fd)) { + for (current = (uint8_t *)ptr; + (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); + current ++) { + *current = *uart_rx; + result++; + } + return result; + } + + return _stub(EBADF); +} diff --git a/dhrystone/bsp/libwrap/sys/sbrk.c b/dhrystone/bsp/libwrap/sys/sbrk.c new file mode 100644 index 0000000..6e6b36a --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/sbrk.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include + +void *__wrap_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} diff --git a/dhrystone/bsp/libwrap/sys/stat.c b/dhrystone/bsp/libwrap/sys/stat.c new file mode 100644 index 0000000..1ccc2f4 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/stat.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +int __wrap_stat(const char* file, struct stat* st) +{ + return _stub(EACCES); +} diff --git a/dhrystone/bsp/libwrap/sys/stub.h b/dhrystone/bsp/libwrap/sys/stub.h new file mode 100644 index 0000000..fb5e5be --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/stub.h @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ +#ifndef _SIFIVE_SYS_STUB_H +#define _SIFIVE_SYS_STUB_H + +static inline int _stub(int err) +{ + return -1; +} + +#endif /* _SIFIVE_SYS_STUB_H */ diff --git a/dhrystone/bsp/libwrap/sys/times.c b/dhrystone/bsp/libwrap/sys/times.c new file mode 100644 index 0000000..26a9566 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/times.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +clock_t __wrap_times(struct tms* buf) +{ + return _stub(EACCES); +} diff --git a/dhrystone/bsp/libwrap/sys/unlink.c b/dhrystone/bsp/libwrap/sys/unlink.c new file mode 100644 index 0000000..b62b1ba --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/unlink.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_unlink(const char* name) +{ + return _stub(ENOENT); +} diff --git a/dhrystone/bsp/libwrap/sys/wait.c b/dhrystone/bsp/libwrap/sys/wait.c new file mode 100644 index 0000000..ea3225b --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/wait.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int wait(int* status) +{ + return _stub(ECHILD); +} diff --git a/dhrystone/bsp/libwrap/sys/write.c b/dhrystone/bsp/libwrap/sys/write.c new file mode 100644 index 0000000..d00eb17 --- /dev/null +++ b/dhrystone/bsp/libwrap/sys/write.c @@ -0,0 +1,29 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_write(int fd, const void* ptr, size_t len) +{ + const uint8_t * current = (const char *)ptr; + + if (isatty(fd)) { + for (size_t jj = 0; jj < len; jj++) { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = current[jj]; + + if (current[jj] == '\n') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = '\r'; + } + } + return len; + } + + return _stub(EBADF); +} diff --git a/dhrystone/dhry.h b/dhrystone/dhry.h new file mode 100644 index 0000000..b556ecc --- /dev/null +++ b/dhrystone/dhry.h @@ -0,0 +1,423 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens AG, AUT E 51 + * Postfach 3220 + * 8520 Erlangen + * Germany (West) + * Phone: [+49]-9131-7-20330 + * (8-17 Central European Time) + * Usenet: ..!mcsun!unido!estevax!weicker + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * In addition, Berkeley UNIX system calls "times ()" or "time ()" + * are used for execution time measurement. For measurements + * on other systems, these calls have to be changed. + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 389-8963 (9-17 EST) + * Usenet: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software used. + * Hardware information includes: Machine type, CPU, type and size + * of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). + * Software information includes: Compiler (and runtime library) + * manufacturer and version, compilation switches, OS version. + * The Operating System version may give an indication about the + * compiler; Dhrystone itself performs no OS calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + *************************************************************************** + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used most. + * There should be, as far as possible, only one C version of + * Dhrystone such that results can be compared without + * restrictions. In the past, the C versions distributed + * by Rick Richardson (Version 1.1) and by Reinhold Weicker + * had small (though not significant) differences. + * + * 2) As far as it is possible without changes to the Dhrystone + * statistics, optimizing compilers should be prevented from + * removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold Weicker. + * As a concession to older compilers, names have been made + * unique within the first 8 characters. + * Inside the measurement loop, this version follows the + * version previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing compilers + * should be prevented from moving code out of the measurement + * loop, or from removing code altogether. Since the statements + * that are executed within the measurement loop have NOT been + * changed, the numbers defining the "Dhrystone distribution" + * (distribution of statements, operand types and locality) + * still hold. Except for sophisticated optimizing compilers, + * execution times for this version should be the same as + * for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic benchmarks. + * Users of the benchmark are advised to check code listings + * whether code is generated for all statements of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it corrects + * some minor deficiencies that were found by users of version 2.0. + * The only change within the measurement loop is that a + * non-executed "else" part was added to the "if" statement in + * Func_3, and a non-executed "else" part removed from Proc_3. + * + *************************************************************************** + * + * Defines: The following "Defines" are possible: + * -DREG=register (default: Not defined) + * As an approximation to what an average C programmer + * might do, the "register" storage class is applied + * (if enabled by -DREG=register) + * - for local variables, if they are used (dynamically) + * five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" declarations + * do not necessarily lead to faster execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * -DTIMES (default) + * -DTIME + * The "times" function of UNIX (returning process times) + * or the "time" function (returning wallclock time) + * is used for measurement. + * For single user machines, "time ()" is adequate. For + * multi-user machines where you cannot get single-user + * access, use the "times ()" function. If you have + * neither, use a stopwatch in the dead of night. + * "printf"s are provided marking the points "Start Timer" + * and "Stop Timer". DO NOT use the UNIX "time(1)" + * command, as this will measure the total time to + * run this program, which will (erroneously) include + * the time to allocate storage (malloc) and to perform + * the initialization. + * -DHZ=nnn + * In Berkeley UNIX, the function "times" returns process + * time in 1/HZ seconds, with HZ = 60 for most systems. + * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY + * A VALUE. + * + *************************************************************************** + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system used. + * + ************************************************************************** + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values as implicit parameters). + * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a record + * component), only the final data type on the access path is counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is syntactically + * and semantically correct. All variables have a value assigned to them + * before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code or + * data. + * + *************************************************************************** + */ + +/* Compiler and system dependent definitions: */ + +#ifndef TIME +#define TIMES +#endif + /* Use times(2) time function unless */ + /* explicitly defined otherwise */ + +#ifdef TIMES +#include +#include + /* for "times" */ +#endif + +#define Mic_secs_Per_Second 1000000 + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + + diff --git a/dhrystone/dhry_1.c b/dhrystone/dhry_1.c new file mode 100644 index 0000000..66571fb --- /dev/null +++ b/dhrystone/dhry_1.c @@ -0,0 +1,385 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_1.c (part 2 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +/* Global Variables: */ + +Rec_Pointer Ptr_Glob, + Next_Ptr_Glob; +int Int_Glob; +Boolean Bool_Glob; +char Ch_1_Glob, + Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +extern void *malloc (); +Enumeration Func_1 (); + /* forward declaration necessary since Enumeration may not simply be int */ + +#ifndef REG + Boolean Reg = false; +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else + Boolean Reg = true; +#endif + +/* variables for time measurement: */ + +#ifdef TIMES +struct tms time_info; +extern int times (); + /* see library function "times" */ +#define Too_Small_Time 120 + /* Measurements should last at least about 2 seconds */ +#endif +#ifdef TIME +extern long time(); + /* see library function "time" */ +#define Too_Small_Time 2 + /* Measurements should last at least 2 seconds */ +#endif + +long Begin_Time, + End_Time, + User_Time; +float Microseconds, + Dhrystones_Per_Second; + +/* end of variables for time measurement */ + + +main () +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + REG int Number_Of_Runs; + + /* Initializations */ + + Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + strcpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING"); + strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + + printf ("\n"); + printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf ("\n"); + if (Reg) + { + printf ("Program compiled with 'register' attribute\n"); + printf ("\n"); + } + else + { + printf ("Program compiled without 'register' attribute\n"); + printf ("\n"); + } + printf ("Please give the number of runs through the benchmark: "); + { + int n; + scanf ("%d", &n); + Number_Of_Runs = n; + } + printf ("\n"); + + printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + +#ifdef TIMES + times (&time_info); + Begin_Time = (long) time_info.tms_utime; +#endif +#ifdef TIME + Begin_Time = time ( (long *) 0); +#endif + + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + +#ifdef TIMES + times (&time_info); + End_Time = (long) time_info.tms_utime; +#endif +#ifdef TIME + End_Time = time ( (long *) 0); +#endif + + printf ("Execution ends\n"); + printf ("\n"); + printf ("Final values of the variables used in the benchmark:\n"); + printf ("\n"); + printf ("Int_Glob: %d\n", Int_Glob); + printf (" should be: %d\n", 5); + printf ("Bool_Glob: %d\n", Bool_Glob); + printf (" should be: %d\n", 1); + printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + printf (" should be: %c\n", 'A'); + printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + printf (" should be: %c\n", 'B'); + printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + printf (" should be: %d\n", 7); + printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + printf (" should be: Number_Of_Runs + 10\n"); + printf ("Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent)\n"); + printf (" Discr: %d\n", Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 2); + printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 17); + printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Next_Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent), same as above\n"); + printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 1); + printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 18); + printf (" Str_Comp: %s\n", + Next_Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Int_1_Loc: %d\n", Int_1_Loc); + printf (" should be: %d\n", 5); + printf ("Int_2_Loc: %d\n", Int_2_Loc); + printf (" should be: %d\n", 13); + printf ("Int_3_Loc: %d\n", Int_3_Loc); + printf (" should be: %d\n", 7); + printf ("Enum_Loc: %d\n", Enum_Loc); + printf (" should be: %d\n", 1); + printf ("Str_1_Loc: %s\n", Str_1_Loc); + printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + printf ("Str_2_Loc: %s\n", Str_2_Loc); + printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + printf ("\n"); + + User_Time = End_Time - Begin_Time; + + if (User_Time < Too_Small_Time) + { + printf ("Measured time too small to obtain meaningful results\n"); + printf ("Please increase number of runs\n"); + printf ("\n"); + } + else + { +#ifdef TIME + Microseconds = (float) User_Time * Mic_secs_Per_Second + / (float) Number_Of_Runs; + Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; +#else + Microseconds = (float) User_Time * Mic_secs_Per_Second + / ((float) HZ * ((float) Number_Of_Runs)); + Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) + / (float) User_Time; +#endif + printf ("Microseconds for one run through Dhrystone: "); + printf ("%6.1f \n", Microseconds); + printf ("Dhrystones per Second: "); + printf ("%6.1f \n", Dhrystones_Per_Second); + printf ("\n"); + } + +} + + +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ + + +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + + +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + + +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + + +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif + + diff --git a/dhrystone/dhry_2.c b/dhrystone/dhry_2.c new file mode 100644 index 0000000..63a3d3e --- /dev/null +++ b/dhrystone/dhry_2.c @@ -0,0 +1,192 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_2.c (part 3 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +#ifndef REG +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#endif + +extern int Int_Glob; +extern char Ch_1_Glob; + + +Proc_6 (Enum_Val_Par, Enum_Ref_Par) +/*********************************/ + /* executed once */ + /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ + +Enumeration Enum_Val_Par; +Enumeration *Enum_Ref_Par; +{ + *Enum_Ref_Par = Enum_Val_Par; + if (! Func_3 (Enum_Val_Par)) + /* then, not executed */ + *Enum_Ref_Par = Ident_4; + switch (Enum_Val_Par) + { + case Ident_1: + *Enum_Ref_Par = Ident_1; + break; + case Ident_2: + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + break; + case Ident_3: /* executed */ + *Enum_Ref_Par = Ident_2; + break; + case Ident_4: break; + case Ident_5: + *Enum_Ref_Par = Ident_3; + break; + } /* switch */ +} /* Proc_6 */ + + +Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +/**********************************************/ + /* executed three times */ + /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ + /* Int_Par_Ref becomes 7 */ + /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ + /* Int_Par_Ref becomes 17 */ + /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ + /* Int_Par_Ref becomes 18 */ +One_Fifty Int_1_Par_Val; +One_Fifty Int_2_Par_Val; +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 2; + *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +} /* Proc_7 */ + + +Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +/*********************************************************************/ + /* executed once */ + /* Int_Par_Val_1 == 3 */ + /* Int_Par_Val_2 == 7 */ +Arr_1_Dim Arr_1_Par_Ref; +Arr_2_Dim Arr_2_Par_Ref; +int Int_1_Par_Val; +int Int_2_Par_Val; +{ + REG One_Fifty Int_Index; + REG One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 5; + Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; + Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; + Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; + for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) + Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; + Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; + Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; + Int_Glob = 5; +} /* Proc_8 */ + + +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +/*************************************************/ + /* executed three times */ + /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ + /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ + /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ + +Capital_Letter Ch_1_Par_Val; +Capital_Letter Ch_2_Par_Val; +{ + Capital_Letter Ch_1_Loc; + Capital_Letter Ch_2_Loc; + + Ch_1_Loc = Ch_1_Par_Val; + Ch_2_Loc = Ch_1_Loc; + if (Ch_2_Loc != Ch_2_Par_Val) + /* then, executed */ + return (Ident_1); + else /* not executed */ + { + Ch_1_Glob = Ch_1_Loc; + return (Ident_2); + } +} /* Func_1 */ + + +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +/*************************************************/ + /* executed once */ + /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ + /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ + +Str_30 Str_1_Par_Ref; +Str_30 Str_2_Par_Ref; +{ + REG One_Thirty Int_Loc; + Capital_Letter Ch_Loc; + + Int_Loc = 2; + while (Int_Loc <= 2) /* loop body executed once */ + if (Func_1 (Str_1_Par_Ref[Int_Loc], + Str_2_Par_Ref[Int_Loc+1]) == Ident_1) + /* then, executed */ + { + Ch_Loc = 'A'; + Int_Loc += 1; + } /* if, while */ + if (Ch_Loc >= 'W' && Ch_Loc < 'Z') + /* then, not executed */ + Int_Loc = 7; + if (Ch_Loc == 'R') + /* then, not executed */ + return (true); + else /* executed */ + { + if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) + /* then, not executed */ + { + Int_Loc += 7; + Int_Glob = Int_Loc; + return (true); + } + else /* executed */ + return (false); + } /* if Ch_Loc */ +} /* Func_2 */ + + +Boolean Func_3 (Enum_Par_Val) +/***************************/ + /* executed once */ + /* Enum_Par_Val == Ident_3 */ +Enumeration Enum_Par_Val; +{ + Enumeration Enum_Loc; + + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + return (true); + else /* not executed */ + return (false); +} /* Func_3 */ + diff --git a/dhrystone/dhry_printf.c b/dhrystone/dhry_printf.c new file mode 100644 index 0000000..025d231 --- /dev/null +++ b/dhrystone/dhry_printf.c @@ -0,0 +1,271 @@ +/* The functions in this file are only meant to support Dhrystone on an + * embedded RV32 system and are obviously incorrect in general. */ + +#include +#include +#include +#include +#include +#include + +#undef putchar +int putchar(int ch) +{ + return write(1, &ch, 1) == 1 ? ch : -1; +} + +static void sprintf_putch(int ch, void** data) +{ + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; +} + +static unsigned long getuint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long getint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*8]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static inline void print_double(void (*putch)(int, void**), void **putdat, + double num, int width, int prec) +{ + union { + double d; + uint64_t u; + } u; + u.d = num; + + if (u.u & (1ULL << 63)) { + putch('-', putdat); + u.u &= ~(1ULL << 63); + } + + for (int i = 0; i < prec; i++) + u.d *= 10; + + char buf[32], *pbuf = buf; + printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0); + if (prec > 0) { + for (int i = 0; i < prec; i++) { + pbuf[-i] = pbuf[-i-1]; + } + pbuf[-prec] = '.'; + pbuf++; + } + + for (char* p = buf; p < pbuf; p++) + putch(*p, putdat); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch, err; + unsigned long num; + int base, lflag, width, precision, altflag; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') + return; + fmt++; + putch(ch, putdat); + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + altflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + altflag = 1; + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag + case 'l': + if (lflag) + goto bad; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // double + case 'f': + print_double(putch, putdat, va_arg(ap, double), width, precision); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long) num < 0) { + putch('-', putdat); + num = -(long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + bad: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +int __wrap_printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + vprintfmt((void*)putchar, 0, fmt, ap); + + va_end(ap); + return 0; // incorrect return value, but who cares, anyway? +} + +int __wrap_sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} diff --git a/dhrystone/dhry_stubs.c b/dhrystone/dhry_stubs.c new file mode 100644 index 0000000..9ae1160 --- /dev/null +++ b/dhrystone/dhry_stubs.c @@ -0,0 +1,24 @@ +#include "platform.h" + +/* The functions in this file are only meant to support Dhrystone on an + * embedded RV32 system and are obviously incorrect in general. */ + +long time(void) +{ + return get_timer_value() / get_timer_freq(); +} + +// set the number of dhrystone iterations +void __wrap_scanf(const char* fmt, int* n) +{ +// *n = 100000000; + *n = 1000000; +} + +volatile uint64_t tohost; +volatile uint64_t fromhost; + +void __wrap_exit(int n){ + tohost = 0x1; + for (;;); +} diff --git a/hello/Makefile b/hello/Makefile new file mode 100644 index 0000000..728bd2d --- /dev/null +++ b/hello/Makefile @@ -0,0 +1,13 @@ + +TARGET = hello +C_SRCS += $(wildcard *.c) +CFLAGS += -g +#-fno-builtin-printf +LDFLAGS := -Wl,--wrap=scanf -Wl,--wrap=printf + +#BOARD = iss +BOARD=freedom-e300-hifive1 +TOOL_DIR=/opt/shared/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin + +BSP_BASE = ./bsp +include $(BSP_BASE)/env/common.mk diff --git a/hello/bsp/Debug/drivers/fe300prci/subdir.mk b/hello/bsp/Debug/drivers/fe300prci/subdir.mk new file mode 100644 index 0000000..9a05361 --- /dev/null +++ b/hello/bsp/Debug/drivers/fe300prci/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../drivers/fe300prci/fe300prci_driver.c + +OBJS += \ +./drivers/fe300prci/fe300prci_driver.o + +C_DEPS += \ +./drivers/fe300prci/fe300prci_driver.d + + +# Each subdirectory must supply rules for building sources it contributes +drivers/fe300prci/%.o: ../drivers/fe300prci/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/drivers/plic/subdir.mk b/hello/bsp/Debug/drivers/plic/subdir.mk new file mode 100644 index 0000000..be3a955 --- /dev/null +++ b/hello/bsp/Debug/drivers/plic/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../drivers/plic/plic_driver.c + +OBJS += \ +./drivers/plic/plic_driver.o + +C_DEPS += \ +./drivers/plic/plic_driver.d + + +# Each subdirectory must supply rules for building sources it contributes +drivers/plic/%.o: ../drivers/plic/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/env/freedom-e300-arty/subdir.mk b/hello/bsp/Debug/env/freedom-e300-arty/subdir.mk new file mode 100644 index 0000000..c0bee22 --- /dev/null +++ b/hello/bsp/Debug/env/freedom-e300-arty/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../env/freedom-e300-arty/init.c + +OBJS += \ +./env/freedom-e300-arty/init.o + +C_DEPS += \ +./env/freedom-e300-arty/init.d + + +# Each subdirectory must supply rules for building sources it contributes +env/freedom-e300-arty/%.o: ../env/freedom-e300-arty/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/env/freedom-e300-hifive1/subdir.mk b/hello/bsp/Debug/env/freedom-e300-hifive1/subdir.mk new file mode 100644 index 0000000..16eea64 --- /dev/null +++ b/hello/bsp/Debug/env/freedom-e300-hifive1/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../env/freedom-e300-hifive1/init.c + +O_SRCS += \ +../env/freedom-e300-hifive1/init.o + +OBJS += \ +./env/freedom-e300-hifive1/init.o + +C_DEPS += \ +./env/freedom-e300-hifive1/init.d + + +# Each subdirectory must supply rules for building sources it contributes +env/freedom-e300-hifive1/%.o: ../env/freedom-e300-hifive1/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/env/iss/subdir.mk b/hello/bsp/Debug/env/iss/subdir.mk new file mode 100644 index 0000000..88f2d87 --- /dev/null +++ b/hello/bsp/Debug/env/iss/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../env/iss/init.c + +O_SRCS += \ +../env/iss/init.o + +OBJS += \ +./env/iss/init.o + +C_DEPS += \ +./env/iss/init.d + + +# Each subdirectory must supply rules for building sources it contributes +env/iss/%.o: ../env/iss/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/env/subdir.mk b/hello/bsp/Debug/env/subdir.mk new file mode 100644 index 0000000..b8eaa7a --- /dev/null +++ b/hello/bsp/Debug/env/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +O_SRCS += \ +../env/entry.o \ +../env/start.o + +S_UPPER_SRCS += \ +../env/entry.S \ +../env/start.S + +OBJS += \ +./env/entry.o \ +./env/start.o + + +# Each subdirectory must supply rules for building sources it contributes +env/%.o: ../env/%.S + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Assembler' + riscv32-unknown-elf-as -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/libwrap/misc/subdir.mk b/hello/bsp/Debug/libwrap/misc/subdir.mk new file mode 100644 index 0000000..23a8c0b --- /dev/null +++ b/hello/bsp/Debug/libwrap/misc/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../libwrap/misc/write_hex.c + +O_SRCS += \ +../libwrap/misc/write_hex.o + +OBJS += \ +./libwrap/misc/write_hex.o + +C_DEPS += \ +./libwrap/misc/write_hex.d + + +# Each subdirectory must supply rules for building sources it contributes +libwrap/misc/%.o: ../libwrap/misc/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/libwrap/stdlib/subdir.mk b/hello/bsp/Debug/libwrap/stdlib/subdir.mk new file mode 100644 index 0000000..2327c6d --- /dev/null +++ b/hello/bsp/Debug/libwrap/stdlib/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../libwrap/stdlib/malloc.c + +O_SRCS += \ +../libwrap/stdlib/malloc.o + +OBJS += \ +./libwrap/stdlib/malloc.o + +C_DEPS += \ +./libwrap/stdlib/malloc.d + + +# Each subdirectory must supply rules for building sources it contributes +libwrap/stdlib/%.o: ../libwrap/stdlib/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/libwrap/sys/subdir.mk b/hello/bsp/Debug/libwrap/sys/subdir.mk new file mode 100644 index 0000000..a93df2a --- /dev/null +++ b/hello/bsp/Debug/libwrap/sys/subdir.mk @@ -0,0 +1,98 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../libwrap/sys/_exit.c \ +../libwrap/sys/close.c \ +../libwrap/sys/execve.c \ +../libwrap/sys/fork.c \ +../libwrap/sys/fstat.c \ +../libwrap/sys/getpid.c \ +../libwrap/sys/isatty.c \ +../libwrap/sys/kill.c \ +../libwrap/sys/link.c \ +../libwrap/sys/lseek.c \ +../libwrap/sys/open.c \ +../libwrap/sys/openat.c \ +../libwrap/sys/read.c \ +../libwrap/sys/sbrk.c \ +../libwrap/sys/stat.c \ +../libwrap/sys/times.c \ +../libwrap/sys/unlink.c \ +../libwrap/sys/wait.c \ +../libwrap/sys/write.c + +O_SRCS += \ +../libwrap/sys/_exit.o \ +../libwrap/sys/close.o \ +../libwrap/sys/execve.o \ +../libwrap/sys/fork.o \ +../libwrap/sys/fstat.o \ +../libwrap/sys/getpid.o \ +../libwrap/sys/isatty.o \ +../libwrap/sys/kill.o \ +../libwrap/sys/link.o \ +../libwrap/sys/lseek.o \ +../libwrap/sys/open.o \ +../libwrap/sys/read.o \ +../libwrap/sys/sbrk.o \ +../libwrap/sys/stat.o \ +../libwrap/sys/times.o \ +../libwrap/sys/unlink.o \ +../libwrap/sys/wait.o \ +../libwrap/sys/write.o + +OBJS += \ +./libwrap/sys/_exit.o \ +./libwrap/sys/close.o \ +./libwrap/sys/execve.o \ +./libwrap/sys/fork.o \ +./libwrap/sys/fstat.o \ +./libwrap/sys/getpid.o \ +./libwrap/sys/isatty.o \ +./libwrap/sys/kill.o \ +./libwrap/sys/link.o \ +./libwrap/sys/lseek.o \ +./libwrap/sys/open.o \ +./libwrap/sys/openat.o \ +./libwrap/sys/read.o \ +./libwrap/sys/sbrk.o \ +./libwrap/sys/stat.o \ +./libwrap/sys/times.o \ +./libwrap/sys/unlink.o \ +./libwrap/sys/wait.o \ +./libwrap/sys/write.o + +C_DEPS += \ +./libwrap/sys/_exit.d \ +./libwrap/sys/close.d \ +./libwrap/sys/execve.d \ +./libwrap/sys/fork.d \ +./libwrap/sys/fstat.d \ +./libwrap/sys/getpid.d \ +./libwrap/sys/isatty.d \ +./libwrap/sys/kill.d \ +./libwrap/sys/link.d \ +./libwrap/sys/lseek.d \ +./libwrap/sys/open.d \ +./libwrap/sys/openat.d \ +./libwrap/sys/read.d \ +./libwrap/sys/sbrk.d \ +./libwrap/sys/stat.d \ +./libwrap/sys/times.d \ +./libwrap/sys/unlink.d \ +./libwrap/sys/wait.d \ +./libwrap/sys/write.d + + +# Each subdirectory must supply rules for building sources it contributes +libwrap/sys/%.o: ../libwrap/sys/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/hello/bsp/Debug/makefile b/hello/bsp/Debug/makefile new file mode 100644 index 0000000..34f9759 --- /dev/null +++ b/hello/bsp/Debug/makefile @@ -0,0 +1,66 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include libwrap/sys/subdir.mk +-include libwrap/stdlib/subdir.mk +-include libwrap/misc/subdir.mk +-include env/iss/subdir.mk +-include env/freedom-e300-hifive1/subdir.mk +-include env/freedom-e300-arty/subdir.mk +-include env/subdir.mk +-include drivers/plic/subdir.mk +-include drivers/fe300prci/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: bsp + +# Tool invocations +bsp: $(OBJS) $(USER_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: Cross G++ Linker' + riscv32-unknown-elf-g++ -o "bsp" $(OBJS) $(USER_OBJS) $(LIBS) + @echo 'Finished building target: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(EXECUTABLES)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(C_DEPS)$(CPP_DEPS) bsp + -@echo ' ' + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/hello/bsp/Debug/objects.mk b/hello/bsp/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/hello/bsp/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/hello/bsp/Debug/sources.mk b/hello/bsp/Debug/sources.mk new file mode 100644 index 0000000..bfb7eff --- /dev/null +++ b/hello/bsp/Debug/sources.mk @@ -0,0 +1,35 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +CC_SRCS := +ASM_SRCS := +C_SRCS := +CPP_SRCS := +O_SRCS := +S_UPPER_SRCS := +CC_DEPS := +C++_DEPS := +EXECUTABLES := +OBJS := +C_UPPER_DEPS := +CXX_DEPS := +C_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +drivers/fe300prci \ +drivers/plic \ +env \ +env/freedom-e300-arty \ +env/freedom-e300-hifive1 \ +env/iss \ +libwrap/misc \ +libwrap/stdlib \ +libwrap/sys \ + diff --git a/hello/bsp/drivers/fe300prci/fe300prci_driver.c b/hello/bsp/drivers/fe300prci/fe300prci_driver.c new file mode 100644 index 0000000..2d9c52f --- /dev/null +++ b/hello/bsp/drivers/fe300prci/fe300prci_driver.c @@ -0,0 +1,252 @@ +// See LICENSE file for license details + +#include "platform.h" + +#ifdef PRCI_BASE_ADDR +#include "fe300prci/fe300prci_driver.h" +#include + +#define rdmcycle(x) { \ + uint32_t lo, hi, hi2; \ + __asm__ __volatile__ ("1:\n\t" \ + "csrr %0, mcycleh\n\t" \ + "csrr %1, mcycle\n\t" \ + "csrr %2, mcycleh\n\t" \ + "bne %0, %2, 1b\n\t" \ + : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ + *(x) = lo | ((uint64_t) hi << 32); \ + } + +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq) +{ + + uint32_t start_mtime = CLINT_REG(CLINT_MTIME); + uint32_t end_mtime = start_mtime + mtime_ticks + 1; + + // Make sure we won't get rollover. + while (end_mtime < start_mtime){ + start_mtime = CLINT_REG(CLINT_MTIME); + end_mtime = start_mtime + mtime_ticks + 1; + } + + // Don't start measuring until mtime edge. + uint32_t tmp = start_mtime; + do { + start_mtime = CLINT_REG(CLINT_MTIME); + } while (start_mtime == tmp); + + uint64_t start_mcycle; + rdmcycle(&start_mcycle); + + while (CLINT_REG(CLINT_MTIME) < end_mtime) ; + + uint64_t end_mcycle; + rdmcycle(&end_mcycle); + uint32_t difference = (uint32_t) (end_mcycle - start_mcycle); + + uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks; + return (uint32_t) freq & 0xFFFFFFFF; + +} + + +void PRCI_use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + // It is OK to change this even if we are running off of it. + + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0); + + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + PRCI_use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if desired. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + + // To overclock, use the hfrosc + if (hfrosctrim >= 0 && hfroscdiv >= 0) { + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + } + + // Set DIV Settings for PLL + + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + if (finaldiv == 1){ + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1)); + } + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = CLINT_REG(CLINT_MTIME); + while (CLINT_REG(CLINT_MTIME) - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0); + + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); + + // If we're running off HFXOSC, turn off the HFROSC to + // save power. + if (refsel) { + PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); + } + +} + +void PRCI_use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + PRCI_use_hfrosc(4, 16); +} + +void PRCI_use_hfxosc(uint32_t finaldiv) +{ + + PRCI_use_pll(1, // Use HFXTAL + 1, // Bypass = 1 + 0, // PLL settings don't matter + 0, // PLL settings don't matter + 0, // PLL settings don't matter + finaldiv, + -1, + -1); +} + +// This is a generic function, which +// doesn't span the entire range of HFROSC settings. +// It only adjusts the trim, which can span a hundred MHz or so. +// This function does not check the legality of the PLL settings +// at all, and it is quite possible to configure invalid PLL settings +// this way. +// It returns the actual measured CPU frequency. + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target ) +{ + + uint32_t hfrosctrim = 0; + uint32_t hfroscdiv = 4; + uint32_t prev_trim = 0; + + // In this function we use PLL settings which + // will give us a 32x multiplier from the output + // of the HFROSC source to the output of the + // PLL. We first measure our HFROSC to get the + // right trim, then finally use it as the PLL source. + // We should really check here that the f_cpu + // requested is something in the limit of the PLL. For + // now that is up to the user. + + // This will undershoot for frequencies not divisible by 16. + uint32_t desired_hfrosc_freq = (f_cpu/ 16); + + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + + // Ignore the first run (for icache reasons) + uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + uint32_t prev_freq = cpu_freq; + + while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){ + prev_trim = hfrosctrim; + prev_freq = cpu_freq; + hfrosctrim ++; + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + } + + // We couldn't go low enough + if (prev_freq > desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // We couldn't go high enough + if (cpu_freq < desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // Check for over/undershoot + switch(target) { + case(PRCI_FREQ_CLOSEST): + if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + } else { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + break; + case(PRCI_FREQ_UNDERSHOOT): + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + break; + default: + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + +} + +#endif diff --git a/hello/bsp/drivers/fe300prci/fe300prci_driver.h b/hello/bsp/drivers/fe300prci/fe300prci_driver.h new file mode 100644 index 0000000..7100f46 --- /dev/null +++ b/hello/bsp/drivers/fe300prci/fe300prci_driver.h @@ -0,0 +1,79 @@ +// See LICENSE file for license details + +#ifndef _FE300PRCI_DRIVER_H_ +#define _FE300PRCI_DRIVER_H_ + +__BEGIN_DECLS + +#include + +typedef enum prci_freq_target { + + PRCI_FREQ_OVERSHOOT, + PRCI_FREQ_CLOSEST, + PRCI_FREQ_UNDERSHOOT + +} PRCI_freq_target; + +/* Measure and return the approximate frequency of the + * CPU, as given by measuring the mcycle counter against + * the mtime ticks. + */ +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq); + +/* Safely switch over to the HFROSC using the given div + * and trim settings. + */ +void PRCI_use_hfrosc(int div, int trim); + +/* Safely switch over to the 16MHz HFXOSC, + * applying the finaldiv clock divider (1 is the lowest + * legal value). + */ +void PRCI_use_hfxosc(uint32_t finaldiv); + +/* Safely switch over to the PLL using the given + * settings. + * + * Note that not all combinations of the inputs are actually + * legal, and this function does not check for their + * legality ("safely" means that this function won't turn off + * or glitch the clock the CPU is actually running off, but + * doesn't protect against you making it too fast or slow.) + */ + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim); + +/* Use the default clocks configured at reset. + * This is ~16Mhz HFROSC and turns off the LFROSC + * (on the current FE310 Dev Platforms, an external LFROSC is + * used as it is more power efficient). + */ +void PRCI_use_default_clocks(); + +/* This routine will adjust the HFROSC trim + * while using HFROSC as the clock source, + * measure the resulting frequency, then + * use it as the PLL clock source, + * in an attempt to get over, under, or close to the + * requested frequency. It returns the actual measured + * frequency. + * + * Note that the requested frequency must be within the + * range supported by the PLL so not all values are + * achievable with this function, and not all + * are guaranteed to actually work. The PLL + * is rated higher than the hardware. + * + * There is no check on the desired f_cpu frequency, it + * is up to the user to specify something reasonable. + */ + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target); + +__END_DECLS + +#endif + diff --git a/hello/bsp/drivers/plic/plic_driver.c b/hello/bsp/drivers/plic/plic_driver.c new file mode 100644 index 0000000..b27d7a5 --- /dev/null +++ b/hello/bsp/drivers/plic/plic_driver.c @@ -0,0 +1,127 @@ +// See LICENSE for license details. + +#include "sifive/devices/plic.h" +#include "plic/plic_driver.h" +#include "platform.h" +#include "encoding.h" +#include + + +// Note that there are no assertions or bounds checking on these +// parameter values. + +void volatile_memzero(uint8_t * base, unsigned int size) +{ + volatile uint8_t * ptr; + for (ptr = base; ptr < (base + size); ptr++){ + *ptr = 0; + } +} + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ) +{ + + this_plic->base_addr = base_addr; + this_plic->num_sources = num_sources; + this_plic->num_priorities = num_priorities; + + // Disable all interrupts (don't assume that these registers are reset). + unsigned long hart_id = read_csr(mhartid); + volatile_memzero((uint8_t*) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)), + (num_sources + 8) / 8); + + // Set all priorities to 0 (equal priority -- don't assume that these are reset). + volatile_memzero ((uint8_t *)(this_plic->base_addr + + PLIC_PRIORITY_OFFSET), + (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE); + + // Set the threshold to 0. + volatile plic_threshold* threshold = (plic_threshold*) + (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold = 0; + +} + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold_ptr = threshold; + +} + + +void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current | ( 1 << (source & 0x7)); + *current_ptr = current; + +} + +void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current & ~(( 1 << (source & 0x7))); + *current_ptr = current; + +} + +void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){ + + if (this_plic->num_priorities > 0) { + volatile plic_priority * priority_ptr = (volatile plic_priority *) + (this_plic->base_addr + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; + } +} + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ + + unsigned long hart_id = read_csr(mhartid); + + volatile plic_source * claim_addr = (volatile plic_source * ) + (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + + return *claim_addr; + +} + +void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; + +} + diff --git a/hello/bsp/drivers/plic/plic_driver.h b/hello/bsp/drivers/plic/plic_driver.h new file mode 100644 index 0000000..e7d609b --- /dev/null +++ b/hello/bsp/drivers/plic/plic_driver.h @@ -0,0 +1,51 @@ +// See LICENSE file for licence details + +#ifndef PLIC_DRIVER_H +#define PLIC_DRIVER_H + + +__BEGIN_DECLS + +#include "platform.h" + +typedef struct __plic_instance_t +{ + uintptr_t base_addr; + + uint32_t num_sources; + uint32_t num_priorities; + +} plic_instance_t; + +typedef uint32_t plic_source; +typedef uint32_t plic_priority; +typedef uint32_t plic_threshold; + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ); + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold); + +void PLIC_enable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_disable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_set_priority (plic_instance_t * this_plic, + plic_source source, + plic_priority priority); + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic); + +void PLIC_complete_interrupt(plic_instance_t * this_plic, + plic_source source); + +__END_DECLS + +#endif diff --git a/hello/bsp/env/common.mk b/hello/bsp/env/common.mk new file mode 100644 index 0000000..0995009 --- /dev/null +++ b/hello/bsp/env/common.mk @@ -0,0 +1,62 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_COMMON +_SIFIVE_MK_COMMON := # defined + +.PHONY: all +all: $(TARGET) + +include $(BSP_BASE)/libwrap/libwrap.mk + +BOARD ?= freedom-e300-hifive1 +ENV_DIR = $(BSP_BASE)/env +PLATFORM_DIR = $(ENV_DIR)/$(BOARD) + +#TARGET_FLAVOR := -march=rv32imac -mabi=ilp32 -mcmodel=medany -msmall-data-limit=8 -x assembler-with-cpp +TARGET_FLAVOR := -march=rv32i -mabi=ilp32 + +ASM_SRCS += $(ENV_DIR)/start.S +ASM_SRCS += $(ENV_DIR)/entry.S +C_SRCS += $(PLATFORM_DIR)/init.c + +LINKER_SCRIPT := $(PLATFORM_DIR)/link.lds + +INCLUDES += -I$(BSP_BASE)/include +INCLUDES += -I$(BSP_BASE)/drivers/ +INCLUDES += -I$(ENV_DIR) +INCLUDES += -I$(PLATFORM_DIR) + +TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin + +CC := $(TOOL_DIR)/riscv64-unknown-elf-gcc ${TARGET_FLAVOR} +AR := $(TOOL_DIR)/riscv64-unknown-elf-ar +OBJDUMP := $(TOOL_DIR)/riscv64-unknown-elf-objdump + +LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles +LDFLAGS += -L$(ENV_DIR) + +ASM_OBJS := $(ASM_SRCS:.S=.o) +C_OBJS := $(C_SRCS:.c=.o) + +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) +LINK_DEPS += $(LINKER_SCRIPT) + +CLEAN_OBJS += $(TARGET) $(LINK_OBJS) + +CFLAGS += -g + +$(TARGET): $(LINK_OBJS) $(LINK_DEPS) + $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) + $(OBJDUMP) -d $(TARGET) > $(TARGET).dis + +$(ASM_OBJS): %.o: %.S $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(C_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + +.PHONY: clean +clean: + rm -f $(CLEAN_OBJS) + +endif # _SIFIVE_MK_COMMON diff --git a/hello/bsp/env/encoding.h b/hello/bsp/env/encoding.h new file mode 100644 index 0000000..35e0f9f --- /dev/null +++ b/hello/bsp/env/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/hello/bsp/env/entry.S b/hello/bsp/env/entry.S new file mode 100644 index 0000000..1f5de24 --- /dev/null +++ b/hello/bsp/env/entry.S @@ -0,0 +1,97 @@ +// See LICENSE for license details + +#ifndef ENTRY_S +#define ENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x2, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + csrw mepc, a0 + + # Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x1, 1*REGBYTES(sp) + LOAD x2, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + mret + +.weak handle_trap +handle_trap: +1: + j 1b + +#endif diff --git a/hello/bsp/env/freedom-e300-arty/init.c b/hello/bsp/env/freedom-e300-arty/init.c new file mode 100644 index 0000000..a6f4b39 --- /dev/null +++ b/hello/bsp/env/freedom-e300-arty/init.c @@ -0,0 +1,87 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long get_cpu_freq() +{ + return 65000000; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + #endif +} + +void _fini() +{ +} diff --git a/hello/bsp/env/freedom-e300-arty/link.lds b/hello/bsp/env/freedom-e300-arty/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/hello/bsp/env/freedom-e300-arty/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/hello/bsp/env/freedom-e300-arty/openocd.cfg b/hello/bsp/env/freedom-e300-arty/openocd.cfg new file mode 100644 index 0000000..f4b28ed --- /dev/null +++ b/hello/bsp/env/freedom-e300-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/hello/bsp/env/freedom-e300-arty/platform.h b/hello/bsp/env/freedom-e300-arty/platform.h new file mode 100644 index 0000000..d5d6dda --- /dev/null +++ b/hello/bsp/env/freedom-e300-arty/platform.h @@ -0,0 +1,125 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF Mappings +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt Numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS +#include "hifive1.h" + +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/hello/bsp/env/freedom-e300-hifive1/init.c b/hello/bsp/env/freedom-e300-hifive1/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/hello/bsp/env/freedom-e300-hifive1/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/hello/bsp/env/freedom-e300-hifive1/link.lds b/hello/bsp/env/freedom-e300-hifive1/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/hello/bsp/env/freedom-e300-hifive1/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/hello/bsp/env/freedom-e300-hifive1/openocd.cfg b/hello/bsp/env/freedom-e300-hifive1/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/hello/bsp/env/freedom-e300-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/hello/bsp/env/freedom-e300-hifive1/platform.h b/hello/bsp/env/freedom-e300-hifive1/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/hello/bsp/env/freedom-e300-hifive1/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/hello/bsp/env/hifive1.h b/hello/bsp/env/hifive1.h new file mode 100644 index 0000000..4c65f18 --- /dev/null +++ b/hello/bsp/env/hifive1.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_HIFIVE1_H +#define _SIFIVE_HIFIVE1_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. +// These are also mapped to RGB LEDs on the Freedom E300 Arty +// FPGA +// Dev Kit. + +#define RED_LED_OFFSET 22 +#define GREEN_LED_OFFSET 19 +#define BLUE_LED_OFFSET 21 + +// These are the GPIO bit offsets for the differen digital pins +// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. +#define PIN_0_OFFSET 16 +#define PIN_1_OFFSET 17 +#define PIN_2_OFFSET 18 +#define PIN_3_OFFSET 19 +#define PIN_4_OFFSET 20 +#define PIN_5_OFFSET 21 +#define PIN_6_OFFSET 22 +#define PIN_7_OFFSET 23 +#define PIN_8_OFFSET 0 +#define PIN_9_OFFSET 1 +#define PIN_10_OFFSET 2 +#define PIN_11_OFFSET 3 +#define PIN_12_OFFSET 4 +#define PIN_13_OFFSET 5 +//#define PIN_14_OFFSET 8 //This pin is not connected on either board. +#define PIN_15_OFFSET 9 +#define PIN_16_OFFSET 10 +#define PIN_17_OFFSET 11 +#define PIN_18_OFFSET 12 +#define PIN_19_OFFSET 13 + +// These are *PIN* numbers, not +// GPIO Offset Numbers. +#define PIN_SPI1_SCK (13u) +#define PIN_SPI1_MISO (12u) +#define PIN_SPI1_MOSI (11u) +#define PIN_SPI1_SS0 (10u) +#define PIN_SPI1_SS1 (14u) +#define PIN_SPI1_SS2 (15u) +#define PIN_SPI1_SS3 (16u) + +#define SS_PIN_TO_CS_ID(x) \ + ((x==PIN_SPI1_SS0 ? 0 : \ + (x==PIN_SPI1_SS1 ? 1 : \ + (x==PIN_SPI1_SS2 ? 2 : \ + (x==PIN_SPI1_SS3 ? 3 : \ + -1))))) + + +// These buttons are present only on the Freedom E300 Arty Dev Kit. +#ifdef HAS_BOARD_BUTTONS +#define BUTTON_0_OFFSET 15 +#define BUTTON_1_OFFSET 30 +#define BUTTON_2_OFFSET 31 + +#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) + +#endif + +#define HAS_HFXOSC 1 +#define HAS_LFROSC_BYPASS 1 + +#define RTC_FREQ 32768 + +void write_hex(int fd, uint32_t hex); + +#endif /* _SIFIVE_HIFIVE1_H */ diff --git a/hello/bsp/env/iss/init.c b/hello/bsp/env/iss/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/hello/bsp/env/iss/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/hello/bsp/env/iss/link.lds b/hello/bsp/env/iss/link.lds new file mode 100644 index 0000000..bc60026 --- /dev/null +++ b/hello/bsp/env/iss/link.lds @@ -0,0 +1,168 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /*flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M*/ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/hello/bsp/env/iss/openocd.cfg b/hello/bsp/env/iss/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/hello/bsp/env/iss/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/hello/bsp/env/iss/platform.h b/hello/bsp/env/iss/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/hello/bsp/env/iss/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/hello/bsp/env/start.S b/hello/bsp/env/start.S new file mode 100644 index 0000000..b526411 --- /dev/null +++ b/hello/bsp/env/start.S @@ -0,0 +1,54 @@ +// See LICENSE for license details. + + .section .init + .globl _start + .type _start,@function + +_start: + la gp, _gp + la sp, _sp + + /* Load data section */ + la a0, _data_lma + la a1, _data + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start + la a1, _end + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + + /* Call global constructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + +#ifndef __riscv_float_abi_soft + /* Enable FPU */ + li t0, MSTATUS_FS + csrs mstatus, t0 + csrr t1, mstatus + and t1, t1, t0 + beqz t1, 1f + fssr x0 +1: +#endif + + /* argc = argv = 0 */ + li a0, 0 + li a1, 0 + call main + tail exit diff --git a/hello/bsp/include/sifive/bits.h b/hello/bsp/include/sifive/bits.h new file mode 100644 index 0000000..e550f80 --- /dev/null +++ b/hello/bsp/include/sifive/bits.h @@ -0,0 +1,35 @@ +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#ifdef __riscv64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/hello/bsp/include/sifive/const.h b/hello/bsp/include/sifive/const.h new file mode 100644 index 0000000..3e0a681 --- /dev/null +++ b/hello/bsp/include/sifive/const.h @@ -0,0 +1,17 @@ +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/hello/bsp/include/sifive/devices/aon.h b/hello/bsp/include/sifive/devices/aon.h new file mode 100644 index 0000000..63f1db3 --- /dev/null +++ b/hello/bsp/include/sifive/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_AON_H +#define _SIFIVE_AON_H + +/* Register offsets */ + +#define AON_WDOGCFG 0x000 +#define AON_WDOGCOUNT 0x008 +#define AON_WDOGS 0x010 +#define AON_WDOGFEED 0x018 +#define AON_WDOGKEY 0x01C +#define AON_WDOGCMP 0x020 + +#define AON_RTCCFG 0x040 +#define AON_RTCLO 0x048 +#define AON_RTCHI 0x04C +#define AON_RTCS 0x050 +#define AON_RTCCMP 0x060 + +#define AON_BACKUP0 0x080 +#define AON_BACKUP1 0x084 +#define AON_BACKUP2 0x088 +#define AON_BACKUP3 0x08C +#define AON_BACKUP4 0x090 +#define AON_BACKUP5 0x094 +#define AON_BACKUP6 0x098 +#define AON_BACKUP7 0x09C +#define AON_BACKUP8 0x0A0 +#define AON_BACKUP9 0x0A4 +#define AON_BACKUP10 0x0A8 +#define AON_BACKUP11 0x0AC +#define AON_BACKUP12 0x0B0 +#define AON_BACKUP13 0x0B4 +#define AON_BACKUP14 0x0B8 +#define AON_BACKUP15 0x0BC + +#define AON_PMUWAKEUPI0 0x100 +#define AON_PMUWAKEUPI1 0x104 +#define AON_PMUWAKEUPI2 0x108 +#define AON_PMUWAKEUPI3 0x10C +#define AON_PMUWAKEUPI4 0x110 +#define AON_PMUWAKEUPI5 0x114 +#define AON_PMUWAKEUPI6 0x118 +#define AON_PMUWAKEUPI7 0x11C +#define AON_PMUSLEEPI0 0x120 +#define AON_PMUSLEEPI1 0x124 +#define AON_PMUSLEEPI2 0x128 +#define AON_PMUSLEEPI3 0x12C +#define AON_PMUSLEEPI4 0x130 +#define AON_PMUSLEEPI5 0x134 +#define AON_PMUSLEEPI6 0x138 +#define AON_PMUSLEEPI7 0x13C +#define AON_PMUIE 0x140 +#define AON_PMUCAUSE 0x144 +#define AON_PMUSLEEP 0x148 +#define AON_PMUKEY 0x14C + +#define AON_LFROSC 0x070 +/* Constants */ + +#define AON_WDOGKEY_VALUE 0x51F15E +#define AON_WDOGFEED_VALUE 0xD09F00D + +#define AON_WDOGCFG_SCALE 0x0000000F +#define AON_WDOGCFG_RSTEN 0x00000100 +#define AON_WDOGCFG_ZEROCMP 0x00000200 +#define AON_WDOGCFG_ENALWAYS 0x00001000 +#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 +#define AON_WDOGCFG_CMPIP 0x10000000 + +#define AON_RTCCFG_SCALE 0x0000000F +#define AON_RTCCFG_ENALWAYS 0x00001000 +#define AON_RTCCFG_CMPIP 0x10000000 + +#define AON_WAKEUPCAUSE_RESET 0x00 +#define AON_WAKEUPCAUSE_RTC 0x01 +#define AON_WAKEUPCAUSE_DWAKEUP 0x02 +#define AON_WAKEUPCAUSE_AWAKEUP 0x03 + +#define AON_RESETCAUSE_POWERON 0x0000 +#define AON_RESETCAUSE_EXTERNAL 0x0100 +#define AON_RESETCAUSE_WATCHDOG 0x0200 + +#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF +#define AON_PMUCAUSE_RESETCAUSE 0xFF00 + +#endif /* _SIFIVE_AON_H */ diff --git a/hello/bsp/include/sifive/devices/clint.h b/hello/bsp/include/sifive/devices/clint.h new file mode 100644 index 0000000..cd3e0c7 --- /dev/null +++ b/hello/bsp/include/sifive/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/hello/bsp/include/sifive/devices/gpio.h b/hello/bsp/include/sifive/devices/gpio.h new file mode 100644 index 0000000..f7f0acb --- /dev/null +++ b/hello/bsp/include/sifive/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/hello/bsp/include/sifive/devices/otp.h b/hello/bsp/include/sifive/devices/otp.h new file mode 100644 index 0000000..93833e2 --- /dev/null +++ b/hello/bsp/include/sifive/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_OTP_H +#define _SIFIVE_OTP_H + +/* Register offsets */ + +#define OTP_LOCK 0x00 +#define OTP_CK 0x04 +#define OTP_OE 0x08 +#define OTP_SEL 0x0C +#define OTP_WE 0x10 +#define OTP_MR 0x14 +#define OTP_MRR 0x18 +#define OTP_MPP 0x1C +#define OTP_VRREN 0x20 +#define OTP_VPPEN 0x24 +#define OTP_A 0x28 +#define OTP_D 0x2C +#define OTP_Q 0x30 +#define OTP_READ_TIMINGS 0x34 + +#endif diff --git a/hello/bsp/include/sifive/devices/plic.h b/hello/bsp/include/sifive/devices/plic.h new file mode 100644 index 0000000..e1ca5d6 --- /dev/null +++ b/hello/bsp/include/sifive/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/hello/bsp/include/sifive/devices/prci.h b/hello/bsp/include/sifive/devices/prci.h new file mode 100644 index 0000000..1a3de58 --- /dev/null +++ b/hello/bsp/include/sifive/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PRCI_H +#define _SIFIVE_PRCI_H + +/* Register offsets */ + +#define PRCI_HFROSCCFG (0x0000) +#define PRCI_HFXOSCCFG (0x0004) +#define PRCI_PLLCFG (0x0008) +#define PRCI_PLLDIV (0x000C) +#define PRCI_PROCMONCFG (0x00F0) + +/* Fields */ +#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) +#define ROSC_TRIM(x) (((x) & 0x1F) << 16) +#define ROSC_EN(x) (((x) & 0x1 ) << 30) +#define ROSC_RDY(x) (((x) & 0x1 ) << 31) + +#define XOSC_EN(x) (((x) & 0x1) << 30) +#define XOSC_RDY(x) (((x) & 0x1) << 31) + +#define PLL_R(x) (((x) & 0x7) << 0) +// single reserved bit for F LSB. +#define PLL_F(x) (((x) & 0x3F) << 4) +#define PLL_Q(x) (((x) & 0x3) << 10) +#define PLL_SEL(x) (((x) & 0x1) << 16) +#define PLL_REFSEL(x) (((x) & 0x1) << 17) +#define PLL_BYPASS(x) (((x) & 0x1) << 18) +#define PLL_LOCK(x) (((x) & 0x1) << 31) + +#define PLL_R_default 0x1 +#define PLL_F_default 0x1F +#define PLL_Q_default 0x3 + +#define PLL_REFSEL_HFROSC 0x0 +#define PLL_REFSEL_HFXOSC 0x1 + +#define PLL_SEL_HFROSC 0x0 +#define PLL_SEL_PLL 0x1 + +#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) +#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) + +#define PROCMON_DIV(x) (((x) & 0x1F) << 0) +#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) +#define PROCMON_EN(x) (((x) & 0x1) << 16) +#define PROCMON_SEL(x) (((x) & 0x3) << 24) +#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) + +#define PROCMON_SEL_HFCLK 0 +#define PROCMON_SEL_HFXOSCIN 1 +#define PROCMON_SEL_PLLOUTDIV 2 +#define PROCMON_SEL_PROCMON 3 + +#endif // _SIFIVE_PRCI_H diff --git a/hello/bsp/include/sifive/devices/pwm.h b/hello/bsp/include/sifive/devices/pwm.h new file mode 100644 index 0000000..067889a --- /dev/null +++ b/hello/bsp/include/sifive/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PWM_H +#define _SIFIVE_PWM_H + +/* Register offsets */ + +#define PWM_CFG 0x00 +#define PWM_COUNT 0x08 +#define PWM_S 0x10 +#define PWM_CMP0 0x20 +#define PWM_CMP1 0x24 +#define PWM_CMP2 0x28 +#define PWM_CMP3 0x2C + +/* Constants */ + +#define PWM_CFG_SCALE 0x0000000F +#define PWM_CFG_STICKY 0x00000100 +#define PWM_CFG_ZEROCMP 0x00000200 +#define PWM_CFG_DEGLITCH 0x00000400 +#define PWM_CFG_ENALWAYS 0x00001000 +#define PWM_CFG_ONESHOT 0x00002000 +#define PWM_CFG_CMP0CENTER 0x00010000 +#define PWM_CFG_CMP1CENTER 0x00020000 +#define PWM_CFG_CMP2CENTER 0x00040000 +#define PWM_CFG_CMP3CENTER 0x00080000 +#define PWM_CFG_CMP0GANG 0x01000000 +#define PWM_CFG_CMP1GANG 0x02000000 +#define PWM_CFG_CMP2GANG 0x04000000 +#define PWM_CFG_CMP3GANG 0x08000000 +#define PWM_CFG_CMP0IP 0x10000000 +#define PWM_CFG_CMP1IP 0x20000000 +#define PWM_CFG_CMP2IP 0x40000000 +#define PWM_CFG_CMP3IP 0x80000000 + +#endif /* _SIFIVE_PWM_H */ diff --git a/hello/bsp/include/sifive/devices/spi.h b/hello/bsp/include/sifive/devices/spi.h new file mode 100644 index 0000000..916d86b --- /dev/null +++ b/hello/bsp/include/sifive/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + + +#endif /* _SIFIVE_SPI_H */ diff --git a/hello/bsp/include/sifive/devices/uart.h b/hello/bsp/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/hello/bsp/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/hello/bsp/include/sifive/sections.h b/hello/bsp/include/sifive/sections.h new file mode 100644 index 0000000..848c237 --- /dev/null +++ b/hello/bsp/include/sifive/sections.h @@ -0,0 +1,16 @@ +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/hello/bsp/libwrap/libwrap.mk b/hello/bsp/libwrap/libwrap.mk new file mode 100644 index 0000000..313ed00 --- /dev/null +++ b/hello/bsp/libwrap/libwrap.mk @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_LIBWRAP +_SIFIVE_MK_LIBWRAP := # defined + +LIBWRAP_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +LIBWRAP_DIR := $(LIBWRAP_DIR:/=) + +LIBWRAP_SRCS := \ + stdlib/malloc.c \ + sys/open.c \ + sys/lseek.c \ + sys/read.c \ + sys/write.c \ + sys/fstat.c \ + sys/stat.c \ + sys/close.c \ + sys/link.c \ + sys/unlink.c \ + sys/execve.c \ + sys/fork.c \ + sys/getpid.c \ + sys/kill.c \ + sys/wait.c \ + sys/isatty.c \ + sys/times.c \ + sys/sbrk.c \ + sys/_exit.c \ + misc/write_hex.c + +LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f)) +LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o) + +LIBWRAP_SYMS := malloc free \ + open lseek read write fstat stat close link unlink \ + execve fork getpid kill wait \ + isatty times sbrk _exit + +LIBWRAP := libwrap.a + +LINK_DEPS += $(LIBWRAP) + +LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s)) +LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group + +CLEAN_OBJS += $(LIBWRAP_OBJS) + +$(LIBWRAP_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(LIBWRAP): $(LIBWRAP_OBJS) + $(AR) rcs $@ $^ + +endif # _SIFIVE_MK_LIBWRAP diff --git a/hello/bsp/libwrap/misc/write_hex.c b/hello/bsp/libwrap/misc/write_hex.c new file mode 100644 index 0000000..e678bdc --- /dev/null +++ b/hello/bsp/libwrap/misc/write_hex.c @@ -0,0 +1,19 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "platform.h" + +void write_hex(int fd, uint32_t hex) +{ + uint8_t ii; + uint8_t jj; + char towrite; + write(fd , "0x", 2); + for (ii = 8 ; ii > 0; ii--) { + jj = ii - 1; + uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4)); + towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA)); + write(fd, &towrite, 1); + } +} diff --git a/hello/bsp/libwrap/stdlib/malloc.c b/hello/bsp/libwrap/stdlib/malloc.c new file mode 100644 index 0000000..8f4f432 --- /dev/null +++ b/hello/bsp/libwrap/stdlib/malloc.c @@ -0,0 +1,17 @@ +/* See LICENSE for license details. */ + +/* These functions are intended for embedded RV32 systems and are + obviously incorrect in general. */ + +void* __wrap_malloc(unsigned long sz) +{ + extern void* sbrk(long); + void* res = sbrk(sz); + if ((long)res == -1) + return 0; + return res; +} + +void __wrap_free(void* ptr) +{ +} diff --git a/hello/bsp/libwrap/sys/_exit.c b/hello/bsp/libwrap/sys/_exit.c new file mode 100644 index 0000000..7261891 --- /dev/null +++ b/hello/bsp/libwrap/sys/_exit.c @@ -0,0 +1,17 @@ +/* See LICENSE of license details. */ + +#include +#include "platform.h" + +void __wrap__exit(int code) +{ +//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); + const char message[] = "\nProgam has exited with code:"; +//*leds = (~(code)); + + write(STDERR_FILENO, message, sizeof(message) - 1); + write_hex(STDERR_FILENO, code); + write(STDERR_FILENO, "\n", 1); + + for (;;); +} diff --git a/hello/bsp/libwrap/sys/close.c b/hello/bsp/libwrap/sys/close.c new file mode 100644 index 0000000..e4f8e14 --- /dev/null +++ b/hello/bsp/libwrap/sys/close.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_close(int fd) +{ + return _stub(EBADF); +} diff --git a/hello/bsp/libwrap/sys/execve.c b/hello/bsp/libwrap/sys/execve.c new file mode 100644 index 0000000..6178a01 --- /dev/null +++ b/hello/bsp/libwrap/sys/execve.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_execve(const char* name, char* const argv[], char* const env[]) +{ + return _stub(ENOMEM); +} diff --git a/hello/bsp/libwrap/sys/fork.c b/hello/bsp/libwrap/sys/fork.c new file mode 100644 index 0000000..13a3e65 --- /dev/null +++ b/hello/bsp/libwrap/sys/fork.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int fork(void) +{ + return _stub(EAGAIN); +} diff --git a/hello/bsp/libwrap/sys/fstat.c b/hello/bsp/libwrap/sys/fstat.c new file mode 100644 index 0000000..6ea3e6a --- /dev/null +++ b/hello/bsp/libwrap/sys/fstat.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +int __wrap_fstat(int fd, struct stat* st) +{ + if (isatty(fd)) { + st->st_mode = S_IFCHR; + return 0; + } + + return _stub(EBADF); +} diff --git a/hello/bsp/libwrap/sys/getpid.c b/hello/bsp/libwrap/sys/getpid.c new file mode 100644 index 0000000..5aa510b --- /dev/null +++ b/hello/bsp/libwrap/sys/getpid.c @@ -0,0 +1,6 @@ +/* See LICENSE of license details. */ + +int __wrap_getpid(void) +{ + return 1; +} diff --git a/hello/bsp/libwrap/sys/isatty.c b/hello/bsp/libwrap/sys/isatty.c new file mode 100644 index 0000000..55eab0a --- /dev/null +++ b/hello/bsp/libwrap/sys/isatty.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */ + +#include + +int __wrap_isatty(int fd) +{ + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + return 1; + + return 0; +} diff --git a/hello/bsp/libwrap/sys/kill.c b/hello/bsp/libwrap/sys/kill.c new file mode 100644 index 0000000..9c56632 --- /dev/null +++ b/hello/bsp/libwrap/sys/kill.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_kill(int pid, int sig) +{ + return _stub(EINVAL); +} diff --git a/hello/bsp/libwrap/sys/link.c b/hello/bsp/libwrap/sys/link.c new file mode 100644 index 0000000..9340cad --- /dev/null +++ b/hello/bsp/libwrap/sys/link.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_link(const char *old_name, const char *new_name) +{ + return _stub(EMLINK); +} diff --git a/hello/bsp/libwrap/sys/lseek.c b/hello/bsp/libwrap/sys/lseek.c new file mode 100644 index 0000000..46f58fa --- /dev/null +++ b/hello/bsp/libwrap/sys/lseek.c @@ -0,0 +1,14 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +off_t __wrap_lseek(int fd, off_t ptr, int dir) +{ + if (isatty(fd)) + return 0; + + return _stub(EBADF); +} diff --git a/hello/bsp/libwrap/sys/open.c b/hello/bsp/libwrap/sys/open.c new file mode 100644 index 0000000..d1871f9 --- /dev/null +++ b/hello/bsp/libwrap/sys/open.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_open(const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/hello/bsp/libwrap/sys/openat.c b/hello/bsp/libwrap/sys/openat.c new file mode 100644 index 0000000..7f1c945 --- /dev/null +++ b/hello/bsp/libwrap/sys/openat.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_openat(int dirfd, const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/hello/bsp/libwrap/sys/read.c b/hello/bsp/libwrap/sys/read.c new file mode 100644 index 0000000..4e57f08 --- /dev/null +++ b/hello/bsp/libwrap/sys/read.c @@ -0,0 +1,30 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_read(int fd, void* ptr, size_t len) +{ + uint8_t * current = (uint8_t *)ptr; + volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + + ssize_t result = 0; + + if (isatty(fd)) { + for (current = (uint8_t *)ptr; + (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); + current ++) { + *current = *uart_rx; + result++; + } + return result; + } + + return _stub(EBADF); +} diff --git a/hello/bsp/libwrap/sys/sbrk.c b/hello/bsp/libwrap/sys/sbrk.c new file mode 100644 index 0000000..6e6b36a --- /dev/null +++ b/hello/bsp/libwrap/sys/sbrk.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include + +void *__wrap_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} diff --git a/hello/bsp/libwrap/sys/stat.c b/hello/bsp/libwrap/sys/stat.c new file mode 100644 index 0000000..1ccc2f4 --- /dev/null +++ b/hello/bsp/libwrap/sys/stat.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +int __wrap_stat(const char* file, struct stat* st) +{ + return _stub(EACCES); +} diff --git a/hello/bsp/libwrap/sys/stub.h b/hello/bsp/libwrap/sys/stub.h new file mode 100644 index 0000000..fb5e5be --- /dev/null +++ b/hello/bsp/libwrap/sys/stub.h @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ +#ifndef _SIFIVE_SYS_STUB_H +#define _SIFIVE_SYS_STUB_H + +static inline int _stub(int err) +{ + return -1; +} + +#endif /* _SIFIVE_SYS_STUB_H */ diff --git a/hello/bsp/libwrap/sys/times.c b/hello/bsp/libwrap/sys/times.c new file mode 100644 index 0000000..26a9566 --- /dev/null +++ b/hello/bsp/libwrap/sys/times.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +clock_t __wrap_times(struct tms* buf) +{ + return _stub(EACCES); +} diff --git a/hello/bsp/libwrap/sys/unlink.c b/hello/bsp/libwrap/sys/unlink.c new file mode 100644 index 0000000..b62b1ba --- /dev/null +++ b/hello/bsp/libwrap/sys/unlink.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_unlink(const char* name) +{ + return _stub(ENOENT); +} diff --git a/hello/bsp/libwrap/sys/wait.c b/hello/bsp/libwrap/sys/wait.c new file mode 100644 index 0000000..ea3225b --- /dev/null +++ b/hello/bsp/libwrap/sys/wait.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int wait(int* status) +{ + return _stub(ECHILD); +} diff --git a/hello/bsp/libwrap/sys/write.c b/hello/bsp/libwrap/sys/write.c new file mode 100644 index 0000000..d00eb17 --- /dev/null +++ b/hello/bsp/libwrap/sys/write.c @@ -0,0 +1,29 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_write(int fd, const void* ptr, size_t len) +{ + const uint8_t * current = (const char *)ptr; + + if (isatty(fd)) { + for (size_t jj = 0; jj < len; jj++) { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = current[jj]; + + if (current[jj] == '\n') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = '\r'; + } + } + return len; + } + + return _stub(EBADF); +} diff --git a/hello/hello b/hello/hello new file mode 100755 index 0000000000000000000000000000000000000000..467a96ed18bdbef20e758fed265fcd812c958729 GIT binary patch literal 65624 zcmeFa3w%`7wLiYkYtBhBgvcZ$;DdolAYdSYQ1R_VqF{}PiWMz7gh?RLkYFA>td(#B z1|PkZjz6)MR$Hl$*4xL8Emm!>-r~htZ%bReSZk{lE4J6xw4(75!vFhS`<$5x;-lVs zd;9zU$R~5oT6?d(_S$Q&z4qGs?3uInjJh)o!%)GWsa{hWi$`Z7@#R6CGgC#CrOMT4 zRiyI^m>!Sv^FWzW{5VWPx|EL-QQZ%e#iLcWQv8INBIO83S~t?W3EQ5|2if7j!x}iO zfx{X&tbxNCIIMxg8aS+h!x}iOfx{X&tbxNCIIMyHW({mU;*msZ-MW7*u6ZO8G1eU@ z#yURYY`A2zgY*p>hKfT-4~1%ygO916366^0aUt^0P^k@Ps68(~HdG9{h~u25>7CP( ztG}aSQAcR@w0vi%xQP57TmEW6chjo{sxyL3f)qZls`&A3NQ)T8o3RN;s95QE6`MF+ z#mZ|`Y|42mR#C5F)2;-sb!KeBCNoz0WivMM+h(l%Q8PB>XJ)M8w`OeGpUqg*a8TYs zc?abkly^|xL3sz|9h7%b-bHyAV_B2dSv`{;wXAZ(?kTUat;y@`p2?5e))d3(nNs6e$F6gFj(yazDvVH1MNP<> zx-Qf+_0f-}B7gLDG}9 zCkpw=+c2zU-9desx?&S;U5_oi_NN90My58;QF0$}UAgad-{k#H(8L^jXxk*CAl19W zvhH?O07q8M8jRhs*T;La@_MbvvK^M>%`s8VwP(2=>Dxxp*@egLz(pK zvNwOIvOSY(hf5oJ6-TLAALg(bmKJM$?D?I)7h|Z+%2L?`K zKU<}bX7}+>Y#PR1#X1F>GPhj>yWep4B@w3pwxgmE=MMF1|Lsp_Y-s&Z3Ou$=ibug~ z@~f&~1nmO$X<4wjSNorPmb8&;Aq#L#H)qPL>ZV+gA>boJJC1!-&G%9+ z>`vPv#@0FmwrKjcI84si#I3MJ*m$S_^1ARZkXOxL9YNh33(3&~q6>@%;Qa^QgD1vQ zmVH;;&#{0sJyvKN7RE?q)xgMD_g>-0v>(HSkQohM(CNtGIt(Y|8e1 zvGQH}ViRB72Y-UQJ=9aW9X_Q{><#w)dQX}CI%R&fVCV5-2fb+T=2Ddk*$4W1-%zn{ z?0v%`-6Z?#r8fpDs2wW#7KG{^#E2cxY2`>IFR4gJ%7{z1?Ep`y#y< z^N_)U4)??dV0&?=2XJchB#e2~;|?h6?i~X`T2Ob-T{{L+?oBHB#%|ce3P;<9vN&GA zOX{KQdzBtXemz5bPVX0a;2-l~lX>v>d9cf{ZFC>q4;!-JxbV z@B_|I?0R_x0{p)*M&qaRnO6 zf;q|pJ^Ac8eE?&z_8s7FRlCoFelPm=c~jFv2GT=Lkr%#M&wI5)Jv(H~Y8|HgvR3m4 zo#t6PwCD1HLE0GlG=x44S(9r*J(G9|jWolLNYV&%4!iLl)hUd-_8-L*gB&Ucba2dW~lfBMo?Z|_u& z0s59@7&9q%r|@m-AICZ@*3s6Vcn9`32)l>vfd*x%=VqOgnp=U$UorJOR1drkU4 z=l=zI+n?QTtU(b5XqOJ*~N%gKmOwxNG(%UPtSa)GO-!+Fm zd%uOcdeApk+4jL#`xDzSZ;i|5Yu)Q&?#R*e+jZ_#aA{oO9EB&N-xm{^FEh+6?-Gf9PM*ZS}_)^{(wHsB^xrgWCOw-(Ydhw+U09pENWTL=Y8$a>g$DF!rh4ZLQ7@2ZD22EOvhL^l zW}C|xY0k%CXAgr}_roP}R!@pnDaUd#@^p-GRA-F+X6oWzVzj5Mi_pegUzp z56^NB9N>DQdf=t>I^m$$D?KO3T!8f#;v)F&?SqJm24fRn91M6_sE08=rw_7gTUx(Ad82DGZJTSWAU(|=>1>zAcVKSR?Znv5 z-!{i6h;S?-|KRfQr&zbGlJtNld=X@s1E1-hHe817gQ?AT>-9=8`m)!3gzd?uIk^5q z%XhGz2Z!kyYlf#|rCVif1^ang`_uJ9h#BH3tl_Xm(Ce*En}RaJ>J03Ym?Nsg86{+CEEYEZhtNO?LeIInuQp#2Y!9e5}zKi0(dZO zztCVV?I~No-zu~Bzp8d#O<&$qhOvP$hxM7P{~3F*pGl|FcV07`?xvL*5Ax@)CeB!Z z^no6G;4j}tm)#g&vy(TurmV;MZ~s$7){o=<6ag>jx;u8y-qU#}ozM4RUA}9b7wj8I zANl(Uv)ui|Y)I4eS{a&NYnE%JZ2`J}eRzB4Urt=c-z@G?aDTwxOVBvh5Ez?299f3A z3**V}e*-@3pfy=$4b47}Vci!A&DZhRhThqFeHzb4pGhpL`#_C@E{C-j{r?{ktY1^1 zenZx_m`5VqE9*}@ux$tYdmT4jRQ1}Vf~xeq zG~gmm1?@7WI&N~SI_6isS6kBlpKX0VAI$ia?KsFsVtyLFM-});*!+H(ugbQ=PE{V| zPp)@8y@q)t#QLaj*oNBkB=%%5MyM~?xUzQWzF;35oX!{|Suh}Te|CAo5qGEbTcCI9 z!vatG!97g_SdZ22M;rs+d=qp$?k{2!+TMeCI@k*vHvf=^>@#@UAEvOk#61V5AvR%L z6U>>}c9QlJfsbI{_1x2YMx?j*46A$&>=E~}Ub**_?a=r{7xP5#8CcWF-I~;E#L5fz z$EMi(V-=W#reO|>Vm_F#3wHM+>IrAB-*Z*JzBx1Mu@YoKi#RrQxrgPjWWwCoyO*(0aUpox+h3|)-y4rj*o5^5Vk7cfP#RC+U>oD2 zLP2Rn;5rj*|!1#gKhS>(YIgel=oo&D2|n zwH?asD2$a36k2!BQ4tS*&*?vq{P@dus$`N%hAp#tL$MJneay4&=`EqHR*!y3RX07Z zVq4uYvC^jsQn1Hl$uAJg?I@{!>EBcg_lOIB{gu6#zfgATHtA=|0{!jRa`g7arcF0` zu-=PR)EIbPfH76izLNcQ^c|injJIMFuQXD*m?y5sC$B*DY`v~9d84hYt+mj>z5|iM zQdPZvy-F_3p$^5)phFXVYGS|Nu%@gtu-|W3#~KFq`&qyElVms-?XN9JZp4_*dFudd z=0IEjbMIJp*D@XP+`xh4QIo9LS4xdN-R@A&UF%D#i;p#WzFw>PR_<2G&xK@dBlLG) zSGcEe)xe$`_r2ZLKkkj#1RMH(Zm{RB?Ik^BwO;iq(3e2x8*=?Vd=7gPPSBsUDeOnB z!`{YpXO@k*=a*+dADir0w4TpTEaYMDV;}Y+j<93paDldrZ8qwc_9_KF{G+H?^lsuy>28o=Hz0YSev}|t%6xO-6~QzQ&l&V8j*{iGOC-e zQ<0-Trc&39c_bA^-&|N{%*riLk=(ZrM7myITYc5_MrwVYiYyv5lD1PIeC*dp&$7X1 z?1`%S^6OP(*RPD~hFT+a^GWFAqDREd(};}N zaG*Npt$20eR-^itrP7Y-FK#tbIXfRgopFrg*D$}e;hC5TcrcQ)VSn}K(dH3I?0;^* z)M4kCkrA+|92@JT{|DEml*mT}x*#DM;wmyKZp;5pOks7|MuT&ocWaR_Lt?EOzyye$f6NO>eseW z{poXzzJ2H)X9Voe#`^iUtoPhhn6Zlu-eKbNViUg%95fm~Cz6MJDKmokbv+XwRjJ)! zquP0jenll$K81cWjOx7qRH;umMs?R2M&Dqa5h-$vKKK6^sYR%})34V-y;FXMb=9B2 zOU;GNf_G52niIkJPHhPLb*nQYluhcUZ0ZcD$2r5mb3G$LSQ+V=wjt-Z)Tw)$5A$TV!mm5xF$SsLuU^s$TP!s_s1#df-}E>mfGnQSv{HdWcng z8TGTR>eSd2%13<(eu|7MDJS^Jl*5{|PIQrx2l|-!sL{86yV^#1dfzyZx)i!t|3%gJ zX)TY`jdrKLIKt@r%pXzb&sg6q>VkFp^&cm7V=PCY6Xbu4cBD zWb}o$8PyLXeJ1*hx}3Ecc6+1h`~G(g*s|(dj(q!md@#;-uQVcsHzR)^>U&hB3csKt zpZt{3_af+K-h{etQGG8q2%akLRLP&aqf)yIRcc=$(l@JA@jl6mEGR@g^7d)TPds0c z8UP)h(WC~j_Zf<-|0cF~4G-BClr zuxG}k*YC}bVC*Ju+#BY)V$ZF6`y&|R9Jh#jyi{IT#(V1e9NZJHrZB(uUHcN+)NSo~ za`zy7u94inJCwTq4>f(o3ykXByHwxJ3yi+Km|LN1>a%*mF6vs@+9r$pnXgO&E5=7pZeTOk=+=(Xs0~Sz&MGZZz9g~r}YhNQ>mvgXI=6; zn{i?CR@(jZH4=~P`W^PtmFn9Iy9iay79Baz&67`|?%hA=+YH;j@IO@b@9q}5h*MQl z?ffoY{ZxP}osMTH2x}kAlg?wPvq(iok5+qbafVn&GVX+u|K@}u*Rp=nBOVHe zO!iIks_!D!ctq$^x1h}B-yITJUwTaSZFnqR-T0JB{l{n(`2_iegkS0(Wc~OK=lo^e zChEK+o_rc>d*@qm=;JNkHO;uUm`57o$tMuc)gcbIO*vN zlUKcNrriFKecSHF7@WoaGpn(O(Rb17su*pKIA@ggxvwkhF&8rE*bsXy@R`ckbNTOJ zYuyIq89cK-+1b|KT;CFH?ueE(1vF&H`X^uR#&b%qqQO0wlvzf zx-r?++1%Dj+Va+}mX^s%t;mf>cZTuZ6nuEk{>=6BnD%^5Ji6G&Ujh8)hxlak`g?`% zL7VpF>2^Pv)!uA*w`8Tyg)SCk=}GxzPtHoa8ZdRNRB61ky?zBdC)w8C7+u=lcxAM{ z6a5vPdsVJtdhY!8wq^CpqfPZ4=%D7##)jys=FX;QvaO-*1%y6 z9M-^L4II|MN7BG6rs`f`sqTmI`A7`@28HA|1yE0Z^}m08=BVW_z49AJVab2^@300A zYv6CAfo@dOy&V@*O~lnO-pL<q?w4=&Wz=oOXedG3%HLKM^v< zGIBg+Se9HhoP9O%D8vBGp|7@|P7b=%yXlA1kWc=hxgix&zXIVts2z>1o$YHf?dV23 ztgvCdyYBar`|mCN{Ux`uwEX^*e{b!|mM2?shb_|m{UwY2T>@i#m)%yjt>~=mXsT~- zY^ZE+?nthzJhQ#Av7v4G1)W_D&25!4s-_=bHGRg6$_tv$Y+l)@X^xvYwX5}t*0xox zQyW{BPFGn zH$&2e4{DXVV8$UoU2=z|OTEKVG>3On>RL?7@K@2J)mjU<(g%lp$=TAZx&WgU;7px? zPN20p(M)ZkGgEXHw3{OoXIKoJz~czrc6fvySNY+`#{WwmLwxgaznk$9tMEJ`v7#M* zVCj2%3Jmu8_GQBy1sp=!Q2*0bT419s$PS?drPD6Y7P*`p5c?_FuEFx%z;M@~8H<+0HE4Gl z1csD2<47{l+MM!?Y{SZF%^=BlLILz{$E`JCi960AKh#7W1mOcpT33rcLej?JlA$BD zWa(?BtetawIycZR>BGW52vuMdD68d@_Jbs3ecBI?S-a=cQ^Uij6V{cT(jk-uKE0NW zu36V^3eP|i)*Ha=sQ_jzfrc~k1QN2>N`0+Lp9hu!K||0P>O_hID#+$TkU*eo{50XJ z8%#^m5G_esZd1#kH`6>!ZI4I`O8PaWW!BSDroF+$!jzz0ge45rts9oE?Nd*~T1&yy z&*?efKutcpR+RfAF?(=gnzquvNb`KN`D`$*DVgby1oox2vmlqc*14KTAUFFaSRkPW zXav*ZC2%dKnt7;c(O+;?;_)lP)v1luRaH})nwKI-o&Gn9;@-z6|Ba*C|J&wF)!f?L ziK&VK?7>0pK@n?a_JJ+<0WP5QyahOzs{p2_C%~MO!ugn!@_cUttED}T_AOYCAYL8% zXFoTvQ(Ad2A}VBb%1Fcz=L|+ZI<(buk?DuIeFT zdLFTSZcNwwT}c_{qeK!bJ1CbF&EJrE^=uXd<)z@JB@famt&BPP8MGGuLZGaXDY(es z=jidv_M0;2X)PGy_eC0CVm+>P%Y#{!{wRR8&($(%?L*6ukKSj5XeZz2Pf8th2lGA} z3Q9^J)IvD$*Yu(&19=H${9#ZtWQPU7yF3q5Gu7Pp@-7%u46G{ucFV%QABXaOlKk!T z@!{PXV%M%E2u0ygR<+~6&3pTnj6cbac;PO5-@<@5SYHDUd<($F_V!kWy8yEY(jEuN z^f={(@n|vZj$>DR39K*}leBF;B7%H>#BoV2qgRj5U}V9nIqHVzid|nt&k^JS3|Tqi zOM)4cHZC*hTM)`rkK+2Stsl;ye_u9E%Tmo9^_`t-bO)xDi!n;&mKLRzJFM}6+Bn!n z>3V>_A&q|o*Z*4@pWtz^L$|#NZ7+fO&>dPii>0O7iNe&V4V?!<g{fKrqz`T;I3l z%dzA4|6H*2LB36UkVI4C>JRBf(pKubfRfSN^Vd_kOhvFs49N7gV%X4?@vP`C0C7nG zQbPVhSrV@fCbab4TZj{z9^x}lt*O3vC@Y^ft#a7E-f-lGEk{0Y9c@cHr!HNghLNGv zyD358Z`mrfysM>QX|-05&p|uihPJLHEsYv(X=`1^4={iDs?xaNy~hNT_NfAz@ekLr;V!Z#ZY>ndq* z$k#3#ub1e7K69y0s$Mk1zR^k>gi zf-RGbR60HT`W|xn^1nOxy;9z*u3!V^U>P)@cXQLSy}Q)ADYH|u;jGrdNMHr6GOt8& zeOCp_O{ufNB zfB)M0>jH!iv=4?Q3_pfBi(#dhjYXM6DKoUc{Hq>s2CFrM9(aBMJ_ti#*6COc>7C8X z8LA)^U({&otS1S+tt0W_R6G~wBUXG<9v0X-6@sGQS|tt7>H@i%;6m}|n6(q&LLPM( znq$1cty=W3dV1rGtsQVaADZg0!`A!Vq(YwdyA$7g#QptSh~6hTJf1$>v4{Vi@ic6N z9V*ICZ-cHZ)?YG#mO#0?u{7o{N2)!UT?|I%#hZ&~nhIq3bd|OyqH=>+*?gao5{C~u8DTwo35Ua9Mj`hU!Uf@O!lx2044+7v(+HP@;e?eNCwx@+ zD@?B;992g|z|=F`k6*%?*RqDQ392w-W4DfQ_o%y#@2e|O#^DMBp z1Bv8g!KOU7>kmM}LzHeMK^4A)@G9X94m5-ON{}|W-x-URj!djj?stW9WTIWU+k|jr zVwG|qAn1jsQ-beRlU4XF!VeP8ADLLPRJjj5hB^wu-$IJ}FzHLe<4N;FHvFjYV}u{; z#qf@XJ1}hB9p46A8t!9jpLhyzdH7-K`^T>Wt{9oVZZa$%#2x=?cwv!Tt|$QsS8VxF)ox7`y= zW|zE99w(VXRT8HFadQ!*v`c=ULA;W?GDx^&A!RsS$`q8aq&wR@)q|y$bTa2m$*C$? zLS&A40di)R{4?u0OLC4cxtuv?n+?c0x#T3~%rkF54e^p6vz~K>thVIW5Enni%AC0+ zG#&Rm^Kz7_EBQ0Y76{q=lKDg~l;$ib`4h=jn@53c;h3)xx!R=N&Nar2A@*tWa@^{S zF_)70I`dN?eAXN@nLMsF$D`%Xn`82c^_soN!d8_J?&QqVcuNW)UJtqcw7`4tkxA<}YW7?~O`3UIj9qp8ku zMnA+GTMNO$Zp`=u@=L_il?kj$4zN)Z4OU~9V1GoplMME>hicgF0-HR?E=GR7dz!JC z48BUTxWKApH<21aLM87IIo;q_gu^O_x4Timm+;7)?#1Rk7)2%J)bb}ydU93rYnE9g z9c7nHV{cq4R9?wHk?b;)jHfM1$Q<6bbuGD zBm3QUa}apRZDi9WuqwHp$VxNpDYaVV(7_NC9!GQU42~;99c(sh!&0@oZ`%4Pt5e@BmE zEkh>9L9~eQ0rOPc#-9a|y@Cg&Al=RQJMhyv-U|Yzn75}1B8=Y&fqn3C6!XDVBoOyD z;RU1`r;&EhLR^HqvE^fkg<>az#yGtV3FfAz(m0NF#Q~Q!E2Ea`F*mg+HSsfGZ$yZf znDOX~XqT~N14>VNBAsDwS`=GBUWKniOz_g2i+mcEbv z+HWanKbOQhu;Ubbh`{b=AV>#xEaC@tpGSH+u$v1c2<#ZJ`GFn5j~3W5cw}H#i+j!q zxcn17A}lKM1G|anuJCVB!{0oxTgsYsU`H?r><9;e9c4}jc0?H1&BA>ph@>G|f!+P& zCo{xl1P>M1J&5!muw%m+*pXGv6S(l>^DMA;0!asUZvgQFJA&^Q*iFR1)`6W+ex$(e zXQ<;)fgKwj1a>JHcM#ZpA8-)Z{T6T#*u4Wd2<*r+2<#}?p#nPt!!ro%jsP44b}W0S zz-}v45d?Oerh~w)0&)g{9mm5#f!%{BM)D%Luu(Y{dup@Hl!0zK72E`!*y99C$9oTV>NC$QtkB1KIn3E3dR-(+I13NY+9oUtFEFIX< zZZm=1N?@75j=@_du$zkZWdget@+7chydMO1gbQpMWFb|~m@G@>f;J%?H2)}+^s|NE zL;`Ini;_t}=lqZ~EJfSO(16EYBuHRK%aLK^2X+j_e4i5pc3i)w13LykL10Jt(1D$F zE~;U>b$FK!?CvB3Kd>X54(x~=DzNKAx-X#wcK0(*@dG=0@^oOwj!Fl1q)G>Nbfh05 zuxmw4>A;RdAsyHeNe6aB(t+J})RPYEb^$qbV8=4)z>Y{dup^QV?1-cTJ0b@McC->! zDGEVgN1U|^j=+xiivjKjb{@YJ9bDA z*s(5M>m@;nbYRDnaU6?cd9Z^R4YuGrf~Pfx0Ee%PIJo@Sp`qjFb#%5fha9a<53h|aU5>}bw!tB3ZF*pBX<7XWJYqNg5hct`b0^LsBUi}H zO?7Hg4e_^{kQ)Zy6~gyR;9D+y-qLIyURyeuY~Ima>eLkc2$(V!73Sc#rWht}xgS55 zbS&o)W6=`;!TQ)gqantk?SjqK>=u!oxv93C%ob^8@yUQMV}`M$f~!I!p{W*3PGVPn zF-0>jo{AkxADP_RwOkqXbEQEo6$hBVgj5JjE3Otk8f&OHHw#-_@jw=~sG=YXn_n@7 zSd#W>Zu;c3Hz|78J!svuZ!zP`-T0BI$|dy;%J?&Xdum#OsW071@KS;=t_P^bv9V$| zMTB5YoRA7^DrXA5>aC1ZPR6fWKaE6V%Om*Wx7OGx)R?vDzO`Cqr?9NG>7KRt6)-gP zR1#X7?pS-Qv_^KltW8_i9{aCk=%cr;bv+|~HYlqgV-1T`bs_eD$b%S@0nM&LlDTQ& zDX{BD$yF*8n0*})3S!=ZSzO4QJRZBwm=a;=7EuhD8K z*J^nB8m)%OtlZkP>zZSw!za@XSetfUqqQ=b(pa0GyyjTxNFROtnu?QI-Lb61+Vsjb zlUKBLD5FA)-lBa;C-QvZs<)ClS_5A9Iq~RX+>I^wB46w^N(hUSW5vdzLHjY|fv);O z7A>KWb?Krn21QGT6_s5f7^|9j0}CDTCRQ{Hq^=k=R!*xwLUUhqESFfu5mW^_uYwyW zMugski=>ZL0?mDvq+Aqf7E(O3j=BY^x78^i^p{a9;lm10f(NRP0(>Q^{1D5i_uLcr zS5z%vIebNB{T$rQmp3p&FRrXQ3@httNy*wTx2vc%ahmqY^#pgJq<#KX1i6duxZLlP zUGz`|J4bfWLz!Ll&?XW%+(ow<4e}4!p}R)IzOeTO%22?4pyUou_xv343{*Xxtfu!+Claop3?E?4th=nT2Yk&4UtN0+(OlBf?^d=P$PE z(6qeYqKtb2OR7A*i%!_i!`cQrmxR4My^BsboTqou2^ZvbgMoW0;lezj-xrp?A?KGYnVnq7#8Y-le#20g*IhoGSPl zVD6$ngS%GQWdv28-bH7vc3v+Ex%JN@-NQS}054&~H$pjN<#At+AD`z)oAJV^5&kav zQD{n@-bE*<@-D%}T_v2sfo3qm-$kc!=F2X+Q0B`nx)A2eE;>OkFKZV)FKZV)U+de7%d#vbA}%Z1)+`*X8M5^d|t%&tr=F zo6FJe1$lZG{d`a^%+tH*EVU?4@1m2kK}DX&jpT)LVWSG~Mhgm=4Q=w7TM@HHr+3kr zUF`3o3srHP!ov!znZa6NvA>JXoT_4f7kvYA zW)}Oq=*&63*xyCJ1vw`d`@87hM-B1fAG4lwO_J3X`@87OnOp4dqHjT&x?+D9on-Ti z{ati6XF;*Qi_V?Fg(b9M?4r|d=NcvcE;=o<&M5JB(fX{mrpD(4IDD(Wi#`DcIEL{qchNT@zgRq7nZT;}02?*YU^RBJzl$!N zi)z^Jkv4gbS&V${qW_2t{KXbwRqXGg6A2X$+eP?pg~-$f^tSM2Yi(~*`I`@85AbZ)V~i_R%*ezCucelu!XSnThjb0{H>6orh@IBON$)p#zWFfEV9J zlkE~%6<<$erEHC_RvsM;A67}3qm@Uc($0MxJMkCEFg(iNMQ4W`mUO zMSn#KvfHD27hOQTi%xw-^)9-ATw!^81mp_K`yIjYPoh5Km2e@#BA~{W2{9)8^6E&i z+Tx~j>}jB3O>54n1T0{lMcOVLWVX;W}#KgXs(qPHJ3%FUtuT1Hkfe z%>3sYN5!KoX>9pdmYA#)eb!~K65Yz0jtAWWq5C7~N?&5eT|A%QSXH*_R+E3jl+Tbf zegsx#Liz>7j+0uEd?Qe-%Ss1H^jR%=Lun)nTUhGBevF&^R!!+#j*vd3v8K|0BIT_b zTU7csRBe1oWAl%_8r4xP|A5N0YJ9@QDt4crr_=o+Xhy|tWVrs7f}m052`0=c9~qBs zhhZ37$`QOyYSI{5fw)^yM>-y7aoYv_I7XE#fw&xJaT*O4cWw7B2c0QTJ=}YqL6SW6aPMU* z_TO>gL&{td^Qnh>=W#&gsfViraXHT7e(fa?_<^|lbrz98-2LV^kUqlBw-+GEpFkbL za=^tKO=XOf(A=y10XcKR@}?711qjVO3BmON7Y*wJE*jPcTr^xzfY98lrfC+ceESOA zbLhBt;UnUsqF)0p^=6#|Wrcr>8ay4EhZ&lCC(@AYFhg@shvss?#XFhl`hbgf3gH4d z;Nt1fTn@N+r!ie0aPf3#E(ct^8m6ZYxOgA`3~Od+?ww6gKL_#Z2Tv%eh@>Iu=OEstzal?T*<}Rva}Y1VTJ-@Jul~14*Uv$`C2aUcD2J?a{)`Jh zKF@rc;b>%}gyvosBMNyA;;kg8pM!XQXr6D=Fh)vf?tSMRm{tKobML!CS%A>o+a@9u zAT;+LAgB+xc;7pftmJ@;_aNc?0*2<^LvNyP{T#&8p}8Dz@qWmL>*pZeWA||SkOMB> zj@^Lua}e(d?oaFIAl{GpaJQm>p}F@H@~i?3$$m=7jt30UbZ9OIT)bZ#33~k;#M^Z& z;MoNX&Ar_$tDl2-Iy9F9F5a&=U+U)|-fylzyY+Jr?}Zx3sh@**FLH$F=OB9S!U30` zq8Q1GbFbHAT!PR%-=_JAf}e!SvJ@<+ui#IjdWQ-5_BU`X+zz$NV~tFIFe&Jd zbPP{(%CJOf0}0|4X)H2w@aThs;iLeEAEvQ+`w1u z^Cy^3BpUZVY0{nRXxv*QeWRms?^2=C(YSY+N#CiXaW5hLsiSdkvDt$1IvV%tO|CR_ zH0~`iY5h7H_mYC>XxwWML`UOZqxl<1qoZ+esre@$IvV$~qj9fE%IIj^YZgRD@c~EKH(tuS;MZ zje9H28OXq+4|X#_;ekgVR4Pr|$B*pyE|QTa(YV)YvO^>q_g0y#OV`>Nl<=eRe48o9 zaQKPk!4B2}&bK)RkKu?2tn_Y4X4sxXOZh$ksoIamy&;pb*;gSD~cyWkpI+JJP9QaQzfhb3kn)3KczYiVo+wng$5 zlzx&NMtooLn##Jt*+K$-?NnQuP~f=T)IjmRsnLJ`9ua|UgtxEoty@}xo% zWo57zsd!Tp0%JeUy9$LE=kYtxwYc{cqTUZam3+vE&eBJb{fN$w)ogn;*aoo>*GFc- z^_0SH$JOEb$b3OSD%jj}DO0&V@H230@UpdW!f9cv^SJ#Zz$8=P^P`^qik;|klffZ z1dbkEoDrfDu#(F8GO?U|wA$P>U*)bvGLgIn07ol_CDf&&lOk@z>qF_k@O8p37t>6? zhIhGThxz7*3-istD$KVe%=eF{Uw~SDQ*rFAMD*!RQJr1zU8Fenmv9x;*)Ir4)!8x@ zMRh(%)%hS*XUkZ0`>7WIW=aPF5pfD5Kt_RDvFZj3R6xOs29h263Vgau)xP^cCzY zoCwFIgKfD}5?NypAT^rn`i*JoshWBP68U&VQ%@!JHd2=?I4T|`H3P%qn<>CF1z9A0 z5zZv2}+TX zB|$CGj0D#Z%}B5XXmLh@;!N#XH9yEQnVSC{s2cq^E~{xInYRBY=`wA{JLR%#K7(kc zW~%Z7YhKMVnVN3^sz&$Y@|WQ?e~EONntx0*)8>Nku$p5)Kd|OHmdVtd0IEhuG2F(| zXcnh?^wXqUhx&8}e}Qyk=5ttPX!Z`Ld7Ct9?6;1IM=Jn~`nWJ7cqSqQNiStOqa|Y+ z&3PHpNBvsJi1rdaGM#%j(VR58gDCAzOY|C0{FRi9i$@Cp{Fp;GfgKg2l2$%8A8AKE zi^QT#qB`=A2PKSNfhIi*`rz@kVJjt-XNz=Q#nCi)g3%*)qON121V_Jc=YCBRD27CtsW98v75JGLbMx_)}f+59V7MgdykfX znnOoVmVc7N->BBR)0X~PrKRH}L|w0f1g2o?6AH{ zZu(@0^|h}7w3S`T8o$mW_7}A*@e!IHwZUCp(js_IulO4{b+;`S0yG*vD!}%#C(~MbdX~6nqhx41GVZr)jhw}oT zw&;@`&Wjum`ecXmJC?=CjudVrFO&-#Rd@+%D`YmbS&pnCX8GI4&Iu;7W&7AU$rLKt zK6c{fnV63B_OXxX?PDL&+sDr7QbundJF`um=hfTC&Y6;Gd7_Oa7zUWq(8*|8X!vh)hOi10|8 z1}Q4P322te1r=qEw3i{PhzTR@c3dMH(GfJHEOI6VJ@jSLlp%ozmZ3rE$B-aik>(>~ z3CBC;g7QFsW8843(HUnvh1Tf}WhZ9D(Hz-OcFF|S8_Lc^qYQ=h@eXH_!S41@4I7V^ zf#;aT$j^69GuDv-HYz%Fc4(hT|PH6;>$!BxNImpT>|S3 zWoM=N1~TyQl3s?O@WAm7nNVS;K7M4sbCHZi*-&;`O?HTEC_Af6)}?FZT2M-)k9RQT z7!F9WJlMf(z$0yr%40Z20xP{jl6mspqou3^AdLJCWoO8wlaUQ&=YSal?A-#ot)Ppl zB5ni7hH|KoDYBs)Dk_6muyQ15`v*|?%iw~X=KxO_|3$i+^ag8+K@>zUDbY-7|NG$ibe}RnSe+1sS549n0{O?)n2PBKl z0_e*5#k`W2kWl&{5>)BMxEiGmxSFNk#?>mF&6uwA1Y8|8-a}Ge^jl_|Rl%2B?pPGw;MaO}MJr}Z$=%yZI zy)a@O8;iFaZ$=Tzvpy>~ITvmfSib|Y6}9%^=GCC|XYmoO9Z*GU0gsykp+^iFOdrQx zwGpOCxNJVy7>~+0srAECW6MOWBp)@;Lw@B*Y|yti;#&|uG|vQH{wPE`}!7Wa-{pQuRVGZ5FPv4l}*T&K+c{{P-0(uhO|IpUk&TnSHn8? z)v(0Ac6BRCGWO-^4KEj$Yw!_aQIW*H_N)OUN$hK%pao{^YoDlVV(e?5L|DhZ_Q`~G z>}#JwSjWEhsf2axYoA6~$G&!)u#SE08p7$=*Z%k{3~h;h?XwB$*w?NjtYcq$9%c4p zU;8{FjD0=a=YU8Wl8$}tOE-`ok51T^5!9!e?F4Jpv9Dc!1JZTuYcFBL8T*oz_XS+| z@p+E4Wn)pFYPP#}AV*?fdnG{~``W97GdRSNq+?(EI|Hbnv9JAIp=9i9ZxceszV-tI zb?j?@Zw_D```Ql@*0Hbs&{t50j(zQiNv~sH`-g0}j(zRNxG}3^Uwa3?2Bc$O`w4!P zN5{VQkADVO$G-MY$WzC@_D?C9j(zQ&8QK z5wrZ**FM2yw#2^nNv2Rq>}$u(Q!!ua*w;sN?CT>s_O(x!GCKCPXPexN(y_07rsU|@ z7k2P5}#KGo{1bC``YtNjz=B)V%bnI)-mmD4Y+UJ>dD5GOvdx4PY z*w?;LnxkW1d$l|_*0HaBwMo16V_*Bz<{V&t>}#(xF9kn8_O-7yEwuc3eX7~+HJgzq zvF}1?Du{gvkF;r!qVkQ@aYp5W`YKN#tB48s0tBv+ZZwL9lts>@poczB8WyF2WoS_P z`$!P4Nb`}ggxEI@%7FlfgJtY%k2C%qt<$lu9W#zcb0qe)%LLZ3uRYOVH9GdSCmHN+ z#=dMkS_Ymv_O(wl){p^XUpp?aj(zPKL3HeEpKi+SW z{-jxod>#ARi=?-7>}y{tR66#xFEi;)b?j>=q=$9vYcDpFD6eB*yWXrtO*;0qmzW$6 zI`*}bg6P=SZV*JrzILN|8>G>(uf5d#8W0`(+RLOK9sAl%QbxzVcC#Ql_QmfVu^t`! z+E)moV_&;P5FPv4%Y_?aUz!T56onx6CC*v}N9;@d!2oCMYq!gJ4~c#4E`fFIi*Mxf z6b52ndKrSk1Fy~<==y4EUKwvmuiqAv2V^4>Re*qoXU2j zjtMrd3mHYfMDT}DVSpzXGNHr zJ08U%Bq|^gYsD|Mfy@c&#p)@j_joip zQluu0fuR%`lg4NfiX4%A^hCK8r%OAOuf#8n_OOyMStyu|O-m%iNBV6LpKMTSYF@_a{_Oeo9zwrGPLwTVeJh^q1l;M+ZA8mVDrrjBd;lwdC4wWN5 zyDH#+P>GM~ytQHckGk%_c1NZSN=&?9xQTz%dH(Oiq{qXlyx%OJ>8*ntHwJ+??t^SO zuyH!?EK8j<5%px5YhadQG#_LFndr_Ay2Qy;tH);OP=iRgyTixKN2$!WwS(()v+Eo- z)V<-u7O(dRVkYV=H}JE0fuH>#q24Rl4b&0JRG`&yXweY;4p#;R%j%`v3>(Us7j)(a ziI>$u*)xsf>n&)m8#LF;)T71C$!_3#O*(mbBl5y|GWBFeU?y=yF=v=`oS!ujVH)y1 zy-afj+1(ZxqHoANjwx+No!%-PiLWmF}+t*+Zi6+T&tDAt)A_-VSq;yBdqR*Oe5HPP{tI|It;+}BXd0gX z?^A>P;9Ee$^M5-n$Pd2iGCcqEsvtl3F2?Zub7uwl!SU4L`6rzaqA;|%?GLv6r6NDtn{jW^`9cTT%NRW`LPZ>(%wlf0sG zS#xLQ`Da})`x8?aGS^PDk$C9+S$Gar4tPuZHcD( z)`pfwmFQ@`3fFdEGmlq^#^sIe%NkpgYd}=rS+5eSlI@*s%a`D#uJxUuTb1k(yu(l6 z>j$H9!Hd_Lm$f!FM0peyU!}%N*vL46cM8?FG$xR?d|@-ELrefzQwl}NU=UC~UUj%6)fxG!y~XL55# zBDosP!0T0-TfwO13N2Q0Wv6g%Te`FZClVkV+lAHz(m_~!3o*c!;ze3yx3m?PL>EM> zp1~%u$*ij_d4-^z4g8W};`HWaBK@-Z<;&}Z2oRLqh#xA%wWF)06TfgEJvA*U4Z~$s zvT2D3+SUcm5Rl)3Oe}3?C$%=WE$L7lO>OO+(cy|lui%BIRa%t#mV~sbz9Y%E!e~U- zrz=p6tt*?`+gjBs$VZ7OxmsGE>}+dqu5aM^a>R7xV3`W9sXgfvGWJ_axD}Fj40ijkjCh=Oe#)iO(n_HK*;f=-h4T<^& z6kJ}vdQ}4~Lf&DFE@*57BbZ_rhXAlE&}jU!p-4pizywhjzGesIiJ{;%pQP-B?Ol;* zsi$rdE9TH$hOb?6>4gl%;<7U=t3xVzvOS`CvR?(_vA}(b1^y$%A(`HPoicVc#-=1tb zrF~`fjAkNBnontNSy4SBI&~TTbv?};4Qzs_GGlx8~^NsY)`P_V;yQa z-sGm4ET^z5y4X&rx?@#yXR=AHpkOOkw8ISe`=|9SogCmOz?Z+l5TUh%*wzYm3`&b3 zL9tb;p_wB$!8eU3Gy_yOL>+Em9LZC&8*aG>?ST z0a~&+ZYC58cI38#zx%qPy)D_;(SiD4Kpo8(7ld#D1%Es=OBgr+NlxfDy9Sc_)u@KX zmd^Ub^5hzrC0_7EpPlGLQ-TbtS#@DnfE8n`EvfHf@55C?oCGu5eS^aL)$rCxAIW55 zP+qBEGl>-~Eo!-RT1y**;7<$%^9BcQL)-GHjn!3EQ=8;HgVXV}kYjCk@pC z3Qc<>Ja>!gY;Rt!maJJ(-w}A`<7wP{TRE<4Iyh3qFxVKp?<#oVd}Z(!^JG_hJ0?a= z+$!Tr+lml~4zi1-U!Lt-l*ZA7j*j|ejqf54UN`Mi3#yWB4Z|tJkeQOX2+wnLeFbZsMgyT{!n5`V*l%^Zc6G zi3`rZATbkqYEE83e+mYYTvJ<{s7@rOtEKJr$tt;mO~C&Anu`)MINzz-GlkvhiKVP% z^$el8aNa?}b--FW)%k&letw2aVkw%Kt{WmPfJ_Z-tKbTPDzjTUTzt~PkOIm5(j8Yc z!*?I5Gz{e3$p{cIY@vaJ*&K>^0lwf`!^T{A-dS3ku=%SJc(EaMFkL|#=!?YaYFt)A z@dxqbq>@)VPbRJDS z=u3ZqXoF9a`+TlSFcex{rIs{zcF8V4%dsR$Q-Z%V#uR0v|?$Jv9K488C6ibhero@Ui z%!Qn7G2OQ`FKgU^l}2R2i~1{Rck$`J_*uRGKPW~cj(t1 zCbZT22*~A4i}HR%L|2?2IBq+dXQ-Of&q|zCH@|wunHjLwXL>MCj5vh27+>2CN9ZZ{l)@+^7cx75U zAFO0OaQOmP7#@R{6>Tdd0u{H!_EC=7v_xkHb*MSBXP+1?hi93rLp&@tapYSaz@MRv ztBnz+iuw!C;Eh4G`Bih*85_-7ywS;A@M!JhwIj@cro_~5DFRLHMuQaAPJ;yC5zqwh zL8{GgpBj1qDBaSeswq>uQ1YB6Y$1;P(@eKdgNXWbL;u;1&D;V}_Tg zUHXl@w&v@fb5%urd6wmibUT`TmGt|1HB)y60Vff^9Ch zl?wLbvis{`-jrtnXoJ1E4x|FYH;4X@ z`}w@v!e1C+)jGLo*xa9EX#S#hSM5`^|53ZU_UYPR);?4FtGW3&qz+aG%SHSZ)Di6Y z9V$PJZQ$%ZyY(m&QkSIcPo`|bVf0%_y=J|hTXs9)qXgIag!yA*K|bM&vhoS@i&;TF z;rp`k3G-)jf_zk${?l?SO4*klBu7}wF;4jCe8Ootke`u5=MR$u`58HM{xCU^pB4hZ zMtn?FC2c1i;UJ$f2Kl^)k#DGGlC6g00{A$z+m8>xLELOK7U09U?bKkvY7u~2Q6{9W z#TVAb-X0VT@St>n2P^_S;Ij|_#d1}T$~^!^M4rXRP)Ukchfg|>dRm{IK;%Yza@40( zZCUOCckJy%Z_cJ6vSm08(XH7uMD80-L$pqml7uwrzivQ=x`ekdC=7KuZ*v8_m^aFZ zRNk6&DsSvT_C(N=hPs#)ES3r`50r;;f!+WHDg%hxR3gnKt$vvh?3Lz485W{ofCqvE zc)%jS1Cate;ClxE%I2!8w7C({!d=2T9>yn~w-3mh*$IV^pcJ1pMFo(V*$F2Dsm)Gc zi(Bx4%>*(748#Q(ND2_5$lo2fYMI1Hc0mN#3vVwAxQw^3Fuj;JibX~9UZsyc@%3Fg@rChtDCoay&b+HyjDGKu~d<@mV+XMKx7_nko+kt37#YmnN=^9?d zjjDs0@umfB2n0nc<5N+X?|M<*geZwu`^;Nh>kbr5R&sd>$!U zoJ#|7o`rrmeZpAymZqr4a4~PC_*iP~)wdHUm-Ga0aRD#ptqz}DwMJE!tybs2ZxEl4 zj|cy9PU!|U{&r#u@Cm66pc{WX;f2E}h~0`01mKOWhgm<3+nYL->YOP}xj2s7Vh!@v zfR9K>ph?mbysZ}S;;V7%)*#h!p9b&8O>5@j=K;Q~Q?u2f8@Q0Sh4?sVOm*4q1RF%6 zg%oa|1}U7bVRcv~P~g0B);tW$ZTGlk0w$~*#e zyUyk96`jjlKR%Yas_XVa0Je;aOL*gm$zre?-k3k|k1-kWtV7a`lEjHY{un*3m!vC# zr00>eU6Rt{do@^h>za6bQo!b*0CT^EPe|Q>pYuEBcEb1Llc(|PRJ?4$?M!$apDY)~ z-*mf4C-L?QK9<63yaK+rBH<35&)XuAX=#wl!L(R%GczAh-(Lk(oDT}oAVa1^NnM1b zXC*1!kKt^I+4AnjfGz4~CLP z1`09_>F5k&F@EG%ie{G>!puO(z|fci9}FstB(!{}h>AW)s)rznAqs**jDmU)>i6G! zuXFZ2Gm;zD-TS}R+TZ8wbI!j1d+xccC9-#*Y;e!{9xA;6nH(^l4eFy*`g@h6k7Zy} zP$^pHlLOYe7T}CvRiybz8ma-2M?s|(j{7YgiCPy(T5(5kKISv@D!Pu)jSE>fWWR)H zqMl)*l>Qi*959}~8&X|El5U&;o(?KSjWmIh&u1l{K{@8_`7r}*^G(g>N8@_Mdu1c9 zlA63%uOju$7i_(&sYTBE7idj`+OKpEqGHM_$;!-2ebsZS!aYE4ghkLM>S{u0igAyeG5Zb=&_ zX~XQU&a{4&sGiolC8O3=rLBFrePv=_If1=9v3J+l)rfl6J*qg=H9zs4U*oIB-j+9Z z^h@w%gv*XKX$DJryv~`bj}uB)lw=*1X*y!hk4o!)x%hn7imuD+5Bj^&J*0zQz(5~n z@Tq+=uKbDykg_}cV&kY%%7B4SA2#tRHHYs`A{Ch&$tp?5Fpb?rBu8C<6w4d6Ws=(3 zlXPt$yk+S=NZ5htUy*F>ySR= z5ZAXVqFV&rj#(HXaRh0>rmLm}>CPZCST|b{yF)a)ZsRW_=gHH8-NHK3-yuIET5~O= zx;{?xO~^2!W$X}QVIteF*tLdUPyABdnleL=Y(V;uVdOY+0XM} zHkDzvbBSHI!x|G^HFQTbhUo4v4UGVs7ai%XsgZOSVn;&3G!FK(N>yUY6{>L96qh(i z6^_p_9ERvZyWyu(xLZfYEnpe?&U{!Lpb3^6a;E3ap~+QGIr zE)20Q`-e^81>mNJ@Ry*%%fL(H{sL(z=)OR$6^R2@9 zI0m*oY589TpM+zn43+wNzhPqg_p(o7Nw9r*;bySy?@q;kCRpdYj;ChI?*_kdS5NCn zu>AEerDyBH-!BWliC%m6$D;i~>?@`R4yf$w!Ar@n>!a`xcr0n(6JXo-mi?ge&j}n* zwPytUJLTyLB>PKX*JJ&^)&HR;idMA#Y=0U1R{TdirhVYyq`r5-_I-`Y`$YbChIjr8 ze+#xfb=7|bY~LHn{u|iVzX}ucH~4y~r}b>CPY*TK*q#dhx3J`n+!6kCOZlgP#ev1$ z&(AEdeXk*VJ2?D|p7F0QIsLEDwQ2M}mfueKbCdb`O9iP)LWT8vA^vImRx@sk@elS! zw@l^7^}piEZY9{hKU4jB*J+vg(v?SeJ@yvn!{=u_GLB{~VXKw{W;`+@fEmfFhSrsH z*CKH$<64P96{%6i!OZh?P?SVZ{)!4u>_Vjh zsquj;H%^x*EMKi#&>HhE=V+#6E_k7$wnWbJkmxvmVk3zQq7*EJ-H*+$C7`9OJ9S_` zoPz=A%@YzZVIgkbl5{B{*Tx~GQty)w4Vt|W3siA7J?J7ufrJKK^Cwy%ET-LR_^!br zxU|sw%z%#hu-2#4zZ&vcPTUE7H=-d_N(hT#6g?SJEJG#@%6P&h^whhJ8{;q;mCr~} z;Xr{!9=PNB+&H|gpOz)(kJ=eJ>pFKI*e3E+CqonBt(MY!yG{-~K6mZ#<#i7CLloKW zItQ|NPd|Bsk=CmmrWc37&3lI!Wr!Ft?TNcF-M@MBuEBj~>4z&jG)Uf%iTYh9)RS%E z1V$ZHIG838i2EFqF{c)bn+&|<+p$E&J5AP^N?gohe%TaeBj#6SeXZhGnd43Vqa2fW zM?Y37f8Tq29@jJ0FbnZg>h49M@+4XhyH=P-h^1HHhYy(_$?A>#mPfx>6;1TlQM4gg zz4rrEw)}LR?Vw(>$VDho=QvKQ`cJY2{Zxj_PJN2D1%- zEiKb~YAuIH)WPZxMG)YS2QhYNl?xncZ1$!L9lA^LU2B36Cn-1_A9Us)u& z4^eD>ul%6ExhjKIi3mkP literal 0 HcmV?d00001 diff --git a/hello/hello.c b/hello/hello.c new file mode 100644 index 0000000..39b67af --- /dev/null +++ b/hello/hello.c @@ -0,0 +1,72 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +#define IOF_SPI1_MASK (0x38 | 0x4) +int factorial(int i){ + + volatile int result = 1; + for (int ii = 1; ii <= i; ii++) { + result = result * ii; + } + return result; + +} + +unsigned read_adc(unsigned index){ + unsigned char txdata[3]; + unsigned result=0; + volatile int x; + + txdata[0]=0x1; + txdata[1]=(0x8 | (index&0x7))<<4; + txdata[2]=0x0; + + GPIO_REG(GPIO_IOF_SEL) &= ~IOF_SPI1_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF_SPI1_MASK; + + SPI1_REG(SPI_REG_FMT) = + SPI_FMT_PROTO(SPI_PROTO_S) | + SPI_FMT_ENDIAN(SPI_ENDIAN_MSB) | + SPI_FMT_DIR(SPI_DIR_RX) | + SPI_FMT_LEN(8); + SPI1_REG(SPI_REG_CSID) = 0; + SPI1_REG(SPI_REG_CSDEF) = 0xFFFF; + SPI1_REG(SPI_REG_SCKDIV) = 7; + SPI1_REG(SPI_REG_SCKMODE) = SPI_SCK_PHA | SPI_SCK_POL; //shifted on the leading edge, sampled on trailing, Inactive state of SCK is logical 1 + SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; + + while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL) ; + SPI1_REG(SPI_REG_TXFIFO) = txdata[0]; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + + while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL) ; + SPI1_REG(SPI_REG_TXFIFO) = txdata[1]; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + result = (x & 0xFF)<<8; + + while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL) ; + SPI1_REG(SPI_REG_TXFIFO) = txdata[2]; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + result += (x & 0xFF); + + SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; + return result&0x03ff; +} + + +extern void write_hex(int fd, uint32_t hex); + +int main() +{ + write_hex(1, 0x55aa); + volatile int result = factorial (10); + printf("Factorial is %d\n", result); + for(unsigned i=0; i<8; ++i) + printf("ADC%u value read is %u\n", i, read_adc(i)); + printf("End of execution"); + return 0; +} diff --git a/hello/hello.dis b/hello/hello.dis new file mode 100644 index 0000000..f835db3 --- /dev/null +++ b/hello/hello.dis @@ -0,0 +1,2311 @@ + +hello: file format elf32-littleriscv + + +Disassembly of section .init: + +20400000 <_start>: +20400000: 5fc01197 auipc gp,0x5fc01 +20400004: c2818193 addi gp,gp,-984 # 80000c28 <_gp> +20400008: 5fc04117 auipc sp,0x5fc04 +2040000c: ff810113 addi sp,sp,-8 # 80004000 <_sp> +20400010: 00002517 auipc a0,0x2 +20400014: 5a850513 addi a0,a0,1448 # 204025b8 <__fini_array_end> +20400018: 5fc00597 auipc a1,0x5fc00 +2040001c: fe858593 addi a1,a1,-24 # 80000000 <_data> +20400020: 5fc00617 auipc a2,0x5fc00 +20400024: 41060613 addi a2,a2,1040 # 80000430 <__bss_start> +20400028: 00c5fc63 bleu a2,a1,20400040 <_start+0x40> +2040002c: 00052283 lw t0,0(a0) +20400030: 0055a023 sw t0,0(a1) +20400034: 00450513 addi a0,a0,4 +20400038: 00458593 addi a1,a1,4 +2040003c: fec5e8e3 bltu a1,a2,2040002c <_start+0x2c> +20400040: 5fc00517 auipc a0,0x5fc00 +20400044: 3f050513 addi a0,a0,1008 # 80000430 <__bss_start> +20400048: 5fc00597 auipc a1,0x5fc00 +2040004c: 3f058593 addi a1,a1,1008 # 80000438 <_end> +20400050: 00b57863 bleu a1,a0,20400060 <_start+0x60> +20400054: 00052023 sw zero,0(a0) +20400058: 00450513 addi a0,a0,4 +2040005c: feb56ce3 bltu a0,a1,20400054 <_start+0x54> +20400060: 00001517 auipc a0,0x1 +20400064: 6dc50513 addi a0,a0,1756 # 2040173c <__libc_fini_array> +20400068: 688010ef jal ra,204016f0 +2040006c: 740010ef jal ra,204017ac <__libc_init_array> +20400070: 00000513 li a0,0 +20400074: 00000593 li a1,0 +20400078: 384000ef jal ra,204003fc
+2040007c: 6880106f j 20401704 + +Disassembly of section .text: + +20400080 : +20400080: f8010113 addi sp,sp,-128 +20400084: 00112223 sw ra,4(sp) +20400088: 00212423 sw sp,8(sp) +2040008c: 00312623 sw gp,12(sp) +20400090: 00412823 sw tp,16(sp) +20400094: 00512a23 sw t0,20(sp) +20400098: 00612c23 sw t1,24(sp) +2040009c: 00712e23 sw t2,28(sp) +204000a0: 02812023 sw s0,32(sp) +204000a4: 02912223 sw s1,36(sp) +204000a8: 02a12423 sw a0,40(sp) +204000ac: 02b12623 sw a1,44(sp) +204000b0: 02c12823 sw a2,48(sp) +204000b4: 02d12a23 sw a3,52(sp) +204000b8: 02e12c23 sw a4,56(sp) +204000bc: 02f12e23 sw a5,60(sp) +204000c0: 05012023 sw a6,64(sp) +204000c4: 05112223 sw a7,68(sp) +204000c8: 05212423 sw s2,72(sp) +204000cc: 05312623 sw s3,76(sp) +204000d0: 05412823 sw s4,80(sp) +204000d4: 05512a23 sw s5,84(sp) +204000d8: 05612c23 sw s6,88(sp) +204000dc: 05712e23 sw s7,92(sp) +204000e0: 07812023 sw s8,96(sp) +204000e4: 07912223 sw s9,100(sp) +204000e8: 07a12423 sw s10,104(sp) +204000ec: 07b12623 sw s11,108(sp) +204000f0: 07c12823 sw t3,112(sp) +204000f4: 07d12a23 sw t4,116(sp) +204000f8: 07e12c23 sw t5,120(sp) +204000fc: 07f12e23 sw t6,124(sp) +20400100: 34202573 csrr a0,mcause +20400104: 341025f3 csrr a1,mepc +20400108: 00010613 mv a2,sp +2040010c: 234010ef jal ra,20401340 +20400110: 34151073 csrw mepc,a0 +20400114: 000022b7 lui t0,0x2 +20400118: 80028293 addi t0,t0,-2048 # 1800 <__stack_size+0x1000> +2040011c: 3002a073 csrs mstatus,t0 +20400120: 00412083 lw ra,4(sp) +20400124: 00812103 lw sp,8(sp) +20400128: 00c12183 lw gp,12(sp) +2040012c: 01012203 lw tp,16(sp) +20400130: 01412283 lw t0,20(sp) +20400134: 01812303 lw t1,24(sp) +20400138: 01c12383 lw t2,28(sp) +2040013c: 02012403 lw s0,32(sp) +20400140: 02412483 lw s1,36(sp) +20400144: 02812503 lw a0,40(sp) +20400148: 02c12583 lw a1,44(sp) +2040014c: 03012603 lw a2,48(sp) +20400150: 03412683 lw a3,52(sp) +20400154: 03812703 lw a4,56(sp) +20400158: 03c12783 lw a5,60(sp) +2040015c: 04012803 lw a6,64(sp) +20400160: 04412883 lw a7,68(sp) +20400164: 04812903 lw s2,72(sp) +20400168: 04c12983 lw s3,76(sp) +2040016c: 05012a03 lw s4,80(sp) +20400170: 05412a83 lw s5,84(sp) +20400174: 05812b03 lw s6,88(sp) +20400178: 05c12b83 lw s7,92(sp) +2040017c: 06012c03 lw s8,96(sp) +20400180: 06412c83 lw s9,100(sp) +20400184: 06812d03 lw s10,104(sp) +20400188: 06c12d83 lw s11,108(sp) +2040018c: 07012e03 lw t3,112(sp) +20400190: 07412e83 lw t4,116(sp) +20400194: 07812f03 lw t5,120(sp) +20400198: 07c12f83 lw t6,124(sp) +2040019c: 08010113 addi sp,sp,128 +204001a0: 30200073 mret +204001a4: 0000006f j 204001a4 + +204001a8 : +204001a8: fd010113 addi sp,sp,-48 +204001ac: 02112623 sw ra,44(sp) +204001b0: 02812423 sw s0,40(sp) +204001b4: 03010413 addi s0,sp,48 +204001b8: fca42e23 sw a0,-36(s0) +204001bc: 00100793 li a5,1 +204001c0: fef42423 sw a5,-24(s0) +204001c4: 00100793 li a5,1 +204001c8: fef42623 sw a5,-20(s0) +204001cc: 0280006f j 204001f4 +204001d0: fe842783 lw a5,-24(s0) +204001d4: fec42583 lw a1,-20(s0) +204001d8: 00078513 mv a0,a5 +204001dc: 791010ef jal ra,2040216c <__mulsi3> +204001e0: 00050793 mv a5,a0 +204001e4: fef42423 sw a5,-24(s0) +204001e8: fec42783 lw a5,-20(s0) +204001ec: 00178793 addi a5,a5,1 +204001f0: fef42623 sw a5,-20(s0) +204001f4: fec42703 lw a4,-20(s0) +204001f8: fdc42783 lw a5,-36(s0) +204001fc: fce7dae3 ble a4,a5,204001d0 +20400200: fe842783 lw a5,-24(s0) +20400204: 00078513 mv a0,a5 +20400208: 02c12083 lw ra,44(sp) +2040020c: 02812403 lw s0,40(sp) +20400210: 03010113 addi sp,sp,48 +20400214: 00008067 ret + +20400218 : +20400218: fd010113 addi sp,sp,-48 +2040021c: 02812623 sw s0,44(sp) +20400220: 03010413 addi s0,sp,48 +20400224: fca42e23 sw a0,-36(s0) +20400228: fe042623 sw zero,-20(s0) +2040022c: 00100793 li a5,1 +20400230: fef40423 sb a5,-24(s0) +20400234: fdc42783 lw a5,-36(s0) +20400238: 0ff7f793 andi a5,a5,255 +2040023c: 00479793 slli a5,a5,0x4 +20400240: 0ff7f793 andi a5,a5,255 +20400244: 0707f793 andi a5,a5,112 +20400248: 0ff7f793 andi a5,a5,255 +2040024c: f807e793 ori a5,a5,-128 +20400250: 0ff7f793 andi a5,a5,255 +20400254: fef404a3 sb a5,-23(s0) +20400258: fe040523 sb zero,-22(s0) +2040025c: 100127b7 lui a5,0x10012 +20400260: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +20400264: 0007a703 lw a4,0(a5) +20400268: 100127b7 lui a5,0x10012 +2040026c: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +20400270: fc377713 andi a4,a4,-61 +20400274: 00e7a023 sw a4,0(a5) +20400278: 100127b7 lui a5,0x10012 +2040027c: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20400280: 0007a703 lw a4,0(a5) +20400284: 100127b7 lui a5,0x10012 +20400288: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +2040028c: 03c76713 ori a4,a4,60 +20400290: 00e7a023 sw a4,0(a5) +20400294: 100247b7 lui a5,0x10024 +20400298: 04078793 addi a5,a5,64 # 10024040 <__stack_size+0x10023840> +2040029c: 00080737 lui a4,0x80 +204002a0: 00e7a023 sw a4,0(a5) +204002a4: 100247b7 lui a5,0x10024 +204002a8: 01078793 addi a5,a5,16 # 10024010 <__stack_size+0x10023810> +204002ac: 0007a023 sw zero,0(a5) +204002b0: 100247b7 lui a5,0x10024 +204002b4: 01478793 addi a5,a5,20 # 10024014 <__stack_size+0x10023814> +204002b8: 00010737 lui a4,0x10 +204002bc: fff70713 addi a4,a4,-1 # ffff <__stack_size+0xf7ff> +204002c0: 00e7a023 sw a4,0(a5) +204002c4: 100247b7 lui a5,0x10024 +204002c8: 00700713 li a4,7 +204002cc: 00e7a023 sw a4,0(a5) # 10024000 <__stack_size+0x10023800> +204002d0: 100247b7 lui a5,0x10024 +204002d4: 00478793 addi a5,a5,4 # 10024004 <__stack_size+0x10023804> +204002d8: 00300713 li a4,3 +204002dc: 00e7a023 sw a4,0(a5) +204002e0: 100247b7 lui a5,0x10024 +204002e4: 01878793 addi a5,a5,24 # 10024018 <__stack_size+0x10023818> +204002e8: 00200713 li a4,2 +204002ec: 00e7a023 sw a4,0(a5) +204002f0: 00000013 nop +204002f4: 100247b7 lui a5,0x10024 +204002f8: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +204002fc: 0007a783 lw a5,0(a5) +20400300: fe07cae3 bltz a5,204002f4 +20400304: fe844703 lbu a4,-24(s0) +20400308: 100247b7 lui a5,0x10024 +2040030c: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400310: 00e7a023 sw a4,0(a5) +20400314: 00000013 nop +20400318: 100247b7 lui a5,0x10024 +2040031c: 04c78793 addi a5,a5,76 # 1002404c <__stack_size+0x1002384c> +20400320: 0007a783 lw a5,0(a5) +20400324: fef42223 sw a5,-28(s0) +20400328: fe07c8e3 bltz a5,20400318 +2040032c: 00000013 nop +20400330: 100247b7 lui a5,0x10024 +20400334: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400338: 0007a783 lw a5,0(a5) +2040033c: fe07cae3 bltz a5,20400330 +20400340: fe944703 lbu a4,-23(s0) +20400344: 100247b7 lui a5,0x10024 +20400348: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +2040034c: 00e7a023 sw a4,0(a5) +20400350: 00000013 nop +20400354: 100247b7 lui a5,0x10024 +20400358: 04c78793 addi a5,a5,76 # 1002404c <__stack_size+0x1002384c> +2040035c: 0007a783 lw a5,0(a5) +20400360: fef42223 sw a5,-28(s0) +20400364: fe07c8e3 bltz a5,20400354 +20400368: fe442783 lw a5,-28(s0) +2040036c: 00879793 slli a5,a5,0x8 +20400370: 00078713 mv a4,a5 +20400374: 000107b7 lui a5,0x10 +20400378: f0078793 addi a5,a5,-256 # ff00 <__stack_size+0xf700> +2040037c: 00f777b3 and a5,a4,a5 +20400380: fef42623 sw a5,-20(s0) +20400384: 00000013 nop +20400388: 100247b7 lui a5,0x10024 +2040038c: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400390: 0007a783 lw a5,0(a5) +20400394: fe07cae3 bltz a5,20400388 +20400398: fea44703 lbu a4,-22(s0) +2040039c: 100247b7 lui a5,0x10024 +204003a0: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +204003a4: 00e7a023 sw a4,0(a5) +204003a8: 00000013 nop +204003ac: 100247b7 lui a5,0x10024 +204003b0: 04c78793 addi a5,a5,76 # 1002404c <__stack_size+0x1002384c> +204003b4: 0007a783 lw a5,0(a5) +204003b8: fef42223 sw a5,-28(s0) +204003bc: fe07c8e3 bltz a5,204003ac +204003c0: fe442783 lw a5,-28(s0) +204003c4: 0ff7f793 andi a5,a5,255 +204003c8: 00078713 mv a4,a5 +204003cc: fec42783 lw a5,-20(s0) +204003d0: 00e787b3 add a5,a5,a4 +204003d4: fef42623 sw a5,-20(s0) +204003d8: 100247b7 lui a5,0x10024 +204003dc: 01878793 addi a5,a5,24 # 10024018 <__stack_size+0x10023818> +204003e0: 0007a023 sw zero,0(a5) +204003e4: fec42783 lw a5,-20(s0) +204003e8: 3ff7f793 andi a5,a5,1023 +204003ec: 00078513 mv a0,a5 +204003f0: 02c12403 lw s0,44(sp) +204003f4: 03010113 addi sp,sp,48 +204003f8: 00008067 ret + +204003fc
: +204003fc: fe010113 addi sp,sp,-32 +20400400: 00112e23 sw ra,28(sp) +20400404: 00812c23 sw s0,24(sp) +20400408: 02010413 addi s0,sp,32 +2040040c: 000057b7 lui a5,0x5 +20400410: 5aa78593 addi a1,a5,1450 # 55aa <__stack_size+0x4daa> +20400414: 00100513 li a0,1 +20400418: 200010ef jal ra,20401618 +2040041c: 00a00513 li a0,10 +20400420: d89ff0ef jal ra,204001a8 +20400424: 00050793 mv a5,a0 +20400428: fef42423 sw a5,-24(s0) +2040042c: fe842783 lw a5,-24(s0) +20400430: 00078593 mv a1,a5 +20400434: 204027b7 lui a5,0x20402 +20400438: 29078513 addi a0,a5,656 # 20402290 <__clzsi2+0x4c> +2040043c: 0d1000ef jal ra,20400d0c <__wrap_printf> +20400440: fe042623 sw zero,-20(s0) +20400444: 0300006f j 20400474 +20400448: fec42503 lw a0,-20(s0) +2040044c: dcdff0ef jal ra,20400218 +20400450: 00050793 mv a5,a0 +20400454: 00078613 mv a2,a5 +20400458: fec42583 lw a1,-20(s0) +2040045c: 204027b7 lui a5,0x20402 +20400460: 2a478513 addi a0,a5,676 # 204022a4 <__clzsi2+0x60> +20400464: 0a9000ef jal ra,20400d0c <__wrap_printf> +20400468: fec42783 lw a5,-20(s0) +2040046c: 00178793 addi a5,a5,1 +20400470: fef42623 sw a5,-20(s0) +20400474: fec42703 lw a4,-20(s0) +20400478: 00700793 li a5,7 +2040047c: fce7f6e3 bleu a4,a5,20400448 +20400480: 204027b7 lui a5,0x20402 +20400484: 2bc78513 addi a0,a5,700 # 204022bc <__clzsi2+0x78> +20400488: 085000ef jal ra,20400d0c <__wrap_printf> +2040048c: 00000793 li a5,0 +20400490: 00078513 mv a0,a5 +20400494: 01c12083 lw ra,28(sp) +20400498: 01812403 lw s0,24(sp) +2040049c: 02010113 addi sp,sp,32 +204004a0: 00008067 ret + +204004a4 : +204004a4: fe010113 addi sp,sp,-32 +204004a8: 00112e23 sw ra,28(sp) +204004ac: 00812c23 sw s0,24(sp) +204004b0: 02010413 addi s0,sp,32 +204004b4: fea42623 sw a0,-20(s0) +204004b8: fec40793 addi a5,s0,-20 +204004bc: 00100613 li a2,1 +204004c0: 00078593 mv a1,a5 +204004c4: 00100513 li a0,1 +204004c8: 785000ef jal ra,2040144c <__wrap_write> +204004cc: 00050713 mv a4,a0 +204004d0: 00100793 li a5,1 +204004d4: 00f71663 bne a4,a5,204004e0 +204004d8: fec42783 lw a5,-20(s0) +204004dc: 0080006f j 204004e4 +204004e0: fff00793 li a5,-1 +204004e4: 00078513 mv a0,a5 +204004e8: 01c12083 lw ra,28(sp) +204004ec: 01812403 lw s0,24(sp) +204004f0: 02010113 addi sp,sp,32 +204004f4: 00008067 ret + +204004f8 : +204004f8: fd010113 addi sp,sp,-48 +204004fc: 02812623 sw s0,44(sp) +20400500: 03010413 addi s0,sp,48 +20400504: fca42e23 sw a0,-36(s0) +20400508: fcb42c23 sw a1,-40(s0) +2040050c: fd842783 lw a5,-40(s0) +20400510: fef42623 sw a5,-20(s0) +20400514: fec42783 lw a5,-20(s0) +20400518: 0007a783 lw a5,0(a5) +2040051c: fdc42703 lw a4,-36(s0) +20400520: 0ff77713 andi a4,a4,255 +20400524: 00e78023 sb a4,0(a5) +20400528: fec42783 lw a5,-20(s0) +2040052c: 0007a783 lw a5,0(a5) +20400530: 00178713 addi a4,a5,1 +20400534: fec42783 lw a5,-20(s0) +20400538: 00e7a023 sw a4,0(a5) +2040053c: 00000013 nop +20400540: 02c12403 lw s0,44(sp) +20400544: 03010113 addi sp,sp,48 +20400548: 00008067 ret + +2040054c : +2040054c: fe010113 addi sp,sp,-32 +20400550: 00812e23 sw s0,28(sp) +20400554: 02010413 addi s0,sp,32 +20400558: fea42623 sw a0,-20(s0) +2040055c: feb42423 sw a1,-24(s0) +20400560: fe842783 lw a5,-24(s0) +20400564: 02078063 beqz a5,20400584 +20400568: fec42783 lw a5,-20(s0) +2040056c: 0007a783 lw a5,0(a5) +20400570: 00478693 addi a3,a5,4 +20400574: fec42703 lw a4,-20(s0) +20400578: 00d72023 sw a3,0(a4) +2040057c: 0007a783 lw a5,0(a5) +20400580: 01c0006f j 2040059c +20400584: fec42783 lw a5,-20(s0) +20400588: 0007a783 lw a5,0(a5) +2040058c: 00478693 addi a3,a5,4 +20400590: fec42703 lw a4,-20(s0) +20400594: 00d72023 sw a3,0(a4) +20400598: 0007a783 lw a5,0(a5) +2040059c: 00078513 mv a0,a5 +204005a0: 01c12403 lw s0,28(sp) +204005a4: 02010113 addi sp,sp,32 +204005a8: 00008067 ret + +204005ac : +204005ac: fe010113 addi sp,sp,-32 +204005b0: 00812e23 sw s0,28(sp) +204005b4: 02010413 addi s0,sp,32 +204005b8: fea42623 sw a0,-20(s0) +204005bc: feb42423 sw a1,-24(s0) +204005c0: fe842783 lw a5,-24(s0) +204005c4: 02078063 beqz a5,204005e4 +204005c8: fec42783 lw a5,-20(s0) +204005cc: 0007a783 lw a5,0(a5) +204005d0: 00478693 addi a3,a5,4 +204005d4: fec42703 lw a4,-20(s0) +204005d8: 00d72023 sw a3,0(a4) +204005dc: 0007a783 lw a5,0(a5) +204005e0: 01c0006f j 204005fc +204005e4: fec42783 lw a5,-20(s0) +204005e8: 0007a783 lw a5,0(a5) +204005ec: 00478693 addi a3,a5,4 +204005f0: fec42703 lw a4,-20(s0) +204005f4: 00d72023 sw a3,0(a4) +204005f8: 0007a783 lw a5,0(a5) +204005fc: 00078513 mv a0,a5 +20400600: 01c12403 lw s0,28(sp) +20400604: 02010113 addi sp,sp,32 +20400608: 00008067 ret + +2040060c : +2040060c: f4010113 addi sp,sp,-192 +20400610: 0a112e23 sw ra,188(sp) +20400614: 0a812c23 sw s0,184(sp) +20400618: 0a912a23 sw s1,180(sp) +2040061c: 0c010413 addi s0,sp,192 +20400620: f4a42e23 sw a0,-164(s0) +20400624: f4b42c23 sw a1,-168(s0) +20400628: f4c42a23 sw a2,-172(s0) +2040062c: f4d42823 sw a3,-176(s0) +20400630: f4e42623 sw a4,-180(s0) +20400634: f4f42423 sw a5,-184(s0) +20400638: fe042623 sw zero,-20(s0) +2040063c: fec42483 lw s1,-20(s0) +20400640: 00148793 addi a5,s1,1 +20400644: fef42623 sw a5,-20(s0) +20400648: f5442783 lw a5,-172(s0) +2040064c: f5042583 lw a1,-176(s0) +20400650: 00078513 mv a0,a5 +20400654: 38d010ef jal ra,204021e0 <__umodsi3> +20400658: 00050793 mv a5,a0 +2040065c: 00078713 mv a4,a5 +20400660: 00249793 slli a5,s1,0x2 +20400664: ff040693 addi a3,s0,-16 +20400668: 00f687b3 add a5,a3,a5 +2040066c: f6e7ae23 sw a4,-132(a5) +20400670: f5442703 lw a4,-172(s0) +20400674: f5042783 lw a5,-176(s0) +20400678: 00f76e63 bltu a4,a5,20400694 +2040067c: f5042583 lw a1,-176(s0) +20400680: f5442503 lw a0,-172(s0) +20400684: 315010ef jal ra,20402198 <__udivsi3> +20400688: 00050793 mv a5,a0 +2040068c: f4f42a23 sw a5,-172(s0) +20400690: fadff06f j 2040063c +20400694: 00000013 nop +20400698: 0140006f j 204006ac +2040069c: f5c42783 lw a5,-164(s0) +204006a0: f5842583 lw a1,-168(s0) +204006a4: f4842503 lw a0,-184(s0) +204006a8: 000780e7 jalr a5 +204006ac: f4c42783 lw a5,-180(s0) +204006b0: fff78713 addi a4,a5,-1 +204006b4: f4e42623 sw a4,-180(s0) +204006b8: fec42703 lw a4,-20(s0) +204006bc: fef740e3 blt a4,a5,2040069c +204006c0: 0540006f j 20400714 +204006c4: fec42783 lw a5,-20(s0) +204006c8: 00279793 slli a5,a5,0x2 +204006cc: ff040713 addi a4,s0,-16 +204006d0: 00f707b3 add a5,a4,a5 +204006d4: f7c7a703 lw a4,-132(a5) +204006d8: fec42783 lw a5,-20(s0) +204006dc: 00279793 slli a5,a5,0x2 +204006e0: ff040693 addi a3,s0,-16 +204006e4: 00f687b3 add a5,a3,a5 +204006e8: f7c7a683 lw a3,-132(a5) +204006ec: 00900793 li a5,9 +204006f0: 00d7f663 bleu a3,a5,204006fc +204006f4: 05700793 li a5,87 +204006f8: 0080006f j 20400700 +204006fc: 03000793 li a5,48 +20400700: 00e787b3 add a5,a5,a4 +20400704: f5c42703 lw a4,-164(s0) +20400708: f5842583 lw a1,-168(s0) +2040070c: 00078513 mv a0,a5 +20400710: 000700e7 jalr a4 +20400714: fec42783 lw a5,-20(s0) +20400718: fff78713 addi a4,a5,-1 +2040071c: fee42623 sw a4,-20(s0) +20400720: faf042e3 bgtz a5,204006c4 +20400724: 00000013 nop +20400728: 0bc12083 lw ra,188(sp) +2040072c: 0b812403 lw s0,184(sp) +20400730: 0b412483 lw s1,180(sp) +20400734: 0c010113 addi sp,sp,192 +20400738: 00008067 ret + +2040073c : +2040073c: f9010113 addi sp,sp,-112 +20400740: 06112623 sw ra,108(sp) +20400744: 06812423 sw s0,104(sp) +20400748: 07212223 sw s2,100(sp) +2040074c: 07312023 sw s3,96(sp) +20400750: 07010413 addi s0,sp,112 +20400754: faa42623 sw a0,-84(s0) +20400758: fab42423 sw a1,-88(s0) +2040075c: fac42023 sw a2,-96(s0) +20400760: fad42223 sw a3,-92(s0) +20400764: f8e42e23 sw a4,-100(s0) +20400768: f8f42c23 sw a5,-104(s0) +2040076c: fa042783 lw a5,-96(s0) +20400770: fa442803 lw a6,-92(s0) +20400774: fcf42c23 sw a5,-40(s0) +20400778: fd042e23 sw a6,-36(s0) +2040077c: fd842783 lw a5,-40(s0) +20400780: fdc42803 lw a6,-36(s0) +20400784: 00080793 mv a5,a6 +20400788: 0207da63 bgez a5,204007bc +2040078c: fac42783 lw a5,-84(s0) +20400790: fa842583 lw a1,-88(s0) +20400794: 02d00513 li a0,45 +20400798: 000780e7 jalr a5 +2040079c: fd842783 lw a5,-40(s0) +204007a0: fdc42803 lw a6,-36(s0) +204007a4: fff7f913 andi s2,a5,-1 +204007a8: 80000737 lui a4,0x80000 +204007ac: fff74713 not a4,a4 +204007b0: 00e879b3 and s3,a6,a4 +204007b4: fd242c23 sw s2,-40(s0) +204007b8: fd342e23 sw s3,-36(s0) +204007bc: fe042623 sw zero,-20(s0) +204007c0: 0400006f j 20400800 +204007c4: fd842783 lw a5,-40(s0) +204007c8: fdc42803 lw a6,-36(s0) +204007cc: 20402737 lui a4,0x20402 +204007d0: 43072603 lw a2,1072(a4) # 20402430 <__clzsi2+0x1ec> +204007d4: 43472683 lw a3,1076(a4) +204007d8: 00078513 mv a0,a5 +204007dc: 00080593 mv a1,a6 +204007e0: 220010ef jal ra,20401a00 <__muldf3> +204007e4: 00050793 mv a5,a0 +204007e8: 00058813 mv a6,a1 +204007ec: fcf42c23 sw a5,-40(s0) +204007f0: fd042e23 sw a6,-36(s0) +204007f4: fec42783 lw a5,-20(s0) +204007f8: 00178793 addi a5,a5,1 +204007fc: fef42623 sw a5,-20(s0) +20400800: fec42703 lw a4,-20(s0) +20400804: f9842783 lw a5,-104(s0) +20400808: faf74ee3 blt a4,a5,204007c4 +2040080c: fb840793 addi a5,s0,-72 +20400810: faf42a23 sw a5,-76(s0) +20400814: fd842783 lw a5,-40(s0) +20400818: fdc42803 lw a6,-36(s0) +2040081c: 00078513 mv a0,a5 +20400820: 00080593 mv a1,a6 +20400824: 0cd010ef jal ra,204020f0 <__fixunsdfsi> +20400828: 00050613 mv a2,a0 +2040082c: fb440593 addi a1,s0,-76 +20400830: 00000793 li a5,0 +20400834: 00000713 li a4,0 +20400838: 00a00693 li a3,10 +2040083c: 20400537 lui a0,0x20400 +20400840: 4f850513 addi a0,a0,1272 # 204004f8 +20400844: dc9ff0ef jal ra,2040060c +20400848: f9842783 lw a5,-104(s0) +2040084c: 06f05863 blez a5,204008bc +20400850: fe042423 sw zero,-24(s0) +20400854: 0380006f j 2040088c +20400858: fb442703 lw a4,-76(s0) +2040085c: fe842783 lw a5,-24(s0) +20400860: fff7c793 not a5,a5 +20400864: 00f70733 add a4,a4,a5 +20400868: fb442783 lw a5,-76(s0) +2040086c: fe842683 lw a3,-24(s0) +20400870: 40d006b3 neg a3,a3 +20400874: 00d787b3 add a5,a5,a3 +20400878: 00074703 lbu a4,0(a4) +2040087c: 00e78023 sb a4,0(a5) +20400880: fe842783 lw a5,-24(s0) +20400884: 00178793 addi a5,a5,1 +20400888: fef42423 sw a5,-24(s0) +2040088c: fe842703 lw a4,-24(s0) +20400890: f9842783 lw a5,-104(s0) +20400894: fcf742e3 blt a4,a5,20400858 +20400898: fb442783 lw a5,-76(s0) +2040089c: f9842703 lw a4,-104(s0) +204008a0: 40e00733 neg a4,a4 +204008a4: 00e787b3 add a5,a5,a4 +204008a8: 02e00713 li a4,46 +204008ac: 00e78023 sb a4,0(a5) +204008b0: fb442783 lw a5,-76(s0) +204008b4: 00178793 addi a5,a5,1 +204008b8: faf42a23 sw a5,-76(s0) +204008bc: fb840793 addi a5,s0,-72 +204008c0: fef42223 sw a5,-28(s0) +204008c4: 0280006f j 204008ec +204008c8: fe442783 lw a5,-28(s0) +204008cc: 0007c783 lbu a5,0(a5) +204008d0: fac42703 lw a4,-84(s0) +204008d4: fa842583 lw a1,-88(s0) +204008d8: 00078513 mv a0,a5 +204008dc: 000700e7 jalr a4 +204008e0: fe442783 lw a5,-28(s0) +204008e4: 00178793 addi a5,a5,1 +204008e8: fef42223 sw a5,-28(s0) +204008ec: fb442783 lw a5,-76(s0) +204008f0: fe442703 lw a4,-28(s0) +204008f4: fcf76ae3 bltu a4,a5,204008c8 +204008f8: 00000013 nop +204008fc: 06c12083 lw ra,108(sp) +20400900: 06812403 lw s0,104(sp) +20400904: 06412903 lw s2,100(sp) +20400908: 06012983 lw s3,96(sp) +2040090c: 07010113 addi sp,sp,112 +20400910: 00008067 ret + +20400914 : +20400914: fc010113 addi sp,sp,-64 +20400918: 02112e23 sw ra,60(sp) +2040091c: 02812c23 sw s0,56(sp) +20400920: 02912a23 sw s1,52(sp) +20400924: 03212823 sw s2,48(sp) +20400928: 04010413 addi s0,sp,64 +2040092c: fca42623 sw a0,-52(s0) +20400930: fcb42423 sw a1,-56(s0) +20400934: fcc42223 sw a2,-60(s0) +20400938: fcd42023 sw a3,-64(s0) +2040093c: 0240006f j 20400960 +20400940: 3a048863 beqz s1,20400cf0 +20400944: fc442783 lw a5,-60(s0) +20400948: 00178793 addi a5,a5,1 +2040094c: fcf42223 sw a5,-60(s0) +20400950: fcc42783 lw a5,-52(s0) +20400954: fc842583 lw a1,-56(s0) +20400958: 00048513 mv a0,s1 +2040095c: 000780e7 jalr a5 +20400960: fc442783 lw a5,-60(s0) +20400964: 0007c783 lbu a5,0(a5) +20400968: 00078493 mv s1,a5 +2040096c: 02500793 li a5,37 +20400970: fcf498e3 bne s1,a5,20400940 +20400974: fc442783 lw a5,-60(s0) +20400978: 00178793 addi a5,a5,1 +2040097c: fcf42223 sw a5,-60(s0) +20400980: fc442783 lw a5,-60(s0) +20400984: fcf42a23 sw a5,-44(s0) +20400988: 02000793 li a5,32 +2040098c: fcf40da3 sb a5,-37(s0) +20400990: fff00793 li a5,-1 +20400994: fef42023 sw a5,-32(s0) +20400998: fff00793 li a5,-1 +2040099c: fcf42e23 sw a5,-36(s0) +204009a0: fe042223 sw zero,-28(s0) +204009a4: fc042823 sw zero,-48(s0) +204009a8: fc442783 lw a5,-60(s0) +204009ac: 00178713 addi a4,a5,1 +204009b0: fce42223 sw a4,-60(s0) +204009b4: 0007c783 lbu a5,0(a5) +204009b8: 00078493 mv s1,a5 +204009bc: fdd48793 addi a5,s1,-35 +204009c0: 05500713 li a4,85 +204009c4: 30f76663 bltu a4,a5,20400cd0 +204009c8: 00279713 slli a4,a5,0x2 +204009cc: 204027b7 lui a5,0x20402 +204009d0: 2d878793 addi a5,a5,728 # 204022d8 <__clzsi2+0x94> +204009d4: 00f707b3 add a5,a4,a5 +204009d8: 0007a783 lw a5,0(a5) +204009dc: 00078067 jr a5 +204009e0: 02d00793 li a5,45 +204009e4: fcf40da3 sb a5,-37(s0) +204009e8: fc1ff06f j 204009a8 +204009ec: 03000793 li a5,48 +204009f0: fcf40da3 sb a5,-37(s0) +204009f4: fb5ff06f j 204009a8 +204009f8: fc042e23 sw zero,-36(s0) +204009fc: fdc42703 lw a4,-36(s0) +20400a00: 00070793 mv a5,a4 +20400a04: 00279793 slli a5,a5,0x2 +20400a08: 00e787b3 add a5,a5,a4 +20400a0c: 00179793 slli a5,a5,0x1 +20400a10: 00f487b3 add a5,s1,a5 +20400a14: fd078793 addi a5,a5,-48 +20400a18: fcf42e23 sw a5,-36(s0) +20400a1c: fc442783 lw a5,-60(s0) +20400a20: 0007c783 lbu a5,0(a5) +20400a24: 00078493 mv s1,a5 +20400a28: 02f00793 li a5,47 +20400a2c: 0497d863 ble s1,a5,20400a7c +20400a30: 03900793 li a5,57 +20400a34: 0497c463 blt a5,s1,20400a7c +20400a38: fc442783 lw a5,-60(s0) +20400a3c: 00178793 addi a5,a5,1 +20400a40: fcf42223 sw a5,-60(s0) +20400a44: fb9ff06f j 204009fc +20400a48: fc042783 lw a5,-64(s0) +20400a4c: 00478713 addi a4,a5,4 +20400a50: fce42023 sw a4,-64(s0) +20400a54: 0007a783 lw a5,0(a5) +20400a58: fcf42e23 sw a5,-36(s0) +20400a5c: 0240006f j 20400a80 +20400a60: fe042783 lw a5,-32(s0) +20400a64: f407d2e3 bgez a5,204009a8 +20400a68: fe042023 sw zero,-32(s0) +20400a6c: f3dff06f j 204009a8 +20400a70: 00100793 li a5,1 +20400a74: fcf42823 sw a5,-48(s0) +20400a78: f31ff06f j 204009a8 +20400a7c: 00000013 nop +20400a80: fe042783 lw a5,-32(s0) +20400a84: f207d2e3 bgez a5,204009a8 +20400a88: fdc42783 lw a5,-36(s0) +20400a8c: fef42023 sw a5,-32(s0) +20400a90: fff00793 li a5,-1 +20400a94: fcf42e23 sw a5,-36(s0) +20400a98: f11ff06f j 204009a8 +20400a9c: fe442783 lw a5,-28(s0) +20400aa0: 22079663 bnez a5,20400ccc +20400aa4: f05ff06f j 204009a8 +20400aa8: fc042783 lw a5,-64(s0) +20400aac: 00478713 addi a4,a5,4 +20400ab0: fce42023 sw a4,-64(s0) +20400ab4: 0007a783 lw a5,0(a5) +20400ab8: fcc42703 lw a4,-52(s0) +20400abc: fc842583 lw a1,-56(s0) +20400ac0: 00078513 mv a0,a5 +20400ac4: 000700e7 jalr a4 +20400ac8: 2240006f j 20400cec +20400acc: fc042783 lw a5,-64(s0) +20400ad0: 00778793 addi a5,a5,7 +20400ad4: ff87f793 andi a5,a5,-8 +20400ad8: 00878713 addi a4,a5,8 +20400adc: fce42023 sw a4,-64(s0) +20400ae0: 0007a603 lw a2,0(a5) +20400ae4: 0047a683 lw a3,4(a5) +20400ae8: fdc42783 lw a5,-36(s0) +20400aec: fe042703 lw a4,-32(s0) +20400af0: fc842583 lw a1,-56(s0) +20400af4: fcc42503 lw a0,-52(s0) +20400af8: c45ff0ef jal ra,2040073c +20400afc: 1f00006f j 20400cec +20400b00: fc042783 lw a5,-64(s0) +20400b04: 00478713 addi a4,a5,4 +20400b08: fce42023 sw a4,-64(s0) +20400b0c: 0007a903 lw s2,0(a5) +20400b10: 00091663 bnez s2,20400b1c +20400b14: 204027b7 lui a5,0x20402 +20400b18: 2d078913 addi s2,a5,720 # 204022d0 <__clzsi2+0x8c> +20400b1c: fe042783 lw a5,-32(s0) +20400b20: 08f05063 blez a5,20400ba0 +20400b24: fdb44703 lbu a4,-37(s0) +20400b28: 02d00793 li a5,45 +20400b2c: 06f70a63 beq a4,a5,20400ba0 +20400b30: fdc42783 lw a5,-36(s0) +20400b34: 00078593 mv a1,a5 +20400b38: 00090513 mv a0,s2 +20400b3c: 509000ef jal ra,20401844 +20400b40: 00050713 mv a4,a0 +20400b44: fe042783 lw a5,-32(s0) +20400b48: 40e787b3 sub a5,a5,a4 +20400b4c: fef42023 sw a5,-32(s0) +20400b50: 0240006f j 20400b74 +20400b54: fdb44783 lbu a5,-37(s0) +20400b58: fcc42703 lw a4,-52(s0) +20400b5c: fc842583 lw a1,-56(s0) +20400b60: 00078513 mv a0,a5 +20400b64: 000700e7 jalr a4 +20400b68: fe042783 lw a5,-32(s0) +20400b6c: fff78793 addi a5,a5,-1 +20400b70: fef42023 sw a5,-32(s0) +20400b74: fe042783 lw a5,-32(s0) +20400b78: fcf04ee3 bgtz a5,20400b54 +20400b7c: 0240006f j 20400ba0 +20400b80: fcc42783 lw a5,-52(s0) +20400b84: fc842583 lw a1,-56(s0) +20400b88: 00048513 mv a0,s1 +20400b8c: 000780e7 jalr a5 +20400b90: 00190913 addi s2,s2,1 +20400b94: fe042783 lw a5,-32(s0) +20400b98: fff78793 addi a5,a5,-1 +20400b9c: fef42023 sw a5,-32(s0) +20400ba0: 00094783 lbu a5,0(s2) +20400ba4: 00078493 mv s1,a5 +20400ba8: 04048063 beqz s1,20400be8 +20400bac: fdc42783 lw a5,-36(s0) +20400bb0: fc07c8e3 bltz a5,20400b80 +20400bb4: fdc42783 lw a5,-36(s0) +20400bb8: fff78793 addi a5,a5,-1 +20400bbc: fcf42e23 sw a5,-36(s0) +20400bc0: fdc42783 lw a5,-36(s0) +20400bc4: fa07dee3 bgez a5,20400b80 +20400bc8: 0200006f j 20400be8 +20400bcc: fcc42783 lw a5,-52(s0) +20400bd0: fc842583 lw a1,-56(s0) +20400bd4: 02000513 li a0,32 +20400bd8: 000780e7 jalr a5 +20400bdc: fe042783 lw a5,-32(s0) +20400be0: fff78793 addi a5,a5,-1 +20400be4: fef42023 sw a5,-32(s0) +20400be8: fe042783 lw a5,-32(s0) +20400bec: fef040e3 bgtz a5,20400bcc +20400bf0: 0fc0006f j 20400cec +20400bf4: fc040793 addi a5,s0,-64 +20400bf8: fe442583 lw a1,-28(s0) +20400bfc: 00078513 mv a0,a5 +20400c00: 9adff0ef jal ra,204005ac +20400c04: 00050793 mv a5,a0 +20400c08: fef42623 sw a5,-20(s0) +20400c0c: fec42783 lw a5,-20(s0) +20400c10: 0207d063 bgez a5,20400c30 +20400c14: fcc42783 lw a5,-52(s0) +20400c18: fc842583 lw a1,-56(s0) +20400c1c: 02d00513 li a0,45 +20400c20: 000780e7 jalr a5 +20400c24: fec42783 lw a5,-20(s0) +20400c28: 40f007b3 neg a5,a5 +20400c2c: fef42623 sw a5,-20(s0) +20400c30: 00a00793 li a5,10 +20400c34: fef42423 sw a5,-24(s0) +20400c38: 0600006f j 20400c98 +20400c3c: 00a00793 li a5,10 +20400c40: fef42423 sw a5,-24(s0) +20400c44: 0400006f j 20400c84 +20400c48: 00800793 li a5,8 +20400c4c: fef42423 sw a5,-24(s0) +20400c50: 0340006f j 20400c84 +20400c54: 00100793 li a5,1 +20400c58: fef42223 sw a5,-28(s0) +20400c5c: fcc42783 lw a5,-52(s0) +20400c60: fc842583 lw a1,-56(s0) +20400c64: 03000513 li a0,48 +20400c68: 000780e7 jalr a5 +20400c6c: fcc42783 lw a5,-52(s0) +20400c70: fc842583 lw a1,-56(s0) +20400c74: 07800513 li a0,120 +20400c78: 000780e7 jalr a5 +20400c7c: 01000793 li a5,16 +20400c80: fef42423 sw a5,-24(s0) +20400c84: fc040793 addi a5,s0,-64 +20400c88: fe442583 lw a1,-28(s0) +20400c8c: 00078513 mv a0,a5 +20400c90: 8bdff0ef jal ra,2040054c +20400c94: fea42623 sw a0,-20(s0) +20400c98: fe842683 lw a3,-24(s0) +20400c9c: fdb44783 lbu a5,-37(s0) +20400ca0: fe042703 lw a4,-32(s0) +20400ca4: fec42603 lw a2,-20(s0) +20400ca8: fc842583 lw a1,-56(s0) +20400cac: fcc42503 lw a0,-52(s0) +20400cb0: 95dff0ef jal ra,2040060c +20400cb4: 0380006f j 20400cec +20400cb8: fcc42783 lw a5,-52(s0) +20400cbc: fc842583 lw a1,-56(s0) +20400cc0: 00048513 mv a0,s1 +20400cc4: 000780e7 jalr a5 +20400cc8: 0240006f j 20400cec +20400ccc: 00000013 nop +20400cd0: fcc42783 lw a5,-52(s0) +20400cd4: fc842583 lw a1,-56(s0) +20400cd8: 02500513 li a0,37 +20400cdc: 000780e7 jalr a5 +20400ce0: fd442783 lw a5,-44(s0) +20400ce4: fcf42223 sw a5,-60(s0) +20400ce8: 00000013 nop +20400cec: c75ff06f j 20400960 +20400cf0: 00000013 nop +20400cf4: 03c12083 lw ra,60(sp) +20400cf8: 03812403 lw s0,56(sp) +20400cfc: 03412483 lw s1,52(sp) +20400d00: 03012903 lw s2,48(sp) +20400d04: 04010113 addi sp,sp,64 +20400d08: 00008067 ret + +20400d0c <__wrap_printf>: +20400d0c: fb010113 addi sp,sp,-80 +20400d10: 02112623 sw ra,44(sp) +20400d14: 02812423 sw s0,40(sp) +20400d18: 03010413 addi s0,sp,48 +20400d1c: fca42e23 sw a0,-36(s0) +20400d20: 00b42223 sw a1,4(s0) +20400d24: 00c42423 sw a2,8(s0) +20400d28: 00d42623 sw a3,12(s0) +20400d2c: 00e42823 sw a4,16(s0) +20400d30: 00f42a23 sw a5,20(s0) +20400d34: 01042c23 sw a6,24(s0) +20400d38: 01142e23 sw a7,28(s0) +20400d3c: 02040793 addi a5,s0,32 +20400d40: fe478793 addi a5,a5,-28 +20400d44: fef42623 sw a5,-20(s0) +20400d48: fec42783 lw a5,-20(s0) +20400d4c: 00078693 mv a3,a5 +20400d50: fdc42603 lw a2,-36(s0) +20400d54: 00000593 li a1,0 +20400d58: 204007b7 lui a5,0x20400 +20400d5c: 4a478513 addi a0,a5,1188 # 204004a4 +20400d60: bb5ff0ef jal ra,20400914 +20400d64: 00000793 li a5,0 +20400d68: 00078513 mv a0,a5 +20400d6c: 02c12083 lw ra,44(sp) +20400d70: 02812403 lw s0,40(sp) +20400d74: 05010113 addi sp,sp,80 +20400d78: 00008067 ret + +20400d7c <__wrap_sprintf>: +20400d7c: fb010113 addi sp,sp,-80 +20400d80: 02112623 sw ra,44(sp) +20400d84: 02812423 sw s0,40(sp) +20400d88: 03010413 addi s0,sp,48 +20400d8c: fca42e23 sw a0,-36(s0) +20400d90: fcb42c23 sw a1,-40(s0) +20400d94: 00c42423 sw a2,8(s0) +20400d98: 00d42623 sw a3,12(s0) +20400d9c: 00e42823 sw a4,16(s0) +20400da0: 00f42a23 sw a5,20(s0) +20400da4: 01042c23 sw a6,24(s0) +20400da8: 01142e23 sw a7,28(s0) +20400dac: fdc42783 lw a5,-36(s0) +20400db0: fef42623 sw a5,-20(s0) +20400db4: 02040793 addi a5,s0,32 +20400db8: fe878793 addi a5,a5,-24 +20400dbc: fef42423 sw a5,-24(s0) +20400dc0: fe842703 lw a4,-24(s0) +20400dc4: fdc40793 addi a5,s0,-36 +20400dc8: 00070693 mv a3,a4 +20400dcc: fd842603 lw a2,-40(s0) +20400dd0: 00078593 mv a1,a5 +20400dd4: 204007b7 lui a5,0x20400 +20400dd8: 4f878513 addi a0,a5,1272 # 204004f8 +20400ddc: b39ff0ef jal ra,20400914 +20400de0: fdc42783 lw a5,-36(s0) +20400de4: 00078023 sb zero,0(a5) +20400de8: fdc42783 lw a5,-36(s0) +20400dec: 00078713 mv a4,a5 +20400df0: fec42783 lw a5,-20(s0) +20400df4: 40f707b3 sub a5,a4,a5 +20400df8: 00078513 mv a0,a5 +20400dfc: 02c12083 lw ra,44(sp) +20400e00: 02812403 lw s0,40(sp) +20400e04: 05010113 addi sp,sp,80 +20400e08: 00008067 ret + +20400e0c : +20400e0c: ff010113 addi sp,sp,-16 +20400e10: 00812623 sw s0,12(sp) +20400e14: 01010413 addi s0,sp,16 +20400e18: 0200c7b7 lui a5,0x200c +20400e1c: ff878793 addi a5,a5,-8 # 200bff8 <__stack_size+0x200b7f8> +20400e20: 0007a783 lw a5,0(a5) +20400e24: 00078513 mv a0,a5 +20400e28: 00c12403 lw s0,12(sp) +20400e2c: 01010113 addi sp,sp,16 +20400e30: 00008067 ret + +20400e34 : +20400e34: ff010113 addi sp,sp,-16 +20400e38: 00112623 sw ra,12(sp) +20400e3c: 00812423 sw s0,8(sp) +20400e40: 01212223 sw s2,4(sp) +20400e44: 01312023 sw s3,0(sp) +20400e48: 01010413 addi s0,sp,16 +20400e4c: fc1ff0ef jal ra,20400e0c +20400e50: 00050793 mv a5,a0 +20400e54: 00078913 mv s2,a5 +20400e58: 00000993 li s3,0 +20400e5c: 00090793 mv a5,s2 +20400e60: 00098813 mv a6,s3 +20400e64: 00078513 mv a0,a5 +20400e68: 00080593 mv a1,a6 +20400e6c: 00c12083 lw ra,12(sp) +20400e70: 00812403 lw s0,8(sp) +20400e74: 00412903 lw s2,4(sp) +20400e78: 00012983 lw s3,0(sp) +20400e7c: 01010113 addi sp,sp,16 +20400e80: 00008067 ret + +20400e84 : +20400e84: ff010113 addi sp,sp,-16 +20400e88: 00812623 sw s0,12(sp) +20400e8c: 01010413 addi s0,sp,16 +20400e90: 000087b7 lui a5,0x8 +20400e94: 00078513 mv a0,a5 +20400e98: 00c12403 lw s0,12(sp) +20400e9c: 01010113 addi sp,sp,16 +20400ea0: 00008067 ret + +20400ea4 : +20400ea4: fe010113 addi sp,sp,-32 +20400ea8: 00812e23 sw s0,28(sp) +20400eac: 02010413 addi s0,sp,32 +20400eb0: fea42623 sw a0,-20(s0) +20400eb4: feb42423 sw a1,-24(s0) +20400eb8: fec42783 lw a5,-20(s0) +20400ebc: 02f7f713 andi a4,a5,47 +20400ec0: fe842783 lw a5,-24(s0) +20400ec4: 01079693 slli a3,a5,0x10 +20400ec8: 001f07b7 lui a5,0x1f0 +20400ecc: 00f6f7b3 and a5,a3,a5 +20400ed0: 00f76733 or a4,a4,a5 +20400ed4: 400007b7 lui a5,0x40000 +20400ed8: 00f76733 or a4,a4,a5 +20400edc: 100087b7 lui a5,0x10008 +20400ee0: 00e7a023 sw a4,0(a5) # 10008000 <__stack_size+0x10007800> +20400ee4: 00000013 nop +20400ee8: 100087b7 lui a5,0x10008 +20400eec: 0007a783 lw a5,0(a5) # 10008000 <__stack_size+0x10007800> +20400ef0: fe07dce3 bgez a5,20400ee8 +20400ef4: 100087b7 lui a5,0x10008 +20400ef8: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400efc: 0007a683 lw a3,0(a5) +20400f00: 100087b7 lui a5,0x10008 +20400f04: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400f08: ffff0737 lui a4,0xffff0 +20400f0c: fff70713 addi a4,a4,-1 # fffeffff <_sp+0x7ffebfff> +20400f10: 00e6f733 and a4,a3,a4 +20400f14: 00e7a023 sw a4,0(a5) +20400f18: 00000013 nop +20400f1c: 01c12403 lw s0,28(sp) +20400f20: 02010113 addi sp,sp,32 +20400f24: 00008067 ret + +20400f28 : +20400f28: fc010113 addi sp,sp,-64 +20400f2c: 02112e23 sw ra,60(sp) +20400f30: 02812c23 sw s0,56(sp) +20400f34: 04010413 addi s0,sp,64 +20400f38: fca42e23 sw a0,-36(s0) +20400f3c: fcb42c23 sw a1,-40(s0) +20400f40: fcc42a23 sw a2,-44(s0) +20400f44: fcd42823 sw a3,-48(s0) +20400f48: fce42623 sw a4,-52(s0) +20400f4c: 100087b7 lui a5,0x10008 +20400f50: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400f54: 0007a703 lw a4,0(a5) +20400f58: 000107b7 lui a5,0x10 +20400f5c: 00f777b3 and a5,a4,a5 +20400f60: 00078863 beqz a5,20400f70 +20400f64: 01000593 li a1,16 +20400f68: 00400513 li a0,4 +20400f6c: f39ff0ef jal ra,20400ea4 +20400f70: fe042623 sw zero,-20(s0) +20400f74: fdc42783 lw a5,-36(s0) +20400f78: 01179793 slli a5,a5,0x11 +20400f7c: 00078713 mv a4,a5 +20400f80: 000207b7 lui a5,0x20 +20400f84: 00f777b3 and a5,a4,a5 +20400f88: fec42703 lw a4,-20(s0) +20400f8c: 00f767b3 or a5,a4,a5 +20400f90: fef42623 sw a5,-20(s0) +20400f94: fd842783 lw a5,-40(s0) +20400f98: 02078c63 beqz a5,20400fd0 +20400f9c: fec42703 lw a4,-20(s0) +20400fa0: 000407b7 lui a5,0x40 +20400fa4: 00f767b3 or a5,a4,a5 +20400fa8: fef42623 sw a5,-20(s0) +20400fac: 100087b7 lui a5,0x10008 +20400fb0: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400fb4: fec42703 lw a4,-20(s0) +20400fb8: 00e7a023 sw a4,0(a5) +20400fbc: 100087b7 lui a5,0x10008 +20400fc0: 00c78793 addi a5,a5,12 # 1000800c <__stack_size+0x1000780c> +20400fc4: 10000713 li a4,256 +20400fc8: 00e7a023 sw a4,0(a5) +20400fcc: 0ec0006f j 204010b8 +20400fd0: 100147b7 lui a5,0x10014 +20400fd4: 00800713 li a4,8 +20400fd8: 00e7a023 sw a4,0(a5) # 10014000 <__stack_size+0x10013800> +20400fdc: fec42703 lw a4,-20(s0) +20400fe0: 000407b7 lui a5,0x40 +20400fe4: 00f767b3 or a5,a4,a5 +20400fe8: fef42623 sw a5,-20(s0) +20400fec: fd442783 lw a5,-44(s0) +20400ff0: 0077f793 andi a5,a5,7 +20400ff4: fec42703 lw a4,-20(s0) +20400ff8: 00f767b3 or a5,a4,a5 +20400ffc: fef42623 sw a5,-20(s0) +20401000: fd042783 lw a5,-48(s0) +20401004: 00479793 slli a5,a5,0x4 +20401008: 3f07f793 andi a5,a5,1008 +2040100c: fec42703 lw a4,-20(s0) +20401010: 00f767b3 or a5,a4,a5 +20401014: fef42623 sw a5,-20(s0) +20401018: fcc42783 lw a5,-52(s0) +2040101c: 00a79793 slli a5,a5,0xa +20401020: 00078713 mv a4,a5 +20401024: 000017b7 lui a5,0x1 +20401028: c0078793 addi a5,a5,-1024 # c00 <__stack_size+0x400> +2040102c: 00f777b3 and a5,a4,a5 +20401030: fec42703 lw a4,-20(s0) +20401034: 00f767b3 or a5,a4,a5 +20401038: fef42623 sw a5,-20(s0) +2040103c: 100087b7 lui a5,0x10008 +20401040: 00c78793 addi a5,a5,12 # 1000800c <__stack_size+0x1000780c> +20401044: 10000713 li a4,256 +20401048: 00e7a023 sw a4,0(a5) +2040104c: 100087b7 lui a5,0x10008 +20401050: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20401054: fec42703 lw a4,-20(s0) +20401058: 00e7a023 sw a4,0(a5) +2040105c: 100087b7 lui a5,0x10008 +20401060: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20401064: 0007a683 lw a3,0(a5) +20401068: 100087b7 lui a5,0x10008 +2040106c: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20401070: fffc0737 lui a4,0xfffc0 +20401074: fff70713 addi a4,a4,-1 # fffbffff <_sp+0x7ffbbfff> +20401078: 00e6f733 and a4,a3,a4 +2040107c: 00e7a023 sw a4,0(a5) +20401080: d8dff0ef jal ra,20400e0c +20401084: fea42423 sw a0,-24(s0) +20401088: 00000013 nop +2040108c: d81ff0ef jal ra,20400e0c +20401090: 00050713 mv a4,a0 +20401094: fe842783 lw a5,-24(s0) +20401098: 40f70733 sub a4,a4,a5 +2040109c: 00300793 li a5,3 +204010a0: fee7f6e3 bleu a4,a5,2040108c +204010a4: 00000013 nop +204010a8: 100087b7 lui a5,0x10008 +204010ac: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +204010b0: 0007a783 lw a5,0(a5) +204010b4: fe07dae3 bgez a5,204010a8 +204010b8: 100087b7 lui a5,0x10008 +204010bc: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +204010c0: 0007a683 lw a3,0(a5) +204010c4: 100087b7 lui a5,0x10008 +204010c8: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +204010cc: 00010737 lui a4,0x10 +204010d0: 00e6e733 or a4,a3,a4 +204010d4: 00e7a023 sw a4,0(a5) +204010d8: 00000013 nop +204010dc: 03c12083 lw ra,60(sp) +204010e0: 03812403 lw s0,56(sp) +204010e4: 04010113 addi sp,sp,64 +204010e8: 00008067 ret + +204010ec : +204010ec: ff010113 addi sp,sp,-16 +204010f0: 00112623 sw ra,12(sp) +204010f4: 00812423 sw s0,8(sp) +204010f8: 01010413 addi s0,sp,16 +204010fc: 100007b7 lui a5,0x10000 +20401100: 07078793 addi a5,a5,112 # 10000070 <__stack_size+0xffff870> +20401104: 0007a683 lw a3,0(a5) +20401108: 100007b7 lui a5,0x10000 +2040110c: 07078793 addi a5,a5,112 # 10000070 <__stack_size+0xffff870> +20401110: c0000737 lui a4,0xc0000 +20401114: fff70713 addi a4,a4,-1 # bfffffff <_sp+0x3fffbfff> +20401118: 00e6f733 and a4,a3,a4 +2040111c: 00e7a023 sw a4,0(a5) +20401120: 01000593 li a1,16 +20401124: 00400513 li a0,4 +20401128: d7dff0ef jal ra,20400ea4 +2040112c: 00000013 nop +20401130: 00c12083 lw ra,12(sp) +20401134: 00812403 lw s0,8(sp) +20401138: 01010113 addi sp,sp,16 +2040113c: 00008067 ret + +20401140 : +20401140: fc010113 addi sp,sp,-64 +20401144: 02112e23 sw ra,60(sp) +20401148: 02812c23 sw s0,56(sp) +2040114c: 02912a23 sw s1,52(sp) +20401150: 04010413 addi s0,sp,64 +20401154: fca42623 sw a0,-52(s0) +20401158: d2dff0ef jal ra,20400e84 +2040115c: fea42623 sw a0,-20(s0) +20401160: cadff0ef jal ra,20400e0c +20401164: fea42423 sw a0,-24(s0) +20401168: ca5ff0ef jal ra,20400e0c +2040116c: fea42223 sw a0,-28(s0) +20401170: fe442703 lw a4,-28(s0) +20401174: fe842783 lw a5,-24(s0) +20401178: fef708e3 beq a4,a5,20401168 +2040117c: b00027f3 csrr a5,mcycle +20401180: fef42023 sw a5,-32(s0) +20401184: fe042783 lw a5,-32(s0) +20401188: fcf42e23 sw a5,-36(s0) +2040118c: c81ff0ef jal ra,20400e0c +20401190: 00050713 mv a4,a0 +20401194: fe442783 lw a5,-28(s0) +20401198: 40f707b3 sub a5,a4,a5 +2040119c: fcf42c23 sw a5,-40(s0) +204011a0: fd842703 lw a4,-40(s0) +204011a4: fcc42783 lw a5,-52(s0) +204011a8: fef762e3 bltu a4,a5,2040118c +204011ac: b00027f3 csrr a5,mcycle +204011b0: fcf42a23 sw a5,-44(s0) +204011b4: fd442703 lw a4,-44(s0) +204011b8: fdc42783 lw a5,-36(s0) +204011bc: 40f707b3 sub a5,a4,a5 +204011c0: fcf42823 sw a5,-48(s0) +204011c4: fd842583 lw a1,-40(s0) +204011c8: fd042503 lw a0,-48(s0) +204011cc: 7cd000ef jal ra,20402198 <__udivsi3> +204011d0: 00050793 mv a5,a0 +204011d4: fec42583 lw a1,-20(s0) +204011d8: 00078513 mv a0,a5 +204011dc: 791000ef jal ra,2040216c <__mulsi3> +204011e0: 00050793 mv a5,a0 +204011e4: 00078493 mv s1,a5 +204011e8: fd042783 lw a5,-48(s0) +204011ec: fd842583 lw a1,-40(s0) +204011f0: 00078513 mv a0,a5 +204011f4: 7ed000ef jal ra,204021e0 <__umodsi3> +204011f8: 00050793 mv a5,a0 +204011fc: fec42583 lw a1,-20(s0) +20401200: 00078513 mv a0,a5 +20401204: 769000ef jal ra,2040216c <__mulsi3> +20401208: 00050793 mv a5,a0 +2040120c: fd842583 lw a1,-40(s0) +20401210: 00078513 mv a0,a5 +20401214: 785000ef jal ra,20402198 <__udivsi3> +20401218: 00050793 mv a5,a0 +2040121c: 00f487b3 add a5,s1,a5 +20401220: 00078513 mv a0,a5 +20401224: 03c12083 lw ra,60(sp) +20401228: 03812403 lw s0,56(sp) +2040122c: 03412483 lw s1,52(sp) +20401230: 04010113 addi sp,sp,64 +20401234: 00008067 ret + +20401238 : +20401238: ff010113 addi sp,sp,-16 +2040123c: 00112623 sw ra,12(sp) +20401240: 00812423 sw s0,8(sp) +20401244: 01010413 addi s0,sp,16 +20401248: 800007b7 lui a5,0x80000 +2040124c: 4307a783 lw a5,1072(a5) # 80000430 <_sp+0xffffc430> +20401250: 02079063 bnez a5,20401270 +20401254: 00100513 li a0,1 +20401258: ee9ff0ef jal ra,20401140 +2040125c: 00a00513 li a0,10 +20401260: ee1ff0ef jal ra,20401140 +20401264: 00050713 mv a4,a0 +20401268: 800007b7 lui a5,0x80000 +2040126c: 42e7a823 sw a4,1072(a5) # 80000430 <_sp+0xffffc430> +20401270: 800007b7 lui a5,0x80000 +20401274: 4307a783 lw a5,1072(a5) # 80000430 <_sp+0xffffc430> +20401278: 00078513 mv a0,a5 +2040127c: 00c12083 lw ra,12(sp) +20401280: 00812403 lw s0,8(sp) +20401284: 01010113 addi sp,sp,16 +20401288: 00008067 ret + +2040128c : +2040128c: fe010113 addi sp,sp,-32 +20401290: 00112e23 sw ra,28(sp) +20401294: 00812c23 sw s0,24(sp) +20401298: 02010413 addi s0,sp,32 +2040129c: fea42623 sw a0,-20(s0) +204012a0: 100127b7 lui a5,0x10012 +204012a4: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +204012a8: 0007a683 lw a3,0(a5) +204012ac: 100127b7 lui a5,0x10012 +204012b0: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +204012b4: fffd0737 lui a4,0xfffd0 +204012b8: fff70713 addi a4,a4,-1 # fffcffff <_sp+0x7ffcbfff> +204012bc: 00e6f733 and a4,a3,a4 +204012c0: 00e7a023 sw a4,0(a5) +204012c4: 100127b7 lui a5,0x10012 +204012c8: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +204012cc: 0007a683 lw a3,0(a5) +204012d0: 100127b7 lui a5,0x10012 +204012d4: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +204012d8: 00030737 lui a4,0x30 +204012dc: 00e6e733 or a4,a3,a4 +204012e0: 00e7a023 sw a4,0(a5) +204012e4: f55ff0ef jal ra,20401238 +204012e8: 00050793 mv a5,a0 +204012ec: fec42583 lw a1,-20(s0) +204012f0: 00078513 mv a0,a5 +204012f4: 6a5000ef jal ra,20402198 <__udivsi3> +204012f8: 00050793 mv a5,a0 +204012fc: 00078713 mv a4,a5 +20401300: 100137b7 lui a5,0x10013 +20401304: 01878793 addi a5,a5,24 # 10013018 <__stack_size+0x10012818> +20401308: fff70713 addi a4,a4,-1 # 2ffff <__stack_size+0x2f7ff> +2040130c: 00e7a023 sw a4,0(a5) +20401310: 100137b7 lui a5,0x10013 +20401314: 00878793 addi a5,a5,8 # 10013008 <__stack_size+0x10012808> +20401318: 0007a703 lw a4,0(a5) +2040131c: 100137b7 lui a5,0x10013 +20401320: 00878793 addi a5,a5,8 # 10013008 <__stack_size+0x10012808> +20401324: 00176713 ori a4,a4,1 +20401328: 00e7a023 sw a4,0(a5) +2040132c: 00000013 nop +20401330: 01c12083 lw ra,28(sp) +20401334: 01812403 lw s0,24(sp) +20401338: 02010113 addi sp,sp,32 +2040133c: 00008067 ret + +20401340 : +20401340: fe010113 addi sp,sp,-32 +20401344: 00112e23 sw ra,28(sp) +20401348: 00812c23 sw s0,24(sp) +2040134c: 02010413 addi s0,sp,32 +20401350: fea42623 sw a0,-20(s0) +20401354: feb42423 sw a1,-24(s0) +20401358: 00500613 li a2,5 +2040135c: 204027b7 lui a5,0x20402 +20401360: 43878593 addi a1,a5,1080 # 20402438 <__clzsi2+0x1f4> +20401364: 00100513 li a0,1 +20401368: 0e4000ef jal ra,2040144c <__wrap_write> +2040136c: fec42783 lw a5,-20(s0) +20401370: 00178793 addi a5,a5,1 +20401374: 00078513 mv a0,a5 +20401378: 1f0000ef jal ra,20401568 <__wrap__exit> + +2040137c <_init>: +2040137c: fe010113 addi sp,sp,-32 +20401380: 00112e23 sw ra,28(sp) +20401384: 00812c23 sw s0,24(sp) +20401388: 02010413 addi s0,sp,32 +2040138c: d61ff0ef jal ra,204010ec +20401390: 00100713 li a4,1 +20401394: 01f00693 li a3,31 +20401398: 00100613 li a2,1 +2040139c: 00000593 li a1,0 +204013a0: 00000513 li a0,0 +204013a4: b85ff0ef jal ra,20400f28 +204013a8: 0001c7b7 lui a5,0x1c +204013ac: 20078513 addi a0,a5,512 # 1c200 <__stack_size+0x1ba00> +204013b0: eddff0ef jal ra,2040128c +204013b4: e85ff0ef jal ra,20401238 +204013b8: 00050793 mv a5,a0 +204013bc: 00078593 mv a1,a5 +204013c0: 204027b7 lui a5,0x20402 +204013c4: 44078513 addi a0,a5,1088 # 20402440 <__clzsi2+0x1fc> +204013c8: 945ff0ef jal ra,20400d0c <__wrap_printf> +204013cc: 204007b7 lui a5,0x20400 +204013d0: 08078793 addi a5,a5,128 # 20400080 +204013d4: 30579073 csrw mtvec,a5 +204013d8: 301027f3 csrr a5,misa +204013dc: fef42623 sw a5,-20(s0) +204013e0: fec42783 lw a5,-20(s0) +204013e4: 0207f793 andi a5,a5,32 +204013e8: 00078863 beqz a5,204013f8 <_init+0x7c> +204013ec: 000067b7 lui a5,0x6 +204013f0: 30079073 csrw mstatus,a5 +204013f4: 00305073 csrwi fcsr,0 +204013f8: 00000013 nop +204013fc: 01c12083 lw ra,28(sp) +20401400: 01812403 lw s0,24(sp) +20401404: 02010113 addi sp,sp,32 +20401408: 00008067 ret + +2040140c <_fini>: +2040140c: ff010113 addi sp,sp,-16 +20401410: 00812623 sw s0,12(sp) +20401414: 01010413 addi s0,sp,16 +20401418: 00000013 nop +2040141c: 00c12403 lw s0,12(sp) +20401420: 01010113 addi sp,sp,16 +20401424: 00008067 ret + +20401428 <_stub>: +20401428: fe010113 addi sp,sp,-32 +2040142c: 00812e23 sw s0,28(sp) +20401430: 02010413 addi s0,sp,32 +20401434: fea42623 sw a0,-20(s0) +20401438: fff00793 li a5,-1 +2040143c: 00078513 mv a0,a5 +20401440: 01c12403 lw s0,28(sp) +20401444: 02010113 addi sp,sp,32 +20401448: 00008067 ret + +2040144c <__wrap_write>: +2040144c: fd010113 addi sp,sp,-48 +20401450: 02112623 sw ra,44(sp) +20401454: 02812423 sw s0,40(sp) +20401458: 03010413 addi s0,sp,48 +2040145c: fca42e23 sw a0,-36(s0) +20401460: fcb42c23 sw a1,-40(s0) +20401464: fcc42a23 sw a2,-44(s0) +20401468: fd842783 lw a5,-40(s0) +2040146c: fef42423 sw a5,-24(s0) +20401470: fdc42503 lw a0,-36(s0) +20401474: 0b0000ef jal ra,20401524 <__wrap_isatty> +20401478: 00050793 mv a5,a0 +2040147c: 08078463 beqz a5,20401504 <__wrap_write+0xb8> +20401480: fe042623 sw zero,-20(s0) +20401484: 06c0006f j 204014f0 <__wrap_write+0xa4> +20401488: 00000013 nop +2040148c: 100137b7 lui a5,0x10013 +20401490: 0007a783 lw a5,0(a5) # 10013000 <__stack_size+0x10012800> +20401494: fe07cce3 bltz a5,2040148c <__wrap_write+0x40> +20401498: fe842703 lw a4,-24(s0) +2040149c: fec42783 lw a5,-20(s0) +204014a0: 00f707b3 add a5,a4,a5 +204014a4: 0007c703 lbu a4,0(a5) +204014a8: 100137b7 lui a5,0x10013 +204014ac: 00e7a023 sw a4,0(a5) # 10013000 <__stack_size+0x10012800> +204014b0: fe842703 lw a4,-24(s0) +204014b4: fec42783 lw a5,-20(s0) +204014b8: 00f707b3 add a5,a4,a5 +204014bc: 0007c703 lbu a4,0(a5) +204014c0: 00a00793 li a5,10 +204014c4: 02f71063 bne a4,a5,204014e4 <__wrap_write+0x98> +204014c8: 00000013 nop +204014cc: 100137b7 lui a5,0x10013 +204014d0: 0007a783 lw a5,0(a5) # 10013000 <__stack_size+0x10012800> +204014d4: fe07cce3 bltz a5,204014cc <__wrap_write+0x80> +204014d8: 100137b7 lui a5,0x10013 +204014dc: 00d00713 li a4,13 +204014e0: 00e7a023 sw a4,0(a5) # 10013000 <__stack_size+0x10012800> +204014e4: fec42783 lw a5,-20(s0) +204014e8: 00178793 addi a5,a5,1 +204014ec: fef42623 sw a5,-20(s0) +204014f0: fec42703 lw a4,-20(s0) +204014f4: fd442783 lw a5,-44(s0) +204014f8: f8f768e3 bltu a4,a5,20401488 <__wrap_write+0x3c> +204014fc: fd442783 lw a5,-44(s0) +20401500: 0100006f j 20401510 <__wrap_write+0xc4> +20401504: 00900513 li a0,9 +20401508: f21ff0ef jal ra,20401428 <_stub> +2040150c: 00050793 mv a5,a0 +20401510: 00078513 mv a0,a5 +20401514: 02c12083 lw ra,44(sp) +20401518: 02812403 lw s0,40(sp) +2040151c: 03010113 addi sp,sp,48 +20401520: 00008067 ret + +20401524 <__wrap_isatty>: +20401524: fe010113 addi sp,sp,-32 +20401528: 00812e23 sw s0,28(sp) +2040152c: 02010413 addi s0,sp,32 +20401530: fea42623 sw a0,-20(s0) +20401534: fec42703 lw a4,-20(s0) +20401538: 00100793 li a5,1 +2040153c: 00f70863 beq a4,a5,2040154c <__wrap_isatty+0x28> +20401540: fec42703 lw a4,-20(s0) +20401544: 00200793 li a5,2 +20401548: 00f71663 bne a4,a5,20401554 <__wrap_isatty+0x30> +2040154c: 00100793 li a5,1 +20401550: 0080006f j 20401558 <__wrap_isatty+0x34> +20401554: 00000793 li a5,0 +20401558: 00078513 mv a0,a5 +2040155c: 01c12403 lw s0,28(sp) +20401560: 02010113 addi sp,sp,32 +20401564: 00008067 ret + +20401568 <__wrap__exit>: +20401568: fc010113 addi sp,sp,-64 +2040156c: 02112e23 sw ra,60(sp) +20401570: 02812c23 sw s0,56(sp) +20401574: 04010413 addi s0,sp,64 +20401578: fca42623 sw a0,-52(s0) +2040157c: 204027b7 lui a5,0x20402 +20401580: 4587a883 lw a7,1112(a5) # 20402458 <__clzsi2+0x214> +20401584: 45878713 addi a4,a5,1112 +20401588: 00472803 lw a6,4(a4) +2040158c: 45878713 addi a4,a5,1112 +20401590: 00872503 lw a0,8(a4) +20401594: 45878713 addi a4,a5,1112 +20401598: 00c72583 lw a1,12(a4) +2040159c: 45878713 addi a4,a5,1112 +204015a0: 01072603 lw a2,16(a4) +204015a4: 45878713 addi a4,a5,1112 +204015a8: 01472683 lw a3,20(a4) +204015ac: 45878713 addi a4,a5,1112 +204015b0: 01872703 lw a4,24(a4) +204015b4: fd142823 sw a7,-48(s0) +204015b8: fd042a23 sw a6,-44(s0) +204015bc: fca42c23 sw a0,-40(s0) +204015c0: fcb42e23 sw a1,-36(s0) +204015c4: fec42023 sw a2,-32(s0) +204015c8: fed42223 sw a3,-28(s0) +204015cc: fee42423 sw a4,-24(s0) +204015d0: 45878793 addi a5,a5,1112 +204015d4: 01c7d783 lhu a5,28(a5) +204015d8: fef41623 sh a5,-20(s0) +204015dc: fd040793 addi a5,s0,-48 +204015e0: 01d00613 li a2,29 +204015e4: 00078593 mv a1,a5 +204015e8: 00200513 li a0,2 +204015ec: e61ff0ef jal ra,2040144c <__wrap_write> +204015f0: fcc42783 lw a5,-52(s0) +204015f4: 00078593 mv a1,a5 +204015f8: 00200513 li a0,2 +204015fc: 01c000ef jal ra,20401618 +20401600: 00100613 li a2,1 +20401604: 204027b7 lui a5,0x20402 +20401608: 45478593 addi a1,a5,1108 # 20402454 <__clzsi2+0x210> +2040160c: 00200513 li a0,2 +20401610: e3dff0ef jal ra,2040144c <__wrap_write> +20401614: 0000006f j 20401614 <__wrap__exit+0xac> + +20401618 : +20401618: fd010113 addi sp,sp,-48 +2040161c: 02112623 sw ra,44(sp) +20401620: 02812423 sw s0,40(sp) +20401624: 03010413 addi s0,sp,48 +20401628: fca42e23 sw a0,-36(s0) +2040162c: fcb42c23 sw a1,-40(s0) +20401630: 00200613 li a2,2 +20401634: 204027b7 lui a5,0x20402 +20401638: 47878593 addi a1,a5,1144 # 20402478 <__clzsi2+0x234> +2040163c: fdc42503 lw a0,-36(s0) +20401640: e0dff0ef jal ra,2040144c <__wrap_write> +20401644: 00800793 li a5,8 +20401648: fef407a3 sb a5,-17(s0) +2040164c: 0880006f j 204016d4 +20401650: fef44783 lbu a5,-17(s0) +20401654: fff78793 addi a5,a5,-1 +20401658: fef40723 sb a5,-18(s0) +2040165c: fee44783 lbu a5,-18(s0) +20401660: 00279793 slli a5,a5,0x2 +20401664: 00f00713 li a4,15 +20401668: 00f717b3 sll a5,a4,a5 +2040166c: 00078713 mv a4,a5 +20401670: fd842783 lw a5,-40(s0) +20401674: 00f77733 and a4,a4,a5 +20401678: fee44783 lbu a5,-18(s0) +2040167c: 00279793 slli a5,a5,0x2 +20401680: 00f757b3 srl a5,a4,a5 +20401684: fef406a3 sb a5,-19(s0) +20401688: fed44703 lbu a4,-19(s0) +2040168c: 00900793 li a5,9 +20401690: 00e7ea63 bltu a5,a4,204016a4 +20401694: fed44783 lbu a5,-19(s0) +20401698: 03078793 addi a5,a5,48 +2040169c: 0ff7f793 andi a5,a5,255 +204016a0: 0100006f j 204016b0 +204016a4: fed44783 lbu a5,-19(s0) +204016a8: 03778793 addi a5,a5,55 +204016ac: 0ff7f793 andi a5,a5,255 +204016b0: fef40623 sb a5,-20(s0) +204016b4: fec40793 addi a5,s0,-20 +204016b8: 00100613 li a2,1 +204016bc: 00078593 mv a1,a5 +204016c0: fdc42503 lw a0,-36(s0) +204016c4: d89ff0ef jal ra,2040144c <__wrap_write> +204016c8: fef44783 lbu a5,-17(s0) +204016cc: fff78793 addi a5,a5,-1 +204016d0: fef407a3 sb a5,-17(s0) +204016d4: fef44783 lbu a5,-17(s0) +204016d8: f6079ce3 bnez a5,20401650 +204016dc: 00000013 nop +204016e0: 02c12083 lw ra,44(sp) +204016e4: 02812403 lw s0,40(sp) +204016e8: 03010113 addi sp,sp,48 +204016ec: 00008067 ret + +204016f0 : +204016f0: 00050593 mv a1,a0 +204016f4: 00000693 li a3,0 +204016f8: 00000613 li a2,0 +204016fc: 00000513 li a0,0 +20401700: 1680006f j 20401868 <__register_exitproc> + +20401704 : +20401704: ff010113 addi sp,sp,-16 +20401708: 00000593 li a1,0 +2040170c: 00812423 sw s0,8(sp) +20401710: 00112623 sw ra,12(sp) +20401714: 00050413 mv s0,a0 +20401718: 1d4000ef jal ra,204018ec <__call_exitprocs> +2040171c: 5fbff797 auipc a5,0x5fbff +20401720: d0c78793 addi a5,a5,-756 # 80000428 <_global_impure_ptr> +20401724: 0007a503 lw a0,0(a5) +20401728: 03c52783 lw a5,60(a0) +2040172c: 00078463 beqz a5,20401734 +20401730: 000780e7 jalr a5 +20401734: 00040513 mv a0,s0 +20401738: e31ff0ef jal ra,20401568 <__wrap__exit> + +2040173c <__libc_fini_array>: +2040173c: ff010113 addi sp,sp,-16 +20401740: 00001797 auipc a5,0x1 +20401744: e7878793 addi a5,a5,-392 # 204025b8 <__fini_array_end> +20401748: 00812423 sw s0,8(sp) +2040174c: 00001417 auipc s0,0x1 +20401750: e6c40413 addi s0,s0,-404 # 204025b8 <__fini_array_end> +20401754: 40878433 sub s0,a5,s0 +20401758: 00912223 sw s1,4(sp) +2040175c: 01212023 sw s2,0(sp) +20401760: 00112623 sw ra,12(sp) +20401764: 40245413 srai s0,s0,0x2 +20401768: 00000493 li s1,0 +2040176c: 00078913 mv s2,a5 +20401770: 00941e63 bne s0,s1,2040178c <__libc_fini_array+0x50> +20401774: 00812403 lw s0,8(sp) +20401778: 00c12083 lw ra,12(sp) +2040177c: 00412483 lw s1,4(sp) +20401780: 00012903 lw s2,0(sp) +20401784: 01010113 addi sp,sp,16 +20401788: c85ff06f j 2040140c <_fini> +2040178c: ffc00593 li a1,-4 +20401790: 00048513 mv a0,s1 +20401794: 1d9000ef jal ra,2040216c <__mulsi3> +20401798: 00a90533 add a0,s2,a0 +2040179c: ffc52783 lw a5,-4(a0) +204017a0: 00148493 addi s1,s1,1 +204017a4: 000780e7 jalr a5 +204017a8: fc9ff06f j 20401770 <__libc_fini_array+0x34> + +204017ac <__libc_init_array>: +204017ac: ff010113 addi sp,sp,-16 +204017b0: 00812423 sw s0,8(sp) +204017b4: 00912223 sw s1,4(sp) +204017b8: 00001417 auipc s0,0x1 +204017bc: e0040413 addi s0,s0,-512 # 204025b8 <__fini_array_end> +204017c0: 00001497 auipc s1,0x1 +204017c4: df848493 addi s1,s1,-520 # 204025b8 <__fini_array_end> +204017c8: 408484b3 sub s1,s1,s0 +204017cc: 01212023 sw s2,0(sp) +204017d0: 00112623 sw ra,12(sp) +204017d4: 4024d493 srai s1,s1,0x2 +204017d8: 00000913 li s2,0 +204017dc: 04991063 bne s2,s1,2040181c <__libc_init_array+0x70> +204017e0: 00001417 auipc s0,0x1 +204017e4: dd840413 addi s0,s0,-552 # 204025b8 <__fini_array_end> +204017e8: 00001497 auipc s1,0x1 +204017ec: dd048493 addi s1,s1,-560 # 204025b8 <__fini_array_end> +204017f0: 408484b3 sub s1,s1,s0 +204017f4: b89ff0ef jal ra,2040137c <_init> +204017f8: 4024d493 srai s1,s1,0x2 +204017fc: 00000913 li s2,0 +20401800: 02991863 bne s2,s1,20401830 <__libc_init_array+0x84> +20401804: 00c12083 lw ra,12(sp) +20401808: 00812403 lw s0,8(sp) +2040180c: 00412483 lw s1,4(sp) +20401810: 00012903 lw s2,0(sp) +20401814: 01010113 addi sp,sp,16 +20401818: 00008067 ret +2040181c: 00042783 lw a5,0(s0) +20401820: 00190913 addi s2,s2,1 +20401824: 00440413 addi s0,s0,4 +20401828: 000780e7 jalr a5 +2040182c: fb1ff06f j 204017dc <__libc_init_array+0x30> +20401830: 00042783 lw a5,0(s0) +20401834: 00190913 addi s2,s2,1 +20401838: 00440413 addi s0,s0,4 +2040183c: 000780e7 jalr a5 +20401840: fc1ff06f j 20401800 <__libc_init_array+0x54> + +20401844 : +20401844: 00b505b3 add a1,a0,a1 +20401848: 00050793 mv a5,a0 +2040184c: 00b78663 beq a5,a1,20401858 +20401850: 0007c703 lbu a4,0(a5) +20401854: 00071663 bnez a4,20401860 +20401858: 40a78533 sub a0,a5,a0 +2040185c: 00008067 ret +20401860: 00178793 addi a5,a5,1 +20401864: fe9ff06f j 2040184c + +20401868 <__register_exitproc>: +20401868: 5fbff797 auipc a5,0x5fbff +2040186c: bc078793 addi a5,a5,-1088 # 80000428 <_global_impure_ptr> +20401870: 0007a703 lw a4,0(a5) +20401874: 00050313 mv t1,a0 +20401878: 14872783 lw a5,328(a4) +2040187c: 00079663 bnez a5,20401888 <__register_exitproc+0x20> +20401880: 14c70793 addi a5,a4,332 +20401884: 14f72423 sw a5,328(a4) +20401888: 0047a703 lw a4,4(a5) +2040188c: 01f00813 li a6,31 +20401890: fff00513 li a0,-1 +20401894: 04e84a63 blt a6,a4,204018e8 <__register_exitproc+0x80> +20401898: 00271893 slli a7,a4,0x2 +2040189c: 02030c63 beqz t1,204018d4 <__register_exitproc+0x6c> +204018a0: 01178533 add a0,a5,a7 +204018a4: 08c52423 sw a2,136(a0) +204018a8: 1887a803 lw a6,392(a5) +204018ac: 00100613 li a2,1 +204018b0: 00e61633 sll a2,a2,a4 +204018b4: 00c86833 or a6,a6,a2 +204018b8: 1907a423 sw a6,392(a5) +204018bc: 10d52423 sw a3,264(a0) +204018c0: 00200693 li a3,2 +204018c4: 00d31863 bne t1,a3,204018d4 <__register_exitproc+0x6c> +204018c8: 18c7a683 lw a3,396(a5) +204018cc: 00c6e633 or a2,a3,a2 +204018d0: 18c7a623 sw a2,396(a5) +204018d4: 00170713 addi a4,a4,1 +204018d8: 00e7a223 sw a4,4(a5) +204018dc: 011787b3 add a5,a5,a7 +204018e0: 00b7a423 sw a1,8(a5) +204018e4: 00000513 li a0,0 +204018e8: 00008067 ret + +204018ec <__call_exitprocs>: +204018ec: fd010113 addi sp,sp,-48 +204018f0: 5fbff797 auipc a5,0x5fbff +204018f4: b3878793 addi a5,a5,-1224 # 80000428 <_global_impure_ptr> +204018f8: 01312e23 sw s3,28(sp) +204018fc: 0007a983 lw s3,0(a5) +20401900: 01412c23 sw s4,24(sp) +20401904: 01512a23 sw s5,20(sp) +20401908: 01612823 sw s6,16(sp) +2040190c: 02112623 sw ra,44(sp) +20401910: 02812423 sw s0,40(sp) +20401914: 02912223 sw s1,36(sp) +20401918: 03212023 sw s2,32(sp) +2040191c: 01712623 sw s7,12(sp) +20401920: 00050a93 mv s5,a0 +20401924: 00058a13 mv s4,a1 +20401928: 00100b13 li s6,1 +2040192c: 1489a483 lw s1,328(s3) +20401930: 00048c63 beqz s1,20401948 <__call_exitprocs+0x5c> +20401934: 0044a403 lw s0,4(s1) +20401938: fff40913 addi s2,s0,-1 +2040193c: 00241413 slli s0,s0,0x2 +20401940: 00848433 add s0,s1,s0 +20401944: 02095863 bgez s2,20401974 <__call_exitprocs+0x88> +20401948: 02c12083 lw ra,44(sp) +2040194c: 02812403 lw s0,40(sp) +20401950: 02412483 lw s1,36(sp) +20401954: 02012903 lw s2,32(sp) +20401958: 01c12983 lw s3,28(sp) +2040195c: 01812a03 lw s4,24(sp) +20401960: 01412a83 lw s5,20(sp) +20401964: 01012b03 lw s6,16(sp) +20401968: 00c12b83 lw s7,12(sp) +2040196c: 03010113 addi sp,sp,48 +20401970: 00008067 ret +20401974: 000a0c63 beqz s4,2040198c <__call_exitprocs+0xa0> +20401978: 10442783 lw a5,260(s0) +2040197c: 01478863 beq a5,s4,2040198c <__call_exitprocs+0xa0> +20401980: fff90913 addi s2,s2,-1 +20401984: ffc40413 addi s0,s0,-4 +20401988: fbdff06f j 20401944 <__call_exitprocs+0x58> +2040198c: 0044a703 lw a4,4(s1) +20401990: 00442783 lw a5,4(s0) +20401994: fff70713 addi a4,a4,-1 +20401998: 03271c63 bne a4,s2,204019d0 <__call_exitprocs+0xe4> +2040199c: 0124a223 sw s2,4(s1) +204019a0: fe0780e3 beqz a5,20401980 <__call_exitprocs+0x94> +204019a4: 1884a683 lw a3,392(s1) +204019a8: 012b1733 sll a4,s6,s2 +204019ac: 0044ab83 lw s7,4(s1) +204019b0: 00d776b3 and a3,a4,a3 +204019b4: 02069263 bnez a3,204019d8 <__call_exitprocs+0xec> +204019b8: 000780e7 jalr a5 +204019bc: 0044a703 lw a4,4(s1) +204019c0: 1489a783 lw a5,328(s3) +204019c4: f77714e3 bne a4,s7,2040192c <__call_exitprocs+0x40> +204019c8: faf48ce3 beq s1,a5,20401980 <__call_exitprocs+0x94> +204019cc: f61ff06f j 2040192c <__call_exitprocs+0x40> +204019d0: 00042223 sw zero,4(s0) +204019d4: fcdff06f j 204019a0 <__call_exitprocs+0xb4> +204019d8: 18c4a683 lw a3,396(s1) +204019dc: 08442583 lw a1,132(s0) +204019e0: 00d77733 and a4,a4,a3 +204019e4: 00071863 bnez a4,204019f4 <__call_exitprocs+0x108> +204019e8: 000a8513 mv a0,s5 +204019ec: 000780e7 jalr a5 +204019f0: fcdff06f j 204019bc <__call_exitprocs+0xd0> +204019f4: 00058513 mv a0,a1 +204019f8: 000780e7 jalr a5 +204019fc: fc1ff06f j 204019bc <__call_exitprocs+0xd0> + +20401a00 <__muldf3>: +20401a00: fa010113 addi sp,sp,-96 +20401a04: 04812c23 sw s0,88(sp) +20401a08: 05312623 sw s3,76(sp) +20401a0c: 00100437 lui s0,0x100 +20401a10: 0145d993 srli s3,a1,0x14 +20401a14: 04912a23 sw s1,84(sp) +20401a18: 05612023 sw s6,64(sp) +20401a1c: 03712e23 sw s7,60(sp) +20401a20: 03812c23 sw s8,56(sp) +20401a24: fff40413 addi s0,s0,-1 # fffff <__stack_size+0xff7ff> +20401a28: 04112e23 sw ra,92(sp) +20401a2c: 05212823 sw s2,80(sp) +20401a30: 05412423 sw s4,72(sp) +20401a34: 05512223 sw s5,68(sp) +20401a38: 03912a23 sw s9,52(sp) +20401a3c: 03a12823 sw s10,48(sp) +20401a40: 03b12623 sw s11,44(sp) +20401a44: 7ff9f993 andi s3,s3,2047 +20401a48: 00050493 mv s1,a0 +20401a4c: 00060b93 mv s7,a2 +20401a50: 00068c13 mv s8,a3 +20401a54: 00b47433 and s0,s0,a1 +20401a58: 01f5db13 srli s6,a1,0x1f +20401a5c: 0a098863 beqz s3,20401b0c <__muldf3+0x10c> +20401a60: 7ff00793 li a5,2047 +20401a64: 10f98663 beq s3,a5,20401b70 <__muldf3+0x170> +20401a68: 00800937 lui s2,0x800 +20401a6c: 00341413 slli s0,s0,0x3 +20401a70: 01246433 or s0,s0,s2 +20401a74: 01d55913 srli s2,a0,0x1d +20401a78: 00896933 or s2,s2,s0 +20401a7c: 00351d13 slli s10,a0,0x3 +20401a80: c0198993 addi s3,s3,-1023 +20401a84: 00000c93 li s9,0 +20401a88: 014c5513 srli a0,s8,0x14 +20401a8c: 00100a37 lui s4,0x100 +20401a90: fffa0a13 addi s4,s4,-1 # fffff <__stack_size+0xff7ff> +20401a94: 7ff57513 andi a0,a0,2047 +20401a98: 018a7a33 and s4,s4,s8 +20401a9c: 000b8493 mv s1,s7 +20401aa0: 01fc5c13 srli s8,s8,0x1f +20401aa4: 10050463 beqz a0,20401bac <__muldf3+0x1ac> +20401aa8: 7ff00793 li a5,2047 +20401aac: 16f50463 beq a0,a5,20401c14 <__muldf3+0x214> +20401ab0: 00800437 lui s0,0x800 +20401ab4: 003a1a13 slli s4,s4,0x3 +20401ab8: 008a6a33 or s4,s4,s0 +20401abc: 01dbd413 srli s0,s7,0x1d +20401ac0: 01446433 or s0,s0,s4 +20401ac4: 003b9493 slli s1,s7,0x3 +20401ac8: c0150513 addi a0,a0,-1023 +20401acc: 00000793 li a5,0 +20401ad0: 002c9713 slli a4,s9,0x2 +20401ad4: 00f76733 or a4,a4,a5 +20401ad8: 00a989b3 add s3,s3,a0 +20401adc: fff70713 addi a4,a4,-1 +20401ae0: 00e00693 li a3,14 +20401ae4: 018b4bb3 xor s7,s6,s8 +20401ae8: 00198a93 addi s5,s3,1 +20401aec: 16e6e063 bltu a3,a4,20401c4c <__muldf3+0x24c> +20401af0: 00001697 auipc a3,0x1 +20401af4: 98c68693 addi a3,a3,-1652 # 2040247c <__clzsi2+0x238> +20401af8: 00271713 slli a4,a4,0x2 +20401afc: 00d70733 add a4,a4,a3 +20401b00: 00072703 lw a4,0(a4) +20401b04: 00d70733 add a4,a4,a3 +20401b08: 00070067 jr a4 +20401b0c: 00a46933 or s2,s0,a0 +20401b10: 06090e63 beqz s2,20401b8c <__muldf3+0x18c> +20401b14: 04040063 beqz s0,20401b54 <__muldf3+0x154> +20401b18: 00040513 mv a0,s0 +20401b1c: 728000ef jal ra,20402244 <__clzsi2> +20401b20: ff550793 addi a5,a0,-11 +20401b24: 01c00713 li a4,28 +20401b28: 02f74c63 blt a4,a5,20401b60 <__muldf3+0x160> +20401b2c: 01d00913 li s2,29 +20401b30: ff850d13 addi s10,a0,-8 +20401b34: 40f90933 sub s2,s2,a5 +20401b38: 01a41433 sll s0,s0,s10 +20401b3c: 0124d933 srl s2,s1,s2 +20401b40: 00896933 or s2,s2,s0 +20401b44: 01a49d33 sll s10,s1,s10 +20401b48: c0d00993 li s3,-1011 +20401b4c: 40a989b3 sub s3,s3,a0 +20401b50: f35ff06f j 20401a84 <__muldf3+0x84> +20401b54: 6f0000ef jal ra,20402244 <__clzsi2> +20401b58: 02050513 addi a0,a0,32 +20401b5c: fc5ff06f j 20401b20 <__muldf3+0x120> +20401b60: fd850913 addi s2,a0,-40 +20401b64: 01249933 sll s2,s1,s2 +20401b68: 00000d13 li s10,0 +20401b6c: fddff06f j 20401b48 <__muldf3+0x148> +20401b70: 00a46933 or s2,s0,a0 +20401b74: 02090463 beqz s2,20401b9c <__muldf3+0x19c> +20401b78: 00050d13 mv s10,a0 +20401b7c: 00040913 mv s2,s0 +20401b80: 7ff00993 li s3,2047 +20401b84: 00300c93 li s9,3 +20401b88: f01ff06f j 20401a88 <__muldf3+0x88> +20401b8c: 00000d13 li s10,0 +20401b90: 00000993 li s3,0 +20401b94: 00100c93 li s9,1 +20401b98: ef1ff06f j 20401a88 <__muldf3+0x88> +20401b9c: 00000d13 li s10,0 +20401ba0: 7ff00993 li s3,2047 +20401ba4: 00200c93 li s9,2 +20401ba8: ee1ff06f j 20401a88 <__muldf3+0x88> +20401bac: 017a6433 or s0,s4,s7 +20401bb0: 06040e63 beqz s0,20401c2c <__muldf3+0x22c> +20401bb4: 040a0063 beqz s4,20401bf4 <__muldf3+0x1f4> +20401bb8: 000a0513 mv a0,s4 +20401bbc: 688000ef jal ra,20402244 <__clzsi2> +20401bc0: ff550793 addi a5,a0,-11 +20401bc4: 01c00713 li a4,28 +20401bc8: 02f74e63 blt a4,a5,20401c04 <__muldf3+0x204> +20401bcc: 01d00413 li s0,29 +20401bd0: ff850493 addi s1,a0,-8 +20401bd4: 40f40433 sub s0,s0,a5 +20401bd8: 009a1a33 sll s4,s4,s1 +20401bdc: 008bd433 srl s0,s7,s0 +20401be0: 01446433 or s0,s0,s4 +20401be4: 009b94b3 sll s1,s7,s1 +20401be8: c0d00793 li a5,-1011 +20401bec: 40a78533 sub a0,a5,a0 +20401bf0: eddff06f j 20401acc <__muldf3+0xcc> +20401bf4: 000b8513 mv a0,s7 +20401bf8: 64c000ef jal ra,20402244 <__clzsi2> +20401bfc: 02050513 addi a0,a0,32 +20401c00: fc1ff06f j 20401bc0 <__muldf3+0x1c0> +20401c04: fd850413 addi s0,a0,-40 +20401c08: 008b9433 sll s0,s7,s0 +20401c0c: 00000493 li s1,0 +20401c10: fd9ff06f j 20401be8 <__muldf3+0x1e8> +20401c14: 017a6433 or s0,s4,s7 +20401c18: 02040263 beqz s0,20401c3c <__muldf3+0x23c> +20401c1c: 000a0413 mv s0,s4 +20401c20: 7ff00513 li a0,2047 +20401c24: 00300793 li a5,3 +20401c28: ea9ff06f j 20401ad0 <__muldf3+0xd0> +20401c2c: 00000493 li s1,0 +20401c30: 00000513 li a0,0 +20401c34: 00100793 li a5,1 +20401c38: e99ff06f j 20401ad0 <__muldf3+0xd0> +20401c3c: 00000493 li s1,0 +20401c40: 7ff00513 li a0,2047 +20401c44: 00200793 li a5,2 +20401c48: e89ff06f j 20401ad0 <__muldf3+0xd0> +20401c4c: 00010737 lui a4,0x10 +20401c50: fff70a13 addi s4,a4,-1 # ffff <__stack_size+0xf7ff> +20401c54: 010d5c13 srli s8,s10,0x10 +20401c58: 0104dd93 srli s11,s1,0x10 +20401c5c: 014d7d33 and s10,s10,s4 +20401c60: 0144f4b3 and s1,s1,s4 +20401c64: 000d0593 mv a1,s10 +20401c68: 00048513 mv a0,s1 +20401c6c: 00e12823 sw a4,16(sp) +20401c70: 4fc000ef jal ra,2040216c <__mulsi3> +20401c74: 00050c93 mv s9,a0 +20401c78: 00048593 mv a1,s1 +20401c7c: 000c0513 mv a0,s8 +20401c80: 4ec000ef jal ra,2040216c <__mulsi3> +20401c84: 00a12623 sw a0,12(sp) +20401c88: 000d8593 mv a1,s11 +20401c8c: 000c0513 mv a0,s8 +20401c90: 4dc000ef jal ra,2040216c <__mulsi3> +20401c94: 00050b13 mv s6,a0 +20401c98: 000d0593 mv a1,s10 +20401c9c: 000d8513 mv a0,s11 +20401ca0: 4cc000ef jal ra,2040216c <__mulsi3> +20401ca4: 00c12683 lw a3,12(sp) +20401ca8: 010cd793 srli a5,s9,0x10 +20401cac: 00d50533 add a0,a0,a3 +20401cb0: 00a78533 add a0,a5,a0 +20401cb4: 00d57663 bleu a3,a0,20401cc0 <__muldf3+0x2c0> +20401cb8: 01012703 lw a4,16(sp) +20401cbc: 00eb0b33 add s6,s6,a4 +20401cc0: 01055693 srli a3,a0,0x10 +20401cc4: 01457533 and a0,a0,s4 +20401cc8: 014cfcb3 and s9,s9,s4 +20401ccc: 01051513 slli a0,a0,0x10 +20401cd0: 019507b3 add a5,a0,s9 +20401cd4: 01045c93 srli s9,s0,0x10 +20401cd8: 01447433 and s0,s0,s4 +20401cdc: 000d0593 mv a1,s10 +20401ce0: 00040513 mv a0,s0 +20401ce4: 00d12a23 sw a3,20(sp) +20401ce8: 00f12623 sw a5,12(sp) +20401cec: 480000ef jal ra,2040216c <__mulsi3> +20401cf0: 00a12823 sw a0,16(sp) +20401cf4: 00040593 mv a1,s0 +20401cf8: 000c0513 mv a0,s8 +20401cfc: 470000ef jal ra,2040216c <__mulsi3> +20401d00: 00050a13 mv s4,a0 +20401d04: 000c8593 mv a1,s9 +20401d08: 000c0513 mv a0,s8 +20401d0c: 460000ef jal ra,2040216c <__mulsi3> +20401d10: 00050c13 mv s8,a0 +20401d14: 000d0593 mv a1,s10 +20401d18: 000c8513 mv a0,s9 +20401d1c: 450000ef jal ra,2040216c <__mulsi3> +20401d20: 01012703 lw a4,16(sp) +20401d24: 01450533 add a0,a0,s4 +20401d28: 01412683 lw a3,20(sp) +20401d2c: 01075793 srli a5,a4,0x10 +20401d30: 00a78533 add a0,a5,a0 +20401d34: 01457663 bleu s4,a0,20401d40 <__muldf3+0x340> +20401d38: 000107b7 lui a5,0x10 +20401d3c: 00fc0c33 add s8,s8,a5 +20401d40: 00010637 lui a2,0x10 +20401d44: 01055793 srli a5,a0,0x10 +20401d48: 01878c33 add s8,a5,s8 +20401d4c: fff60793 addi a5,a2,-1 # ffff <__stack_size+0xf7ff> +20401d50: 00f57a33 and s4,a0,a5 +20401d54: 00f77733 and a4,a4,a5 +20401d58: 010a1a13 slli s4,s4,0x10 +20401d5c: 01095d13 srli s10,s2,0x10 +20401d60: 00ea0a33 add s4,s4,a4 +20401d64: 00f97933 and s2,s2,a5 +20401d68: 01468733 add a4,a3,s4 +20401d6c: 00090593 mv a1,s2 +20401d70: 00048513 mv a0,s1 +20401d74: 00e12823 sw a4,16(sp) +20401d78: 00c12e23 sw a2,28(sp) +20401d7c: 3f0000ef jal ra,2040216c <__mulsi3> +20401d80: 00048593 mv a1,s1 +20401d84: 00a12c23 sw a0,24(sp) +20401d88: 000d0513 mv a0,s10 +20401d8c: 3e0000ef jal ra,2040216c <__mulsi3> +20401d90: 00a12a23 sw a0,20(sp) +20401d94: 000d0593 mv a1,s10 +20401d98: 000d8513 mv a0,s11 +20401d9c: 3d0000ef jal ra,2040216c <__mulsi3> +20401da0: 00050493 mv s1,a0 +20401da4: 00090593 mv a1,s2 +20401da8: 000d8513 mv a0,s11 +20401dac: 3c0000ef jal ra,2040216c <__mulsi3> +20401db0: 01412683 lw a3,20(sp) +20401db4: 01812703 lw a4,24(sp) +20401db8: 00d50533 add a0,a0,a3 +20401dbc: 01075793 srli a5,a4,0x10 +20401dc0: 00a78533 add a0,a5,a0 +20401dc4: 00d57663 bleu a3,a0,20401dd0 <__muldf3+0x3d0> +20401dc8: 01c12603 lw a2,28(sp) +20401dcc: 00c484b3 add s1,s1,a2 +20401dd0: 000106b7 lui a3,0x10 +20401dd4: fff68793 addi a5,a3,-1 # ffff <__stack_size+0xf7ff> +20401dd8: 01055d93 srli s11,a0,0x10 +20401ddc: 009d84b3 add s1,s11,s1 +20401de0: 00f57db3 and s11,a0,a5 +20401de4: 00f77733 and a4,a4,a5 +20401de8: 00090593 mv a1,s2 +20401dec: 00040513 mv a0,s0 +20401df0: 010d9d93 slli s11,s11,0x10 +20401df4: 00ed8db3 add s11,s11,a4 +20401df8: 00d12c23 sw a3,24(sp) +20401dfc: 370000ef jal ra,2040216c <__mulsi3> +20401e00: 00040593 mv a1,s0 +20401e04: 00a12a23 sw a0,20(sp) +20401e08: 000d0513 mv a0,s10 +20401e0c: 360000ef jal ra,2040216c <__mulsi3> +20401e10: 000d0593 mv a1,s10 +20401e14: 00050413 mv s0,a0 +20401e18: 000c8513 mv a0,s9 +20401e1c: 350000ef jal ra,2040216c <__mulsi3> +20401e20: 00050d13 mv s10,a0 +20401e24: 00090593 mv a1,s2 +20401e28: 000c8513 mv a0,s9 +20401e2c: 340000ef jal ra,2040216c <__mulsi3> +20401e30: 01412703 lw a4,20(sp) +20401e34: 00850533 add a0,a0,s0 +20401e38: 01075793 srli a5,a4,0x10 +20401e3c: 00a78533 add a0,a5,a0 +20401e40: 00857663 bleu s0,a0,20401e4c <__muldf3+0x44c> +20401e44: 01812683 lw a3,24(sp) +20401e48: 00dd0d33 add s10,s10,a3 +20401e4c: 01012783 lw a5,16(sp) +20401e50: 000106b7 lui a3,0x10 +20401e54: fff68693 addi a3,a3,-1 # ffff <__stack_size+0xf7ff> +20401e58: 00fb0b33 add s6,s6,a5 +20401e5c: 00d577b3 and a5,a0,a3 +20401e60: 00d77733 and a4,a4,a3 +20401e64: 01079793 slli a5,a5,0x10 +20401e68: 00e787b3 add a5,a5,a4 +20401e6c: 014b3a33 sltu s4,s6,s4 +20401e70: 018787b3 add a5,a5,s8 +20401e74: 01478433 add s0,a5,s4 +20401e78: 01bb0b33 add s6,s6,s11 +20401e7c: 00940733 add a4,s0,s1 +20401e80: 01bb3db3 sltu s11,s6,s11 +20401e84: 01b706b3 add a3,a4,s11 +20401e88: 0187bc33 sltu s8,a5,s8 +20401e8c: 01443433 sltu s0,s0,s4 +20401e90: 01055793 srli a5,a0,0x10 +20401e94: 00973733 sltu a4,a4,s1 +20401e98: 008c6433 or s0,s8,s0 +20401e9c: 01b6bdb3 sltu s11,a3,s11 +20401ea0: 00f40433 add s0,s0,a5 +20401ea4: 01b76db3 or s11,a4,s11 +20401ea8: 01b40433 add s0,s0,s11 +20401eac: 01a40433 add s0,s0,s10 +20401eb0: 0176d793 srli a5,a3,0x17 +20401eb4: 00941413 slli s0,s0,0x9 +20401eb8: 00f46433 or s0,s0,a5 +20401ebc: 00c12783 lw a5,12(sp) +20401ec0: 009b1493 slli s1,s6,0x9 +20401ec4: 017b5b13 srli s6,s6,0x17 +20401ec8: 00f4e4b3 or s1,s1,a5 +20401ecc: 009034b3 snez s1,s1 +20401ed0: 00969793 slli a5,a3,0x9 +20401ed4: 0164e4b3 or s1,s1,s6 +20401ed8: 00f4e4b3 or s1,s1,a5 +20401edc: 00741793 slli a5,s0,0x7 +20401ee0: 1207d263 bgez a5,20402004 <__muldf3+0x604> +20401ee4: 0014d793 srli a5,s1,0x1 +20401ee8: 0014f493 andi s1,s1,1 +20401eec: 0097e4b3 or s1,a5,s1 +20401ef0: 01f41793 slli a5,s0,0x1f +20401ef4: 00f4e4b3 or s1,s1,a5 +20401ef8: 00145413 srli s0,s0,0x1 +20401efc: 3ffa8713 addi a4,s5,1023 +20401f00: 10e05663 blez a4,2040200c <__muldf3+0x60c> +20401f04: 0074f793 andi a5,s1,7 +20401f08: 02078063 beqz a5,20401f28 <__muldf3+0x528> +20401f0c: 00f4f793 andi a5,s1,15 +20401f10: 00400693 li a3,4 +20401f14: 00d78a63 beq a5,a3,20401f28 <__muldf3+0x528> +20401f18: 00448793 addi a5,s1,4 +20401f1c: 0097b4b3 sltu s1,a5,s1 +20401f20: 00940433 add s0,s0,s1 +20401f24: 00078493 mv s1,a5 +20401f28: 00741793 slli a5,s0,0x7 +20401f2c: 0007da63 bgez a5,20401f40 <__muldf3+0x540> +20401f30: ff0007b7 lui a5,0xff000 +20401f34: fff78793 addi a5,a5,-1 # feffffff <_sp+0x7effbfff> +20401f38: 00f47433 and s0,s0,a5 +20401f3c: 400a8713 addi a4,s5,1024 +20401f40: 7fe00793 li a5,2046 +20401f44: 18e7c663 blt a5,a4,204020d0 <__muldf3+0x6d0> +20401f48: 0034da93 srli s5,s1,0x3 +20401f4c: 01d41493 slli s1,s0,0x1d +20401f50: 0154e4b3 or s1,s1,s5 +20401f54: 00345413 srli s0,s0,0x3 +20401f58: 001007b7 lui a5,0x100 +20401f5c: fff78793 addi a5,a5,-1 # fffff <__stack_size+0xff7ff> +20401f60: 00f47433 and s0,s0,a5 +20401f64: 7ff77793 andi a5,a4,2047 +20401f68: 80100737 lui a4,0x80100 +20401f6c: fff70713 addi a4,a4,-1 # 800fffff <_sp+0xfbfff> +20401f70: 01479793 slli a5,a5,0x14 +20401f74: 00e47433 and s0,s0,a4 +20401f78: 01fb9b93 slli s7,s7,0x1f +20401f7c: 00f46433 or s0,s0,a5 +20401f80: 017467b3 or a5,s0,s7 +20401f84: 05c12083 lw ra,92(sp) +20401f88: 05812403 lw s0,88(sp) +20401f8c: 00048513 mv a0,s1 +20401f90: 05012903 lw s2,80(sp) +20401f94: 05412483 lw s1,84(sp) +20401f98: 04c12983 lw s3,76(sp) +20401f9c: 04812a03 lw s4,72(sp) +20401fa0: 04412a83 lw s5,68(sp) +20401fa4: 04012b03 lw s6,64(sp) +20401fa8: 03c12b83 lw s7,60(sp) +20401fac: 03812c03 lw s8,56(sp) +20401fb0: 03412c83 lw s9,52(sp) +20401fb4: 03012d03 lw s10,48(sp) +20401fb8: 02c12d83 lw s11,44(sp) +20401fbc: 00078593 mv a1,a5 +20401fc0: 06010113 addi sp,sp,96 +20401fc4: 00008067 ret +20401fc8: 000b0b93 mv s7,s6 +20401fcc: 00090413 mv s0,s2 +20401fd0: 000d0493 mv s1,s10 +20401fd4: 000c8793 mv a5,s9 +20401fd8: 00200713 li a4,2 +20401fdc: 0ee78a63 beq a5,a4,204020d0 <__muldf3+0x6d0> +20401fe0: 00300713 li a4,3 +20401fe4: 0ce78c63 beq a5,a4,204020bc <__muldf3+0x6bc> +20401fe8: 00100713 li a4,1 +20401fec: f0e798e3 bne a5,a4,20401efc <__muldf3+0x4fc> +20401ff0: 00000413 li s0,0 +20401ff4: 00000493 li s1,0 +20401ff8: 0880006f j 20402080 <__muldf3+0x680> +20401ffc: 000c0b93 mv s7,s8 +20402000: fd9ff06f j 20401fd8 <__muldf3+0x5d8> +20402004: 00098a93 mv s5,s3 +20402008: ef5ff06f j 20401efc <__muldf3+0x4fc> +2040200c: 00100693 li a3,1 +20402010: 40e686b3 sub a3,a3,a4 +20402014: 03800793 li a5,56 +20402018: fcd7cce3 blt a5,a3,20401ff0 <__muldf3+0x5f0> +2040201c: 01f00793 li a5,31 +20402020: 06d7c463 blt a5,a3,20402088 <__muldf3+0x688> +20402024: 41ea8a93 addi s5,s5,1054 +20402028: 015417b3 sll a5,s0,s5 +2040202c: 00d4d733 srl a4,s1,a3 +20402030: 015494b3 sll s1,s1,s5 +20402034: 00e7e7b3 or a5,a5,a4 +20402038: 009034b3 snez s1,s1 +2040203c: 0097e4b3 or s1,a5,s1 +20402040: 00d45433 srl s0,s0,a3 +20402044: 0074f793 andi a5,s1,7 +20402048: 02078063 beqz a5,20402068 <__muldf3+0x668> +2040204c: 00f4f793 andi a5,s1,15 +20402050: 00400713 li a4,4 +20402054: 00e78a63 beq a5,a4,20402068 <__muldf3+0x668> +20402058: 00448793 addi a5,s1,4 +2040205c: 0097b4b3 sltu s1,a5,s1 +20402060: 00940433 add s0,s0,s1 +20402064: 00078493 mv s1,a5 +20402068: 00841793 slli a5,s0,0x8 +2040206c: 0607ca63 bltz a5,204020e0 <__muldf3+0x6e0> +20402070: 01d41793 slli a5,s0,0x1d +20402074: 0034d493 srli s1,s1,0x3 +20402078: 0097e4b3 or s1,a5,s1 +2040207c: 00345413 srli s0,s0,0x3 +20402080: 00000713 li a4,0 +20402084: ed5ff06f j 20401f58 <__muldf3+0x558> +20402088: fe100793 li a5,-31 +2040208c: 40e787b3 sub a5,a5,a4 +20402090: 02000613 li a2,32 +20402094: 00f457b3 srl a5,s0,a5 +20402098: 00000713 li a4,0 +2040209c: 00c68663 beq a3,a2,204020a8 <__muldf3+0x6a8> +204020a0: 43ea8a93 addi s5,s5,1086 +204020a4: 01541733 sll a4,s0,s5 +204020a8: 009764b3 or s1,a4,s1 +204020ac: 009034b3 snez s1,s1 +204020b0: 0097e4b3 or s1,a5,s1 +204020b4: 00000413 li s0,0 +204020b8: f8dff06f j 20402044 <__muldf3+0x644> +204020bc: 00080437 lui s0,0x80 +204020c0: 00000493 li s1,0 +204020c4: 7ff00713 li a4,2047 +204020c8: 00000b93 li s7,0 +204020cc: e8dff06f j 20401f58 <__muldf3+0x558> +204020d0: 00000413 li s0,0 +204020d4: 00000493 li s1,0 +204020d8: 7ff00713 li a4,2047 +204020dc: e7dff06f j 20401f58 <__muldf3+0x558> +204020e0: 00000413 li s0,0 +204020e4: 00000493 li s1,0 +204020e8: 00100713 li a4,1 +204020ec: e6dff06f j 20401f58 <__muldf3+0x558> + +204020f0 <__fixunsdfsi>: +204020f0: 0145d713 srli a4,a1,0x14 +204020f4: 001006b7 lui a3,0x100 +204020f8: 00050613 mv a2,a0 +204020fc: fff68793 addi a5,a3,-1 # fffff <__stack_size+0xff7ff> +20402100: 7ff77713 andi a4,a4,2047 +20402104: 3fe00513 li a0,1022 +20402108: 00b7f7b3 and a5,a5,a1 +2040210c: 01f5d593 srli a1,a1,0x1f +20402110: 04e55a63 ble a4,a0,20402164 <__fixunsdfsi+0x74> +20402114: 00000513 li a0,0 +20402118: 00059863 bnez a1,20402128 <__fixunsdfsi+0x38> +2040211c: 41e00593 li a1,1054 +20402120: fff00513 li a0,-1 +20402124: 00e5d463 ble a4,a1,2040212c <__fixunsdfsi+0x3c> +20402128: 00008067 ret +2040212c: 00d7e7b3 or a5,a5,a3 +20402130: 43300693 li a3,1075 +20402134: 40e686b3 sub a3,a3,a4 +20402138: 01f00593 li a1,31 +2040213c: 00d5cc63 blt a1,a3,20402154 <__fixunsdfsi+0x64> +20402140: bed70713 addi a4,a4,-1043 +20402144: 00e797b3 sll a5,a5,a4 +20402148: 00d65533 srl a0,a2,a3 +2040214c: 00a7e533 or a0,a5,a0 +20402150: 00008067 ret +20402154: 41300513 li a0,1043 +20402158: 40e50533 sub a0,a0,a4 +2040215c: 00a7d533 srl a0,a5,a0 +20402160: 00008067 ret +20402164: 00000513 li a0,0 +20402168: 00008067 ret + +2040216c <__mulsi3>: +2040216c: 00050613 mv a2,a0 +20402170: 00000513 li a0,0 +20402174: 0015f693 andi a3,a1,1 +20402178: 00068463 beqz a3,20402180 <__mulsi3+0x14> +2040217c: 00c50533 add a0,a0,a2 +20402180: 0015d593 srli a1,a1,0x1 +20402184: 00161613 slli a2,a2,0x1 +20402188: fe0596e3 bnez a1,20402174 <__mulsi3+0x8> +2040218c: 00008067 ret + +20402190 <__divsi3>: +20402190: 06054063 bltz a0,204021f0 <__umodsi3+0x10> +20402194: 0605c663 bltz a1,20402200 <__umodsi3+0x20> + +20402198 <__udivsi3>: +20402198: 00058613 mv a2,a1 +2040219c: 00050593 mv a1,a0 +204021a0: fff00513 li a0,-1 +204021a4: 02060c63 beqz a2,204021dc <__udivsi3+0x44> +204021a8: 00100693 li a3,1 +204021ac: 00b67a63 bleu a1,a2,204021c0 <__udivsi3+0x28> +204021b0: 00c05863 blez a2,204021c0 <__udivsi3+0x28> +204021b4: 00161613 slli a2,a2,0x1 +204021b8: 00169693 slli a3,a3,0x1 +204021bc: feb66ae3 bltu a2,a1,204021b0 <__udivsi3+0x18> +204021c0: 00000513 li a0,0 +204021c4: 00c5e663 bltu a1,a2,204021d0 <__udivsi3+0x38> +204021c8: 40c585b3 sub a1,a1,a2 +204021cc: 00d56533 or a0,a0,a3 +204021d0: 0016d693 srli a3,a3,0x1 +204021d4: 00165613 srli a2,a2,0x1 +204021d8: fe0696e3 bnez a3,204021c4 <__udivsi3+0x2c> +204021dc: 00008067 ret + +204021e0 <__umodsi3>: +204021e0: 00008293 mv t0,ra +204021e4: fb5ff0ef jal ra,20402198 <__udivsi3> +204021e8: 00058513 mv a0,a1 +204021ec: 00028067 jr t0 +204021f0: 40a00533 neg a0,a0 +204021f4: 0005d863 bgez a1,20402204 <__umodsi3+0x24> +204021f8: 40b005b3 neg a1,a1 +204021fc: f9dff06f j 20402198 <__udivsi3> +20402200: 40b005b3 neg a1,a1 +20402204: 00008293 mv t0,ra +20402208: f91ff0ef jal ra,20402198 <__udivsi3> +2040220c: 40a00533 neg a0,a0 +20402210: 00028067 jr t0 + +20402214 <__modsi3>: +20402214: 00008293 mv t0,ra +20402218: 0005ca63 bltz a1,2040222c <__modsi3+0x18> +2040221c: 00054c63 bltz a0,20402234 <__modsi3+0x20> +20402220: f79ff0ef jal ra,20402198 <__udivsi3> +20402224: 00058513 mv a0,a1 +20402228: 00028067 jr t0 +2040222c: 40b005b3 neg a1,a1 +20402230: fe0558e3 bgez a0,20402220 <__modsi3+0xc> +20402234: 40a00533 neg a0,a0 +20402238: f61ff0ef jal ra,20402198 <__udivsi3> +2040223c: 40b00533 neg a0,a1 +20402240: 00028067 jr t0 + +20402244 <__clzsi2>: +20402244: 000107b7 lui a5,0x10 +20402248: 02f57a63 bleu a5,a0,2040227c <__clzsi2+0x38> +2040224c: 0ff00793 li a5,255 +20402250: 00a7b7b3 sltu a5,a5,a0 +20402254: 00379793 slli a5,a5,0x3 +20402258: 02000713 li a4,32 +2040225c: 40f70733 sub a4,a4,a5 +20402260: 00f557b3 srl a5,a0,a5 +20402264: 00000517 auipc a0,0x0 +20402268: 25450513 addi a0,a0,596 # 204024b8 <__clz_tab> +2040226c: 00f507b3 add a5,a0,a5 +20402270: 0007c503 lbu a0,0(a5) # 10000 <__stack_size+0xf800> +20402274: 40a70533 sub a0,a4,a0 +20402278: 00008067 ret +2040227c: 01000737 lui a4,0x1000 +20402280: 01000793 li a5,16 +20402284: fce56ae3 bltu a0,a4,20402258 <__clzsi2+0x14> +20402288: 01800793 li a5,24 +2040228c: fcdff06f j 20402258 <__clzsi2+0x14> diff --git a/hello/wrap_printf.c b/hello/wrap_printf.c new file mode 100644 index 0000000..025d231 --- /dev/null +++ b/hello/wrap_printf.c @@ -0,0 +1,271 @@ +/* The functions in this file are only meant to support Dhrystone on an + * embedded RV32 system and are obviously incorrect in general. */ + +#include +#include +#include +#include +#include +#include + +#undef putchar +int putchar(int ch) +{ + return write(1, &ch, 1) == 1 ? ch : -1; +} + +static void sprintf_putch(int ch, void** data) +{ + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; +} + +static unsigned long getuint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long getint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*8]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static inline void print_double(void (*putch)(int, void**), void **putdat, + double num, int width, int prec) +{ + union { + double d; + uint64_t u; + } u; + u.d = num; + + if (u.u & (1ULL << 63)) { + putch('-', putdat); + u.u &= ~(1ULL << 63); + } + + for (int i = 0; i < prec; i++) + u.d *= 10; + + char buf[32], *pbuf = buf; + printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0); + if (prec > 0) { + for (int i = 0; i < prec; i++) { + pbuf[-i] = pbuf[-i-1]; + } + pbuf[-prec] = '.'; + pbuf++; + } + + for (char* p = buf; p < pbuf; p++) + putch(*p, putdat); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch, err; + unsigned long num; + int base, lflag, width, precision, altflag; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') + return; + fmt++; + putch(ch, putdat); + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + altflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + altflag = 1; + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag + case 'l': + if (lflag) + goto bad; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // double + case 'f': + print_double(putch, putdat, va_arg(ap, double), width, precision); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long) num < 0) { + putch('-', putdat); + num = -(long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + bad: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +int __wrap_printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + vprintfmt((void*)putchar, 0, fmt, ap); + + va_end(ap); + return 0; // incorrect return value, but who cares, anyway? +} + +int __wrap_sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +}