import "RV32IBase.core_desc" import "RV32M.core_desc" import "RV32A.core_desc" import "RV32C.core_desc" import "RV32F.core_desc" import "RV32D.core_desc" import "RV64IBase.core_desc" import "RV64M.core_desc" import "RV64A.core_desc" Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC { constants { XLEN:=32; PCLEN:=32; // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b01000000000101000001000100000101; PGSIZE := 0x1000; //1 << 12; PGMASK := 0xfff; //PGSIZE-1 } } Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32DC { constants { XLEN:=32; FLEN:=64; PCLEN:=32; // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b01000000000101000001000100101101; PGSIZE := 0x1000; //1 << 12; PGMASK := 0xfff; //PGSIZE-1 } } Core RV64I provides RV64IBase { constants { XLEN:=64; PCLEN:=64; // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b10000000000001000000000100000000; PGSIZE := 0x1000; //1 << 12; PGMASK := 0xfff; //PGSIZE-1 } } Core RV64GC provides RV64IC, RV64A, RV64M, RV32A, RV32M, RV64F, RV64D, RV32FC, RV32DC { constants { XLEN:=64; FLEN:=64; PCLEN:=64; // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b01000000000101000001000100101101; PGSIZE := 0x1000; //1 << 12; PGMASK := 0xfff; //PGSIZE-1 } }