diff --git a/.cproject b/.cproject index c53663e..2e0c551 100644 --- a/.cproject +++ b/.cproject @@ -76,7 +76,7 @@ - + diff --git a/riscv.sc/incl/sysc/SiFive/aon.h b/riscv.sc/incl/sysc/SiFive/aon.h index fe02e92..62afa03 100644 --- a/riscv.sc/incl/sysc/SiFive/aon.h +++ b/riscv.sc/incl/sysc/SiFive/aon.h @@ -17,13 +17,13 @@ #ifndef _AON_H_ #define _AON_H_ -#include +#include "scc/tlm_target.h" namespace sysc { class aon_regs; -class aon : public sc_core::sc_module, public tlm_target<> { +class aon : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(aon); sc_core::sc_in clk_i; diff --git a/riscv.sc/incl/sysc/SiFive/clint.h b/riscv.sc/incl/sysc/SiFive/clint.h index a0a035b..e1130cb 100644 --- a/riscv.sc/incl/sysc/SiFive/clint.h +++ b/riscv.sc/incl/sysc/SiFive/clint.h @@ -17,7 +17,7 @@ #ifndef _CLINT_H_ #define _CLINT_H_ -#include +#include "scc/tlm_target.h" namespace iss { namespace arch { @@ -32,7 +32,7 @@ namespace SiFive { class core_complex; } -class clint : public sc_core::sc_module, public tlm_target<> { +class clint : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(clint); sc_core::sc_in clk_i; diff --git a/riscv.sc/incl/sysc/SiFive/core_complex.h b/riscv.sc/incl/sysc/SiFive/core_complex.h index 6382cd4..824032c 100644 --- a/riscv.sc/incl/sysc/SiFive/core_complex.h +++ b/riscv.sc/incl/sysc/SiFive/core_complex.h @@ -37,13 +37,13 @@ #ifndef _SYSC_SIFIVE_FE310_H_ #define _SYSC_SIFIVE_FE310_H_ -#include -#include -#include -#include #include #include #include +#include "scc/ext_attribute.h" +#include "scc/initiator_mixin.h" +#include "scc/traceable.h" +#include "scc/utilities.h" namespace iss { class vm_if; @@ -67,25 +67,25 @@ public: namespace SiFive { class core_wrapper; -class core_complex : public sc_core::sc_module, public sysc::traceable { +class core_complex : public sc_core::sc_module, public scc::traceable { public: SC_HAS_PROCESS(core_complex); - sysc::initiator_mixin> initiator; + scc::initiator_mixin> initiator; sc_core::sc_in clk_i; sc_core::sc_in rst_i; - sysc::ext_attribute elf_file; + scc::ext_attribute elf_file; - sysc::ext_attribute enable_disass; + scc::ext_attribute enable_disass; - sysc::ext_attribute reset_address; + scc::ext_attribute reset_address; - sysc::ext_attribute gdb_server_port; + scc::ext_attribute gdb_server_port; - sysc::ext_attribute dump_ir; + scc::ext_attribute dump_ir; core_complex(sc_core::sc_module_name name); diff --git a/riscv.sc/incl/sysc/SiFive/gen/aon_regs.h b/riscv.sc/incl/sysc/SiFive/gen/aon_regs.h index 0d472bf..51ad1c4 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/aon_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/aon_regs.h @@ -36,14 +36,14 @@ #ifndef _AON_REGS_H_ #define _AON_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class aon_regs : public sc_core::sc_module, public sysc::resetable { +class aon_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations uint32_t r_wdogcfg; @@ -97,29 +97,29 @@ public: uint32_t r_pmukey; // register declarations - sysc::sc_register wdogcfg; - sysc::sc_register wdogcount; - sysc::sc_register wdogs; - sysc::sc_register wdogfeed; - sysc::sc_register wdogkey; - sysc::sc_register wdogcmp; - sysc::sc_register rtccfg; - sysc::sc_register rtclo; - sysc::sc_register rtchi; - sysc::sc_register rtcs; - sysc::sc_register rtccmp; - sysc::sc_register lfrosccfg; - sysc::sc_register_indexed backup; - sysc::sc_register_indexed pmuwakeupi; - sysc::sc_register_indexed pmusleepi; - sysc::sc_register pmuie; - sysc::sc_register pmucause; - sysc::sc_register pmusleep; - sysc::sc_register pmukey; + scc::sc_register wdogcfg; + scc::sc_register wdogcount; + scc::sc_register wdogs; + scc::sc_register wdogfeed; + scc::sc_register wdogkey; + scc::sc_register wdogcmp; + scc::sc_register rtccfg; + scc::sc_register rtclo; + scc::sc_register rtchi; + scc::sc_register rtcs; + scc::sc_register rtccmp; + scc::sc_register lfrosccfg; + scc::sc_register_indexed backup; + scc::sc_register_indexed pmuwakeupi; + scc::sc_register_indexed pmusleepi; + scc::sc_register pmuie; + scc::sc_register pmucause; + scc::sc_register pmusleep; + scc::sc_register pmukey; aon_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -148,7 +148,7 @@ inline sysc::aon_regs::aon_regs(sc_core::sc_module_name nm) , NAMED(pmusleep, r_pmusleep, 0, *this) , NAMED(pmukey, r_pmukey, 0, *this) {} -template inline void sysc::aon_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::aon_regs::registerResources(scc::tlm_target &target) { target.addResource(wdogcfg, 0x0UL); target.addResource(wdogcount, 0x8UL); target.addResource(wdogs, 0x10UL); diff --git a/riscv.sc/incl/sysc/SiFive/gen/clint_regs.h b/riscv.sc/incl/sysc/SiFive/gen/clint_regs.h index 306339e..eb9afda 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/clint_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/clint_regs.h @@ -36,14 +36,14 @@ #ifndef _CLINT_REGS_H_ #define _CLINT_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class clint_regs : public sc_core::sc_module, public sysc::resetable { +class clint_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations BEGIN_BF_DECL(msip_t, uint32_t); @@ -55,13 +55,13 @@ public: uint64_t r_mtime; // register declarations - sysc::sc_register msip; - sysc::sc_register mtimecmp; - sysc::sc_register mtime; + scc::sc_register msip; + scc::sc_register mtimecmp; + scc::sc_register mtime; clint_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -74,7 +74,7 @@ inline sysc::clint_regs::clint_regs(sc_core::sc_module_name nm) , NAMED(mtimecmp, r_mtimecmp, 0, *this) , NAMED(mtime, r_mtime, 0, *this) {} -template inline void sysc::clint_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::clint_regs::registerResources(scc::tlm_target &target) { target.addResource(msip, 0x0UL); target.addResource(mtimecmp, 0x4000UL); target.addResource(mtime, 0xbff8UL); diff --git a/riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h b/riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h index 8d8d5d2..33190d5 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h +++ b/riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h @@ -2,7 +2,7 @@ #define _E300_PLAT_MAP_H_ // need double braces, see // https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191 -const std::array, 8> e300_plat_map = {{ +const std::array, 8> e300_plat_map = {{ {&i_clint, 0x2000000, 0xc000}, {&i_plic, 0xc000000, 0x200008}, {&i_aon, 0x10000000, 0x150}, diff --git a/riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h b/riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h index 1dbb745..b7710e3 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h @@ -36,14 +36,14 @@ #ifndef _GPIO_REGS_H_ #define _GPIO_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class gpio_regs : public sc_core::sc_module, public sysc::resetable { +class gpio_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations uint32_t r_value; @@ -81,27 +81,27 @@ public: uint32_t r_out_xor; // register declarations - sysc::sc_register value; - sysc::sc_register input_en; - sysc::sc_register output_en; - sysc::sc_register port; - sysc::sc_register pue; - sysc::sc_register ds; - sysc::sc_register rise_ie; - sysc::sc_register rise_ip; - sysc::sc_register fall_ie; - sysc::sc_register fall_ip; - sysc::sc_register high_ie; - sysc::sc_register high_ip; - sysc::sc_register low_ie; - sysc::sc_register low_ip; - sysc::sc_register iof_en; - sysc::sc_register iof_sel; - sysc::sc_register out_xor; + scc::sc_register value; + scc::sc_register input_en; + scc::sc_register output_en; + scc::sc_register port; + scc::sc_register pue; + scc::sc_register ds; + scc::sc_register rise_ie; + scc::sc_register rise_ip; + scc::sc_register fall_ie; + scc::sc_register fall_ip; + scc::sc_register high_ie; + scc::sc_register high_ip; + scc::sc_register low_ie; + scc::sc_register low_ip; + scc::sc_register iof_en; + scc::sc_register iof_sel; + scc::sc_register out_xor; gpio_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -128,7 +128,7 @@ inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm) , NAMED(iof_sel, r_iof_sel, 0, *this) , NAMED(out_xor, r_out_xor, 0, *this) {} -template inline void sysc::gpio_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::gpio_regs::registerResources(scc::tlm_target &target) { target.addResource(value, 0x0UL); target.addResource(input_en, 0x4UL); target.addResource(output_en, 0x8UL); diff --git a/riscv.sc/incl/sysc/SiFive/gen/plic_regs.h b/riscv.sc/incl/sysc/SiFive/gen/plic_regs.h index 014951f..5e2f19a 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/plic_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/plic_regs.h @@ -36,14 +36,14 @@ #ifndef _PLIC_REGS_H_ #define _PLIC_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class plic_regs : public sc_core::sc_module, public sysc::resetable { +class plic_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations BEGIN_BF_DECL(priority_t, uint32_t); @@ -62,15 +62,15 @@ public: uint32_t r_claim_complete; // register declarations - sysc::sc_register_indexed priority; - sysc::sc_register pending; - sysc::sc_register enabled; - sysc::sc_register threshold; - sysc::sc_register claim_complete; + scc::sc_register_indexed priority; + scc::sc_register pending; + scc::sc_register enabled; + scc::sc_register threshold; + scc::sc_register claim_complete; plic_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -85,7 +85,7 @@ inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm) , NAMED(threshold, r_threshold, 0, *this) , NAMED(claim_complete, r_claim_complete, 0, *this) {} -template inline void sysc::plic_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::plic_regs::registerResources(scc::tlm_target &target) { target.addResource(priority, 0x4UL); target.addResource(pending, 0x1000UL); target.addResource(enabled, 0x2000UL); diff --git a/riscv.sc/incl/sysc/SiFive/gen/prci_regs.h b/riscv.sc/incl/sysc/SiFive/gen/prci_regs.h index a197408..cbe3d26 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/prci_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/prci_regs.h @@ -36,14 +36,14 @@ #ifndef _PRCI_REGS_H_ #define _PRCI_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class prci_regs : public sc_core::sc_module, public sysc::resetable { +class prci_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations BEGIN_BF_DECL(hfrosccfg_t, uint32_t); @@ -73,15 +73,15 @@ public: uint32_t r_coreclkcfg; // register declarations - sysc::sc_register hfrosccfg; - sysc::sc_register hfxosccfg; - sysc::sc_register pllcfg; - sysc::sc_register plloutdiv; - sysc::sc_register coreclkcfg; + scc::sc_register hfrosccfg; + scc::sc_register hfxosccfg; + scc::sc_register pllcfg; + scc::sc_register plloutdiv; + scc::sc_register coreclkcfg; prci_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -96,7 +96,7 @@ inline sysc::prci_regs::prci_regs(sc_core::sc_module_name nm) , NAMED(plloutdiv, r_plloutdiv, 0, *this) , NAMED(coreclkcfg, r_coreclkcfg, 0, *this) {} -template inline void sysc::prci_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::prci_regs::registerResources(scc::tlm_target &target) { target.addResource(hfrosccfg, 0x0UL); target.addResource(hfxosccfg, 0x4UL); target.addResource(pllcfg, 0x8UL); diff --git a/riscv.sc/incl/sysc/SiFive/gen/spi_regs.h b/riscv.sc/incl/sysc/SiFive/gen/spi_regs.h index 05b3608..7db0f97 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/spi_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/spi_regs.h @@ -36,14 +36,14 @@ #ifndef _SPI_REGS_H_ #define _SPI_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class spi_regs : public sc_core::sc_module, public sysc::resetable { +class spi_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations BEGIN_BF_DECL(sckdiv_t, uint32_t); @@ -124,26 +124,26 @@ public: END_BF_DECL() r_ip; // register declarations - sysc::sc_register sckdiv; - sysc::sc_register sckmode; - sysc::sc_register csid; - sysc::sc_register csdef; - sysc::sc_register csmode; - sysc::sc_register delay0; - sysc::sc_register delay1; - sysc::sc_register fmt; - sysc::sc_register txdata; - sysc::sc_register rxdata; - sysc::sc_register txmark; - sysc::sc_register rxmark; - sysc::sc_register fctrl; - sysc::sc_register ffmt; - sysc::sc_register ie; - sysc::sc_register ip; + scc::sc_register sckdiv; + scc::sc_register sckmode; + scc::sc_register csid; + scc::sc_register csdef; + scc::sc_register csmode; + scc::sc_register delay0; + scc::sc_register delay1; + scc::sc_register fmt; + scc::sc_register txdata; + scc::sc_register rxdata; + scc::sc_register txmark; + scc::sc_register rxmark; + scc::sc_register fctrl; + scc::sc_register ffmt; + scc::sc_register ie; + scc::sc_register ip; spi_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -169,7 +169,7 @@ inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm) , NAMED(ie, r_ie, 0, *this) , NAMED(ip, r_ip, 0, *this) {} -template inline void sysc::spi_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::spi_regs::registerResources(scc::tlm_target &target) { target.addResource(sckdiv, 0x0UL); target.addResource(sckmode, 0x4UL); target.addResource(csid, 0x10UL); diff --git a/riscv.sc/incl/sysc/SiFive/gen/uart_regs.h b/riscv.sc/incl/sysc/SiFive/gen/uart_regs.h index 84f4fb5..67ed819 100644 --- a/riscv.sc/incl/sysc/SiFive/gen/uart_regs.h +++ b/riscv.sc/incl/sysc/SiFive/gen/uart_regs.h @@ -36,14 +36,14 @@ #ifndef _UART_REGS_H_ #define _UART_REGS_H_ -#include -#include -#include #include +#include "scc/register.h" +#include "scc/tlm_target.h" +#include "scc/utilities.h" namespace sysc { -class uart_regs : public sc_core::sc_module, public sysc::resetable { +class uart_regs : public sc_core::sc_module, public scc::resetable { public: // storage declarations BEGIN_BF_DECL(txdata_t, uint32_t); @@ -82,17 +82,17 @@ public: END_BF_DECL() r_div; // register declarations - sysc::sc_register txdata; - sysc::sc_register rxdata; - sysc::sc_register txctrl; - sysc::sc_register rxctrl; - sysc::sc_register ie; - sysc::sc_register ip; - sysc::sc_register div; + scc::sc_register txdata; + scc::sc_register rxdata; + scc::sc_register txctrl; + scc::sc_register rxctrl; + scc::sc_register ie; + scc::sc_register ip; + scc::sc_register div; uart_regs(sc_core::sc_module_name nm); - template void registerResources(sysc::tlm_target &target); + template void registerResources(scc::tlm_target &target); }; } ////////////////////////////////////////////////////////////////////////////// @@ -109,7 +109,7 @@ inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm) , NAMED(ip, r_ip, 0, *this) , NAMED(div, r_div, 0, *this) {} -template inline void sysc::uart_regs::registerResources(sysc::tlm_target &target) { +template inline void sysc::uart_regs::registerResources(scc::tlm_target &target) { target.addResource(txdata, 0x0UL); target.addResource(rxdata, 0x4UL); target.addResource(txctrl, 0x8UL); diff --git a/riscv.sc/incl/sysc/SiFive/gpio.h b/riscv.sc/incl/sysc/SiFive/gpio.h index 25426c0..9c72cd4 100644 --- a/riscv.sc/incl/sysc/SiFive/gpio.h +++ b/riscv.sc/incl/sysc/SiFive/gpio.h @@ -17,13 +17,13 @@ #ifndef _GPIO_H_ #define _GPIO_H_ -#include +#include "scc/tlm_target.h" namespace sysc { class gpio_regs; -class gpio : public sc_core::sc_module, public tlm_target<> { +class gpio : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(gpio); sc_core::sc_in clk_i; diff --git a/riscv.sc/incl/sysc/SiFive/platform.h b/riscv.sc/incl/sysc/SiFive/platform.h index dd3dc5d..e74f018 100644 --- a/riscv.sc/incl/sysc/SiFive/platform.h +++ b/riscv.sc/incl/sysc/SiFive/platform.h @@ -33,10 +33,10 @@ #include #include -#include -#include -#include +#include "scc/memory.h" +#include "scc/router.h" +#include "scc/utilities.h" #include "core_complex.h" namespace sysc { @@ -46,7 +46,7 @@ public: SC_HAS_PROCESS(platform); SiFive::core_complex i_core_complex; - router<> i_router; + scc::router<> i_router; uart i_uart0, i_uart1; spi i_spi; gpio i_gpio; @@ -55,8 +55,8 @@ public: prci i_prci; clint i_clint; - memory<512_MB, 32> i_mem_qspi; - memory<128_kB, 32> i_mem_ram; + scc::memory<512_MB, 32> i_mem_qspi; + scc::memory<128_kB, 32> i_mem_ram; sc_core::sc_signal s_clk; sc_core::sc_signal s_rst, s_mtime_int, s_msie_int; diff --git a/riscv.sc/incl/sysc/SiFive/plic.h b/riscv.sc/incl/sysc/SiFive/plic.h index 7b0ec3c..0c50814 100644 --- a/riscv.sc/incl/sysc/SiFive/plic.h +++ b/riscv.sc/incl/sysc/SiFive/plic.h @@ -17,13 +17,13 @@ #ifndef _PLIC_H_ #define _PLIC_H_ -#include +#include "scc/tlm_target.h" namespace sysc { class plic_regs; -class plic : public sc_core::sc_module, public tlm_target<> { +class plic : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(plic); sc_core::sc_in clk_i; diff --git a/riscv.sc/incl/sysc/SiFive/prci.h b/riscv.sc/incl/sysc/SiFive/prci.h index 5c9f376..463cb58 100644 --- a/riscv.sc/incl/sysc/SiFive/prci.h +++ b/riscv.sc/incl/sysc/SiFive/prci.h @@ -17,13 +17,13 @@ #ifndef _PRCI_H_ #define _PRCI_H_ -#include +#include "scc/tlm_target.h" namespace sysc { class prci_regs; -class prci : public sc_core::sc_module, public tlm_target<> { +class prci : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(prci); sc_core::sc_in clk_i; diff --git a/riscv.sc/incl/sysc/SiFive/spi.h b/riscv.sc/incl/sysc/SiFive/spi.h index e896fc6..78ae7df 100644 --- a/riscv.sc/incl/sysc/SiFive/spi.h +++ b/riscv.sc/incl/sysc/SiFive/spi.h @@ -17,13 +17,13 @@ #ifndef _SPI_H_ #define _SPI_H_ -#include +#include "scc/tlm_target.h" namespace sysc { class spi_regs; -class spi : public sc_core::sc_module, public tlm_target<> { +class spi : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(spi); sc_core::sc_in clk_i; diff --git a/riscv.sc/incl/sysc/SiFive/uart.h b/riscv.sc/incl/sysc/SiFive/uart.h index 4487484..efcd63e 100644 --- a/riscv.sc/incl/sysc/SiFive/uart.h +++ b/riscv.sc/incl/sysc/SiFive/uart.h @@ -17,13 +17,13 @@ #ifndef _UART_H_ #define _UART_H_ -#include +#include "scc/tlm_target.h" namespace sysc { class uart_regs; -class uart : public sc_core::sc_module, public tlm_target<> { +class uart : public sc_core::sc_module, public scc::tlm_target<> { public: SC_HAS_PROCESS(uart); sc_core::sc_in clk_i; diff --git a/riscv.sc/src/sc_main.cpp b/riscv.sc/src/sc_main.cpp index 9e24318..8988b82 100644 --- a/riscv.sc/src/sc_main.cpp +++ b/riscv.sc/src/sc_main.cpp @@ -26,10 +26,10 @@ #include #include #include -#include -#include -#include -#include +#include "scc/configurer.h" +#include "scc/report.h" +#include "scc/scv_tr_db.h" +#include "scc/tracer.h" using namespace sysc; namespace po = boost::program_options; @@ -42,7 +42,7 @@ const size_t ERROR_UNHANDLED_EXCEPTION = 2; int sc_main(int argc, char *argv[]) { // sc_report_handler::set_handler(my_report_handler); - sysc::Logger<>::reporting_level() = log::ERROR; + scc::Logger<>::reporting_level() = logging::ERROR; /////////////////////////////////////////////////////////////////////////// // CLI argument parsing /////////////////////////////////////////////////////////////////////////// @@ -84,7 +84,7 @@ int sc_main(int argc, char *argv[]) { LOGGER(DEFAULT)::reporting_level() = l; LOGGER(connection)::reporting_level() = l; LOGGER(SystemC)::reporting_level() = l; - sysc::Logger<>::reporting_level() = l; + scc::Logger<>::reporting_level() = l; } if (vm.count("log-file")) { // configure the connection logger @@ -100,12 +100,12 @@ int sc_main(int argc, char *argv[]) { /////////////////////////////////////////////////////////////////////////// // set up tracing & transaction recording /////////////////////////////////////////////////////////////////////////// - sysc::tracer trace("simple_system", static_cast(vm["trace"].as() >> 1), + scc::tracer trace("simple_system", static_cast(vm["trace"].as() >> 1), vm["trace"].as() != 0); /////////////////////////////////////////////////////////////////////////// // set up configuration /////////////////////////////////////////////////////////////////////////// - sysc::configurer cfg(vm["config-file"].as()); + scc::configurer cfg(vm["config-file"].as()); /////////////////////////////////////////////////////////////////////////// // instantiate top level /////////////////////////////////////////////////////////////////////////// diff --git a/riscv.sc/src/sysc/aon.cpp b/riscv.sc/src/sysc/aon.cpp index e177112..df6cd42 100644 --- a/riscv.sc/src/sysc/aon.cpp +++ b/riscv.sc/src/sysc/aon.cpp @@ -15,8 +15,9 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/aon.h" + +#include "scc/utilities.h" #include "sysc/SiFive/gen/aon_regs.h" -#include "sysc/utilities.h" namespace sysc { diff --git a/riscv.sc/src/sysc/clint.cpp b/riscv.sc/src/sysc/clint.cpp index f21de23..009f365 100644 --- a/riscv.sc/src/sysc/clint.cpp +++ b/riscv.sc/src/sysc/clint.cpp @@ -15,8 +15,9 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/clint.h" + +#include "scc/utilities.h" #include "sysc/SiFive/gen/clint_regs.h" -#include "sysc/utilities.h" namespace sysc { @@ -37,20 +38,20 @@ clint::clint(sc_core::sc_module_name nm) SC_METHOD(reset_cb); sensitive << rst_i; dont_initialize(); - regs->mtimecmp.set_write_cb([this](sc_register ®, uint64_t data) -> bool { + regs->mtimecmp.set_write_cb([this](scc::sc_register ®, uint64_t data) -> bool { if (!regs->in_reset()) { reg.put(data); this->update_mtime(); } return true; }); - regs->mtime.set_read_cb([this](const sc_register ®, uint64_t &data) -> bool { + regs->mtime.set_read_cb([this](const scc::sc_register ®, uint64_t &data) -> bool { this->update_mtime(); data = reg.get(); return true; }); - regs->mtime.set_write_cb([this](sc_register ®, uint64_t data) -> bool { return false; }); - regs->msip.set_write_cb([this](sc_register ®, uint32_t data) -> bool { + regs->mtime.set_write_cb([this](scc::sc_register ®, uint64_t data) -> bool { return false; }); + regs->msip.set_write_cb([this](scc::sc_register ®, uint32_t data) -> bool { reg.put(data); msip_int_o.write(regs->r_msip.msip); return true; diff --git a/riscv.sc/src/sysc/core_complex.cpp b/riscv.sc/src/sysc/core_complex.cpp index 8996316..67d7fa3 100644 --- a/riscv.sc/src/sysc/core_complex.cpp +++ b/riscv.sc/src/sysc/core_complex.cpp @@ -39,7 +39,8 @@ #include #include #include -#include + +#include "scc/report.h" namespace sysc { namespace SiFive { diff --git a/riscv.sc/src/sysc/gpio.cpp b/riscv.sc/src/sysc/gpio.cpp index 4236b1a..e0638a0 100644 --- a/riscv.sc/src/sysc/gpio.cpp +++ b/riscv.sc/src/sysc/gpio.cpp @@ -15,8 +15,9 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/gpio.h" + +#include "scc/utilities.h" #include "sysc/SiFive/gen/gpio_regs.h" -#include "sysc/utilities.h" namespace sysc { diff --git a/riscv.sc/src/sysc/plic.cpp b/riscv.sc/src/sysc/plic.cpp index 4e0d33e..dfe4c06 100644 --- a/riscv.sc/src/sysc/plic.cpp +++ b/riscv.sc/src/sysc/plic.cpp @@ -15,8 +15,9 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/plic.h" + +#include "scc/utilities.h" #include "sysc/SiFive/gen/plic_regs.h" -#include "sysc/utilities.h" namespace sysc { diff --git a/riscv.sc/src/sysc/prci.cpp b/riscv.sc/src/sysc/prci.cpp index 2e77656..a361858 100644 --- a/riscv.sc/src/sysc/prci.cpp +++ b/riscv.sc/src/sysc/prci.cpp @@ -15,8 +15,9 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/prci.h" + +#include "scc/utilities.h" #include "sysc/SiFive/gen/prci_regs.h" -#include "sysc/utilities.h" namespace sysc { @@ -36,14 +37,14 @@ prci::prci(sc_core::sc_module_name nm) sensitive << hfrosc_en_evt; dont_initialize(); - regs->hfrosccfg.set_write_cb([this](sysc::sc_register ®, uint32_t data) -> bool { + regs->hfrosccfg.set_write_cb([this](scc::sc_register ®, uint32_t data) -> bool { reg.put(data); if (this->regs->r_hfrosccfg & (1 << 30)) { // check rosc_en this->hfrosc_en_evt.notify(1, sc_core::SC_US); } return true; }); - regs->pllcfg.set_write_cb([this](sysc::sc_register ®, uint32_t data) -> bool { + regs->pllcfg.set_write_cb([this](scc::sc_register ®, uint32_t data) -> bool { reg.put(data); auto &pllcfg = this->regs->r_pllcfg; if (pllcfg.pllbypass == 0 && pllcfg.pllq != 0) { // set pll_lock if pll is selected diff --git a/riscv.sc/src/sysc/spi.cpp b/riscv.sc/src/sysc/spi.cpp index bda7942..7b060c2 100644 --- a/riscv.sc/src/sysc/spi.cpp +++ b/riscv.sc/src/sysc/spi.cpp @@ -15,8 +15,9 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/spi.h" + +#include "scc/utilities.h" #include "sysc/SiFive/gen/spi_regs.h" -#include "sysc/utilities.h" namespace sysc { diff --git a/riscv.sc/src/sysc/uart.cpp b/riscv.sc/src/sysc/uart.cpp index eef2758..867abce 100644 --- a/riscv.sc/src/sysc/uart.cpp +++ b/riscv.sc/src/sysc/uart.cpp @@ -15,9 +15,10 @@ //////////////////////////////////////////////////////////////////////////////// #include "sysc/SiFive/uart.h" + +#include "scc/report.h" +#include "scc/utilities.h" #include "sysc/SiFive/gen/uart_regs.h" -#include "sysc/report.h" -#include "sysc/utilities.h" namespace sysc { @@ -33,7 +34,7 @@ uart::uart(sc_core::sc_module_name nm) SC_METHOD(reset_cb); sensitive << rst_i; dont_initialize(); - regs->txdata.set_write_cb([this](sc_register ®, uint32_t data) -> bool { + regs->txdata.set_write_cb([this](scc::sc_register ®, uint32_t data) -> bool { if (!this->regs->in_reset()) { reg.put(data); this->transmit_data(); diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h index abdf585..1ecd7e7 100644 --- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h +++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h @@ -893,9 +893,9 @@ iss::status riscv_hart_msu_vp::read_mem(phys_addr_t paddr, unsigned length const auto &p = mem(paddr.val / mem.page_size); auto offs = paddr.val & mem.page_addr_mask; std::copy(p.data() + offs, p.data() + offs + length, data); - return iss::Ok; } } + return iss::Ok; } template @@ -911,22 +911,20 @@ iss::status riscv_hart_msu_vp::write_mem(phys_addr_t paddr, unsigned lengt std::cout << uart_buf.str(); uart_buf.str(""); } - return iss::Ok; + break; case 0x10008000: { // HFROSC base, hfrosccfg reg mem_type::page_type &p = mem(paddr.val / mem.page_size); size_t offs = paddr.val & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); uint8_t &x = *(p.data() + offs + 3); if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1 - return iss::Ok; - } + } break; case 0x10008008: { // HFROSC base, pllcfg reg mem_type::page_type &p = mem(paddr.val / mem.page_size); size_t offs = paddr.val & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); uint8_t &x = *(p.data() + offs + 3); x |= 0x80; // set pll lock upon writing - return iss::Ok; } break; default: { mem_type::page_type &p = mem(paddr.val / mem.page_size); @@ -969,9 +967,9 @@ iss::status riscv_hart_msu_vp::write_mem(phys_addr_t paddr, unsigned lengt *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; } } - return iss::Ok; } } + return iss::Ok; } template void riscv_hart_msu_vp::check_interrupt() { diff --git a/sc-components b/sc-components index 35379b7..f1c733d 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit 35379b77b6297557de15e37c009501dbdfc747f7 +Subproject commit f1c733dc2caed17742feca32a275eb21d15a4c8d