3885 lines
170 KiB
C++
3885 lines
170 KiB
C++
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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#include <iss/iss.h>
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#include <iss/debugger/gdb_session.h>
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#include <util/logging.h>
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#include <memory>
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#include <cstring>
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#include "iss/vm_base.h"
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#include "iss/arch/rv64ia.h"
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#include "iss/debugger/server.h"
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#include <boost/format.hpp>
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#include "iss/arch/riscv_hart_msu_vp.h"
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namespace iss {
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namespace rv64ia {
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using namespace iss::arch;
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using namespace llvm;
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using namespace iss::debugger;
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template<typename ARCH>
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struct vm_impl;
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template<typename ARCH>
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struct target_adapter: public target_adapter_base {
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target_adapter(server_if* srv, vm_impl<ARCH>* vm)
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: target_adapter_base(srv)
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, vm(vm)
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{
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}
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/*============== Thread Control ===============================*/
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/* Set generic thread */
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status set_gen_thread(rp_thread_ref& thread) override;
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/* Set control thread */
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status set_ctrl_thread(rp_thread_ref& thread) override;
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/* Get thread status */
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status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
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/*============= Register Access ================================*/
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/* Read all registers. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
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/* Write all registers. buf is 4-byte aligned and it is in target
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byte order */
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status write_registers(const std::vector<uint8_t>& data) override;
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/* Read one register. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
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/* Write one register. buf is 4-byte aligned and it is in target byte
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order */
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status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
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/*=================== Memory Access =====================*/
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/* Read memory, buf is 4-bytes aligned and it is in target
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byte order */
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status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
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/* Write memory, buf is 4-bytes aligned and it is in target
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byte order */
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status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
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status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
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status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num, bool& done) override;
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status current_thread_query(rp_thread_ref& thread) override;
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status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
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status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
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status raw_query(std::string in_buf, std::string& out_buf) override;
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status threadinfo_query(int first, std::string& out_buf) override;
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status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
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status packetsize_query(std::string& out_buf) override;
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status add_break(int type, uint64_t addr, unsigned int length) override;
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status remove_break(int type, uint64_t addr, unsigned int length) override;
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status resume_from_addr(bool step, int sig, uint64_t addr) override;
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protected:
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static inline constexpr addr_t map_addr(const addr_t& i){
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return i;
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}
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vm_impl<ARCH>* vm;
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rp_thread_ref thread_idx;
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};
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template<typename ARCH>
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struct vm_impl: public vm::vm_base<ARCH> {
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using super = typename vm::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t ;
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vm_impl();
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vm_impl(ARCH& core, bool dump=false);
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void enableDebug(bool enable) {
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super::sync_exec=super::ALL_SYNC;
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}
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target_adapter_if* accquire_target_adapter(server_if* srv){
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debugger_if::dbg_enabled=true;
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if(vm::vm_base<ARCH>::tgt_adapter==nullptr)
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vm::vm_base<ARCH>::tgt_adapter=new target_adapter<ARCH>(srv, this);
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return vm::vm_base<ARCH>::tgt_adapter;
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}
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protected:
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template<typename T> inline
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llvm::ConstantInt* size(T type){
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return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
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}
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inline llvm::Value * gen_choose(llvm::Value * cond, llvm::Value * trueVal, llvm::Value * falseVal, unsigned size) const {
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return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
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}
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std::tuple<vm::continuation_e, llvm::BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, llvm::BasicBlock*) override;
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void gen_leave_behavior(llvm::BasicBlock* leave_blk) override;
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void gen_raise_trap(uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(unsigned lvl);
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void gen_wait(unsigned type);
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void gen_trap_behavior(llvm::BasicBlock*) override;
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void gen_trap_check(llvm::BasicBlock* bb);
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inline
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void gen_set_pc(virt_addr_t pc, unsigned reg_num){
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llvm::Value* next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val), this->get_type(traits<ARCH>::XLEN));
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this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
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}
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inline
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llvm::Value* get_reg_ptr(unsigned i){
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void* ptr = this->core.get_regs_base_ptr()+traits<ARCH>::reg_byte_offset(i);
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llvm::PointerType* ptrType=nullptr;
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switch (traits<ARCH>::reg_bit_width(i)>>3) {
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case 8:
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ptrType=llvm::Type::getInt64PtrTy(this->mod->getContext());
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break;
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case 4:
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ptrType=llvm::Type::getInt32PtrTy(this->mod->getContext());
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break;
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case 2:
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ptrType=llvm::Type::getInt16PtrTy(this->mod->getContext());
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break;
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case 1:
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ptrType=llvm::Type::getInt8PtrTy(this->mod->getContext());
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break;
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default:
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throw std::runtime_error("unsupported access with");
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break;
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}
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return llvm::ConstantExpr::getIntToPtr(
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llvm::ConstantInt::get(this->mod->getContext(), llvm::APInt(
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8/*bits*/ * sizeof(uint8_t*),
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reinterpret_cast<uint64_t>(ptr)
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)),
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ptrType);
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}
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inline
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llvm::Value* gen_reg_load(unsigned i, unsigned level=0){
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// if(level){
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return this->builder->CreateLoad(get_reg_ptr(i), false);
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// } else {
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// if(!this->loaded_regs[i])
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// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
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// return this->loaded_regs[i];
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// }
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}
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inline
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void gen_set_pc(virt_addr_t pc){
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llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width));
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super::gen_set_reg(traits<ARCH>::PC, pc_l);
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}
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// some compile time constants
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enum {MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111};
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enum {EXTR_MASK16 = MASK16>>2, EXTR_MASK32 = MASK32>>2};
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enum {LUT_SIZE = 1<< bit_count(EXTR_MASK32), LUT_SIZE_C = 1<<bit_count(EXTR_MASK16)};
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using this_class = vm_impl<ARCH>;
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using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb);
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compile_func lut[LUT_SIZE];
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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compile_func* qlut[4];// = {lut_00, lut_01, lut_10, lut_11};
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const uint32_t lutmasks[4]={EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f){
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if(pos<0){
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lut[idx]=f;
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} else {
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auto bitmask = 1UL<<pos;
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if((mask & bitmask)==0){
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expand_bit_mask(pos-1, mask, value, valid, idx, lut, f);
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} else {
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if((valid & bitmask) == 0) {
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expand_bit_mask(pos-1, mask, value, valid, (idx<<1), lut, f);
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expand_bit_mask(pos-1, mask, value, valid, (idx<<1)+1, lut, f);
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} else {
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auto new_val = idx<<1;
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if((value&bitmask)!=0)
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new_val++;
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expand_bit_mask(pos-1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val){
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return extract_fields(29, val>>2, lutmasks[val&0x3], 0);
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}
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val){
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if(pos>=0) {
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auto bitmask = 1UL<<pos;
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if((mask & bitmask)==0){
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lut_val = extract_fields(pos-1, val, mask, lut_val);
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} else {
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auto new_val = lut_val<<1;
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if((val&bitmask)!=0)
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new_val++;
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lut_val = extract_fields(pos-1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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/* start generated code */
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const InstructionDesriptor instr_descr[75] = {
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/* entries are: valid value, valid mask, function ptr */
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/* instruction LWU */
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{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lwu},
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/* instruction LD */
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{32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld},
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/* instruction SD */
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{32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd},
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/* instruction SLLI */
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{32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli},
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/* instruction SRLI */
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{32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli},
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/* instruction SRAI */
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{32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai},
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/* instruction ADDIW */
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{32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw},
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/* instruction SLLIW */
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{32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, &this_class::__slliw},
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/* instruction SRLIW */
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{32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__srliw},
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/* instruction SRAIW */
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{32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__sraiw},
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/* instruction ADDW */
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{32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__addw},
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/* instruction SUBW */
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{32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__subw},
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/* instruction SLLW */
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|
{32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, &this_class::__sllw},
|
||
|
|
/* instruction SRLW */
|
||
|
|
{32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__srlw},
|
||
|
|
/* instruction SRAW */
|
||
|
|
{32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__sraw},
|
||
|
|
/* instruction LUI */
|
||
|
|
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
|
||
|
|
/* instruction AUIPC */
|
||
|
|
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
|
||
|
|
/* instruction JAL */
|
||
|
|
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
|
||
|
|
/* instruction JALR */
|
||
|
|
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
|
||
|
|
/* instruction BEQ */
|
||
|
|
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
|
||
|
|
/* instruction BNE */
|
||
|
|
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
|
||
|
|
/* instruction BLT */
|
||
|
|
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
|
||
|
|
/* instruction BGE */
|
||
|
|
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
|
||
|
|
/* instruction BLTU */
|
||
|
|
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
|
||
|
|
/* instruction BGEU */
|
||
|
|
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
|
||
|
|
/* instruction LB */
|
||
|
|
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
|
||
|
|
/* instruction LH */
|
||
|
|
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
|
||
|
|
/* instruction LW */
|
||
|
|
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
|
||
|
|
/* instruction LBU */
|
||
|
|
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
|
||
|
|
/* instruction LHU */
|
||
|
|
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
|
||
|
|
/* instruction SB */
|
||
|
|
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
|
||
|
|
/* instruction SH */
|
||
|
|
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
|
||
|
|
/* instruction SW */
|
||
|
|
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
|
||
|
|
/* instruction ADDI */
|
||
|
|
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
|
||
|
|
/* instruction SLTI */
|
||
|
|
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
|
||
|
|
/* instruction SLTIU */
|
||
|
|
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
|
||
|
|
/* instruction XORI */
|
||
|
|
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
|
||
|
|
/* instruction ORI */
|
||
|
|
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
|
||
|
|
/* instruction ANDI */
|
||
|
|
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
|
||
|
|
/* instruction ADD */
|
||
|
|
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
|
||
|
|
/* instruction SUB */
|
||
|
|
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
|
||
|
|
/* instruction SLL */
|
||
|
|
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
|
||
|
|
/* instruction SLT */
|
||
|
|
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
|
||
|
|
/* instruction SLTU */
|
||
|
|
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
|
||
|
|
/* instruction XOR */
|
||
|
|
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
|
||
|
|
/* instruction SRL */
|
||
|
|
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
|
||
|
|
/* instruction SRA */
|
||
|
|
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
|
||
|
|
/* instruction OR */
|
||
|
|
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
|
||
|
|
/* instruction AND */
|
||
|
|
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
|
||
|
|
/* instruction FENCE */
|
||
|
|
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
|
||
|
|
/* instruction FENCE_I */
|
||
|
|
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
|
||
|
|
/* instruction ECALL */
|
||
|
|
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
|
||
|
|
/* instruction EBREAK */
|
||
|
|
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
|
||
|
|
/* instruction URET */
|
||
|
|
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
|
||
|
|
/* instruction SRET */
|
||
|
|
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
|
||
|
|
/* instruction MRET */
|
||
|
|
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
|
||
|
|
/* instruction WFI */
|
||
|
|
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
|
||
|
|
/* instruction SFENCE.VMA */
|
||
|
|
{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
|
||
|
|
/* instruction CSRRW */
|
||
|
|
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
|
||
|
|
/* instruction CSRRS */
|
||
|
|
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
|
||
|
|
/* instruction CSRRC */
|
||
|
|
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
|
||
|
|
/* instruction CSRRWI */
|
||
|
|
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
|
||
|
|
/* instruction CSRRSI */
|
||
|
|
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
|
||
|
|
/* instruction CSRRCI */
|
||
|
|
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
|
||
|
|
/* instruction LR.D */
|
||
|
|
{32, 0b00010000000000000011000000101111, 0b11111001111100000111000001111111, &this_class::__lr_d},
|
||
|
|
/* instruction SC.D */
|
||
|
|
{32, 0b00011000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__sc_d},
|
||
|
|
/* instruction AMOSWAP.D */
|
||
|
|
{32, 0b00001000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_d},
|
||
|
|
/* instruction AMOADD.D */
|
||
|
|
{32, 0b00000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_d},
|
||
|
|
/* instruction AMOXOR.D */
|
||
|
|
{32, 0b00100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_d},
|
||
|
|
/* instruction AMOAND.D */
|
||
|
|
{32, 0b01100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_d},
|
||
|
|
/* instruction AMOOR.D */
|
||
|
|
{32, 0b01000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_d},
|
||
|
|
/* instruction AMOMIN.D */
|
||
|
|
{32, 0b10000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_d},
|
||
|
|
/* instruction AMOMAX.D */
|
||
|
|
{32, 0b10100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_d},
|
||
|
|
/* instruction AMOMINU.D */
|
||
|
|
{32, 0b11000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_d},
|
||
|
|
/* instruction AMOMAXU.D */
|
||
|
|
{32, 0b11100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_d},
|
||
|
|
};
|
||
|
|
// instruction LWU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lwu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LWU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LWU x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8),
|
||
|
|
64,
|
||
|
|
false);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LD
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __ld(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LD");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LD x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SD
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sd(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SD");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SD x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_const(64U, fld_imm_val),
|
||
|
|
64,
|
||
|
|
true));
|
||
|
|
Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLLI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLLI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_shamt_val = 0 | (bit_sub<20,6>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateShl(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_shamt_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRLI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRLI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_shamt_val = 0 | (bit_sub<20,6>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateLShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_shamt_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRAI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRAI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_shamt_val = 0 | (bit_sub<20,6>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_shamt_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ADDIW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __addiw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ADDIW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("ADDIW x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAdd(
|
||
|
|
this->gen_ext(
|
||
|
|
this->builder->CreateTrunc(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this-> get_type(32)
|
||
|
|
),
|
||
|
|
64,
|
||
|
|
true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_const(64U, fld_imm_val),
|
||
|
|
64,
|
||
|
|
true));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLLIW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slliw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLLIW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLLIW x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* sh_val_val = this->builder->CreateShl(
|
||
|
|
this->builder->CreateTrunc(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this-> get_type(32)
|
||
|
|
),
|
||
|
|
this->gen_const(32U, fld_shamt_val));
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
sh_val_val,
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRLIW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srliw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRLIW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRLIW x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* sh_val_val = this->builder->CreateLShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(32U, fld_shamt_val));
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
sh_val_val,
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRAIW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sraiw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRAIW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRAIW x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* sh_val_val = this->builder->CreateAShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(32U, fld_shamt_val));
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
sh_val_val,
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ADDW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __addw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ADDW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("ADDW");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
/* TODO: describe operations for ADDW ! */
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SUBW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __subw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SUBW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("SUBW");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
/* TODO: describe operations for SUBW ! */
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLLW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sllw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLLW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLLW x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* sh_val_val = this->builder->CreateShl(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
this->gen_const(32U, 31)));
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
sh_val_val,
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRLW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srlw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRLW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRLW x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* sh_val_val = this->builder->CreateLShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
this->gen_const(32U, 31)));
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
sh_val_val,
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRAW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sraw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRAW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRAW x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* sh_val_val = this->builder->CreateAShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
this->gen_const(32U, 31)));
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
sh_val_val,
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LUI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LUI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LUI x%1$d, 0x%2$05x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_const(64U, fld_imm_val);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AUIPC
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AUIPC");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AUIPC x%1%, 0x%2$08x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction JAL
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("JAL");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
int32_t fld_imm_val = 0 | (bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (signed_bit_sub<31,1>(instr) << 20);
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("JAL x%1$d, 0x%2$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* PC_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction JALR
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("JALR");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* ret_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
Value* PC_val = this->builder->CreateAnd(
|
||
|
|
ret_val,
|
||
|
|
this->builder->CreateNot(this->gen_const(64U, 1)));
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction BEQ
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("BEQ");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* PC_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_EQ,
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction BNE
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("BNE");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* PC_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_NE,
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction BLT
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("BLT");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* PC_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_SLT,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
64, true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
64, true)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction BGE
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("BGE");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* PC_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_SGE,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
64, true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
64, true)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction BLTU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("BLTU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* PC_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_ULT,
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction BGEU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("BGEU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* PC_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_UGE,
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val)),
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(traits<ARCH>::PC, 0),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LB
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LB");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LB x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 8/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LH
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LH");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LH x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 16/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LW x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LBU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LBU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 8/8),
|
||
|
|
64,
|
||
|
|
false);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LHU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LHU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 16/8),
|
||
|
|
64,
|
||
|
|
false);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SB
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SB");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SB x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(8)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SH
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SH");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SH x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(16)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SW x%1$d, %2%(x%3$d)");
|
||
|
|
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ADDI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ADDI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLTI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLTI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_SLT,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
64, true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_const(64U, fld_imm_val),
|
||
|
|
64, true)),
|
||
|
|
this->gen_const(64U, 1),
|
||
|
|
this->gen_const(64U, 0),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLTIU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLTIU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
int64_t full_imm_val = fld_imm_val;
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_ULT,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
64, false),
|
||
|
|
this->gen_ext(
|
||
|
|
full_imm_val,
|
||
|
|
64, false)),
|
||
|
|
this->gen_const(64U, 1),
|
||
|
|
this->gen_const(64U, 0),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction XORI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("XORI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateXor(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ORI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ORI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateOr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ANDI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ANDI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_const(64U, fld_imm_val));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ADD
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ADD");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAdd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SUB
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SUB");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateSub(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLL
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLL");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateShl(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
63));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLT
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLT");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_SLT,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
64, true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
64, true)),
|
||
|
|
this->gen_const(64U, 1),
|
||
|
|
this->gen_const(64U, 0),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SLTU
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SLTU");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_ULT,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
64,
|
||
|
|
false),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
64,
|
||
|
|
false)),
|
||
|
|
this->gen_const(64U, 1),
|
||
|
|
this->gen_const(64U, 0),
|
||
|
|
64);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction XOR
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("XOR");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateXor(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRL
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRL");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateLShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
63));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRA
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRA");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAShr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
63));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction OR
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("OR");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateOr(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AND
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AND");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->builder->CreateAnd(
|
||
|
|
this->gen_reg_load(fld_rs1_val, 0),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction FENCE
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("FENCE");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_succ_val = 0 | (bit_sub<20,4>(instr));
|
||
|
|
uint8_t fld_pred_val = 0 | (bit_sub<24,4>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("FENCE");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* FENCE_fence_val = this->builder->CreateOr(
|
||
|
|
this->builder->CreateShl(
|
||
|
|
this->gen_const(64U, fld_pred_val),
|
||
|
|
this->gen_const(64U, 4)),
|
||
|
|
this->gen_const(64U, fld_succ_val));
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::FENCE,
|
||
|
|
(uint64_t)0,
|
||
|
|
this->builder->CreateZExtOrTrunc(FENCE_fence_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction FENCE_I
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("FENCE_I");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("FENCE_I");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* FENCE_fencei_val = this->gen_const(64U, fld_imm_val);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::FENCE,
|
||
|
|
(uint64_t)1,
|
||
|
|
this->builder->CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::FLUSH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction ECALL
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("ECALL");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
;
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("ECALL");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
this->gen_raise_trap(0, 11);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction EBREAK
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("EBREAK");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
;
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("EBREAK");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
this->gen_raise_trap(0, 3);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction URET
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __uret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("URET");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
;
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("URET");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
this->gen_leave_trap(0);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SRET
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SRET");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
;
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("SRET");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
this->gen_leave_trap(1);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction MRET
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __mret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("MRET");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
;
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("MRET");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
this->gen_leave_trap(3);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction WFI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __wfi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("WFI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
;
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("WFI");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
this->gen_wait(1);
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SFENCE.VMA
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sfence_vma(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SFENCE.VMA");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
std::string opcode("SFENCE.VMA");
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
|
||
|
|
fmter % pc.val % opcode;
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* FENCE_fencevmal_val = this->gen_const(64U, fld_rs1_val);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::FENCE,
|
||
|
|
(uint64_t)2,
|
||
|
|
this->builder->CreateZExtOrTrunc(FENCE_fencevmal_val,this->get_type(64)));
|
||
|
|
Value* FENCE_fencevmau_val = this->gen_const(64U, fld_rs2_val);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::FENCE,
|
||
|
|
(uint64_t)3,
|
||
|
|
this->builder->CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction CSRRW
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("CSRRW");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* rs_val_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* csr_val_val = this->gen_read_mem(traits<ARCH>::CSR, fld_csr_val, 64/8);
|
||
|
|
Value* CSR_csr_val = rs_val_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
Value* X_rd_val = csr_val_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
} else {
|
||
|
|
Value* CSR_csr_val = rs_val_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction CSRRS
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrs(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("CSRRS");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* xrd_val = this->gen_read_mem(traits<ARCH>::CSR, fld_csr_val, 64/8);
|
||
|
|
Value* xrs1_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = xrd_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
if(fld_rs1_val != 0){
|
||
|
|
Value* CSR_csr_val = this->builder->CreateOr(
|
||
|
|
xrd_val,
|
||
|
|
xrs1_val);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction CSRRC
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("CSRRC");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* xrd_val = this->gen_read_mem(traits<ARCH>::CSR, fld_csr_val, 64/8);
|
||
|
|
Value* xrs1_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = xrd_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
if(fld_rs1_val != 0){
|
||
|
|
Value* CSR_csr_val = this->builder->CreateAnd(
|
||
|
|
xrd_val,
|
||
|
|
this->builder->CreateNot(xrs1_val));
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction CSRRWI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrwi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("CSRRWI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_read_mem(traits<ARCH>::CSR, fld_csr_val, 64/8);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* CSR_csr_val = this->gen_ext(
|
||
|
|
this->gen_const(64U, fld_zimm_val),
|
||
|
|
64,
|
||
|
|
false);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction CSRRSI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrsi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("CSRRSI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* res_val = this->gen_read_mem(traits<ARCH>::CSR, fld_csr_val, 64/8);
|
||
|
|
if(fld_zimm_val != 0){
|
||
|
|
Value* CSR_csr_val = this->builder->CreateOr(
|
||
|
|
res_val,
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_const(64U, fld_zimm_val),
|
||
|
|
64,
|
||
|
|
false));
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
}
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction CSRRCI
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrci(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("CSRRCI");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* res_val = this->gen_read_mem(traits<ARCH>::CSR, fld_csr_val, 64/8);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
if(fld_zimm_val != 0){
|
||
|
|
Value* CSR_csr_val = this->builder->CreateAnd(
|
||
|
|
res_val,
|
||
|
|
this->builder->CreateNot(this->gen_ext(
|
||
|
|
this->gen_const(64U, fld_zimm_val),
|
||
|
|
64,
|
||
|
|
false)));
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::CSR,
|
||
|
|
fld_csr_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction LR.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lr_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("LR.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("LR.D x%1$d, x%2$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
Value* RES_offs_val = this->gen_ext(
|
||
|
|
this->builder->CreateNeg(this->gen_const(8U, 1)),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::RES,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(RES_offs_val,this->get_type(64)));
|
||
|
|
}
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction SC.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sc_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("SC.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("SC.D x%1$d, x%2$d, x%3$d");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_read_mem(traits<ARCH>::RES, offs_val, 8/8);
|
||
|
|
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
|
||
|
|
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
|
||
|
|
llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext);
|
||
|
|
// this->builder->SetInsertPoint(bb);
|
||
|
|
this->gen_cond_branch(this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_NE,
|
||
|
|
res_val,
|
||
|
|
this->gen_const(64U, 0)),
|
||
|
|
bb_then,
|
||
|
|
bb_else);
|
||
|
|
this->builder->SetInsertPoint(bb_then);
|
||
|
|
{
|
||
|
|
Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 1);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_const(64U, 0);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
this->builder->CreateBr(bbnext);
|
||
|
|
this->builder->SetInsertPoint(bb_else);
|
||
|
|
{
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_const(64U, 1);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
this->builder->CreateBr(bbnext);
|
||
|
|
bb=bbnext;
|
||
|
|
this->builder->SetInsertPoint(bb);
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOSWAP.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoswap_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOSWAP.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOSWAP.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0);
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOADD.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoadd_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOADD.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOADD.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->builder->CreateAdd(
|
||
|
|
res_val,
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOXOR.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoxor_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOXOR.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOXOR.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->builder->CreateXor(
|
||
|
|
res_val,
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOAND.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoand_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOAND.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOAND.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->builder->CreateAnd(
|
||
|
|
res_val,
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOOR.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoor_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOOR.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOOR.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->builder->CreateOr(
|
||
|
|
res_val,
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0));
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOMIN.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomin_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOMIN.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOMIN.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_SGT,
|
||
|
|
this->gen_ext(
|
||
|
|
res_val,
|
||
|
|
64, true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
64, true)),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
res_val,
|
||
|
|
64);
|
||
|
|
Value* MEM_offs_val = res_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOMAX.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomax_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOMAX.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOMAX.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
true);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_SLT,
|
||
|
|
this->gen_ext(
|
||
|
|
res_val,
|
||
|
|
64, true),
|
||
|
|
this->gen_ext(
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
64, true)),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
res_val,
|
||
|
|
64);
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOMINU.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amominu_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOMINU.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOMINU.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
false);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_UGT,
|
||
|
|
res_val,
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0)),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
res_val,
|
||
|
|
64);
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
// instruction AMOMAXU.D
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomaxu_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
bb->setName("AMOMAXU.D");
|
||
|
|
|
||
|
|
this->gen_sync(iss::PRE_SYNC);
|
||
|
|
|
||
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
|
||
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
|
||
|
|
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
|
||
|
|
uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr));
|
||
|
|
uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr));
|
||
|
|
if(this->disass_enabled){
|
||
|
|
/* generate console output when executing the command */
|
||
|
|
boost::format ins_fmter("AMOMAXU.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)");
|
||
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
|
||
|
|
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
|
||
|
|
fmter % pc.val % ins_fmter.str();
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->builder->CreateGlobalStringPtr(fmter.str())
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("print_disass"), args);
|
||
|
|
}
|
||
|
|
pc=pc+4;
|
||
|
|
|
||
|
|
Value* offs_val = this->gen_reg_load(fld_rs1_val, 0);
|
||
|
|
Value* res_val = this->gen_ext(
|
||
|
|
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 64/8),
|
||
|
|
64,
|
||
|
|
false);
|
||
|
|
if(fld_rd_val != 0){
|
||
|
|
Value* X_rd_val = res_val;
|
||
|
|
this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
|
||
|
|
}
|
||
|
|
Value* res2_val = this->gen_choose(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_ULT,
|
||
|
|
res_val,
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0)),
|
||
|
|
this->gen_reg_load(fld_rs2_val, 0),
|
||
|
|
res_val,
|
||
|
|
64);
|
||
|
|
Value* MEM_offs_val = res2_val;
|
||
|
|
this->gen_write_mem(
|
||
|
|
traits<ARCH>::MEM,
|
||
|
|
offs_val,
|
||
|
|
this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
|
||
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
|
||
|
|
this->gen_trap_check(bb);
|
||
|
|
return std::make_tuple(vm::CONT, bb);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* end generated code */
|
||
|
|
/****************************************************************************
|
||
|
|
* end opcode definitions
|
||
|
|
****************************************************************************/
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||
|
|
//this->gen_sync(iss::PRE_SYNC);
|
||
|
|
this->builder->CreateStore(
|
||
|
|
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
|
||
|
|
get_reg_ptr(traits<ARCH>::PC), true);
|
||
|
|
this->builder->CreateStore(
|
||
|
|
this->builder->CreateAdd(
|
||
|
|
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
|
||
|
|
this->gen_const(64U, 1)),
|
||
|
|
get_reg_ptr(traits<ARCH>::ICOUNT), true);
|
||
|
|
if(this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
|
||
|
|
pc=pc+((instr&3) == 3?4:2);
|
||
|
|
this->gen_raise_trap(0, 2); // illegal instruction trap
|
||
|
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||
|
|
this->gen_trap_check(this->leave_blk);
|
||
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
template<typename CODE_WORD>
|
||
|
|
void debug_fn(CODE_WORD insn){
|
||
|
|
volatile CODE_WORD x=insn;
|
||
|
|
insn=2*x;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
vm_impl<ARCH>::vm_impl(){
|
||
|
|
this(new ARCH());
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
vm_impl<ARCH>::vm_impl(ARCH& core, bool dump) : vm::vm_base<ARCH>(core, dump) {
|
||
|
|
qlut[0] = lut_00.data();
|
||
|
|
qlut[1] = lut_01.data();
|
||
|
|
qlut[2] = lut_10.data();
|
||
|
|
qlut[3] = lut_11.data();
|
||
|
|
for(auto instr: instr_descr){
|
||
|
|
auto quantrant = instr.value&0x3;
|
||
|
|
expand_bit_mask(29, lutmasks[quantrant], instr.value>>2, instr.mask>>2, 0, qlut[quantrant], instr.op);
|
||
|
|
}
|
||
|
|
this->sync_exec=static_cast<sync_type>(this->sync_exec|core.needed_sync());
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, llvm::BasicBlock* this_block){
|
||
|
|
// we fetch at max 4 byte, alignment is 2
|
||
|
|
code_word_t insn = 0;
|
||
|
|
iss::addr_t paddr;
|
||
|
|
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||
|
|
try {
|
||
|
|
uint8_t* const data = (uint8_t*)&insn;
|
||
|
|
paddr=this->core.v2p(pc);
|
||
|
|
if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary
|
||
|
|
auto res = this->core.read(paddr, 2, data);
|
||
|
|
if(res!=iss::Ok)
|
||
|
|
throw trap_access(1, pc.val);
|
||
|
|
if((insn & 0x3) == 0x3){ // this is a 32bit instruction
|
||
|
|
res = this->core.read(this->core.v2p(pc+2), 2, data+2);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
auto res = this->core.read(paddr, 4, data);
|
||
|
|
if(res!=iss::Ok)
|
||
|
|
throw trap_access(1, pc.val);
|
||
|
|
}
|
||
|
|
} catch(trap_access& ta){
|
||
|
|
throw trap_access(ta.id, pc.val);
|
||
|
|
}
|
||
|
|
if(insn==0x0000006f)
|
||
|
|
throw simulation_stopped(0);
|
||
|
|
// curr pc on stack
|
||
|
|
typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
|
||
|
|
++inst_cnt;
|
||
|
|
auto lut_val = extract_fields(insn);
|
||
|
|
auto f = qlut[insn&0x3][lut_val];
|
||
|
|
if (f==nullptr){
|
||
|
|
f=&this_class::illegal_intruction;
|
||
|
|
}
|
||
|
|
return (this->*f)(pc, insn, this_block);
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
|
||
|
|
this->builder->SetInsertPoint(leave_blk);
|
||
|
|
this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
|
||
|
|
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
|
||
|
|
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
void vm_impl<ARCH>::gen_leave_trap(unsigned lvl){
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("leave_trap"), args);
|
||
|
|
auto* PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl<<8)+0x41, traits<ARCH>::XLEN/8);
|
||
|
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
void vm_impl<ARCH>::gen_wait(unsigned type){
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("wait"), args);
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock* trap_blk){
|
||
|
|
this->builder->SetInsertPoint(trap_blk);
|
||
|
|
auto* trap_state_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||
|
|
std::vector<llvm::Value*> args {
|
||
|
|
this->core_ptr,
|
||
|
|
this->adj_to64(trap_state_val),
|
||
|
|
this->adj_to64(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))
|
||
|
|
};
|
||
|
|
this->builder->CreateCall(this->mod->getFunction("enter_trap"), args);
|
||
|
|
auto* trap_addr_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||
|
|
this->builder->CreateRet(trap_addr_val);
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH> inline
|
||
|
|
void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){
|
||
|
|
auto* v = this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
|
||
|
|
this->gen_cond_branch(
|
||
|
|
this->builder->CreateICmp(
|
||
|
|
ICmpInst::ICMP_EQ,
|
||
|
|
v,
|
||
|
|
llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
|
||
|
|
bb,
|
||
|
|
this->trap_blk, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace rv64ia
|
||
|
|
|
||
|
|
#define CREATE_FUNCS(ARCH) \
|
||
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\
|
||
|
|
std::unique_ptr<rv64ia::vm_impl<ARCH> > ret = std::make_unique<rv64ia::vm_impl<ARCH> >(*core, dump);\
|
||
|
|
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\
|
||
|
|
return ret;\
|
||
|
|
}\
|
||
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
|
||
|
|
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
|
||
|
|
}\
|
||
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
|
||
|
|
return std::make_unique<rv64ia::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
|
||
|
|
}\
|
||
|
|
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
|
||
|
|
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\
|
||
|
|
}
|
||
|
|
|
||
|
|
CREATE_FUNCS(arch::rv64ia)
|
||
|
|
|
||
|
|
namespace rv64ia {
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
|
||
|
|
thread_idx=thread;
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) {
|
||
|
|
thread_idx=thread;
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) {
|
||
|
|
alive=1;
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* List threads. If first is non-zero then start from the first thread,
|
||
|
|
* otherwise start from arg, result points to array of threads to be
|
||
|
|
* filled out, result size is number of elements in the result,
|
||
|
|
* num points to the actual number of threads found, done is
|
||
|
|
* set if all threads are processed.
|
||
|
|
*/
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num,
|
||
|
|
size_t& num, bool& done) {
|
||
|
|
if(first==0){
|
||
|
|
result.clear();
|
||
|
|
result.push_back(thread_idx);
|
||
|
|
num=1;
|
||
|
|
done=true;
|
||
|
|
return Ok;
|
||
|
|
} else
|
||
|
|
return NotSupported;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) {
|
||
|
|
thread=thread_idx;
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
|
||
|
|
LOG(logging::TRACE)<<"reading target registers";
|
||
|
|
//return idx<0?:;
|
||
|
|
data.clear();
|
||
|
|
avail.clear();
|
||
|
|
std::vector<uint8_t> reg_data;
|
||
|
|
for(size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no){
|
||
|
|
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
|
||
|
|
auto reg_width=reg_bit_width/8;
|
||
|
|
reg_data.resize(reg_width);
|
||
|
|
vm->get_arch()->get_reg(reg_no, reg_data);
|
||
|
|
for(size_t j=0; j<reg_data.size(); ++j){
|
||
|
|
data.push_back(reg_data[j]);
|
||
|
|
avail.push_back(0xff);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// work around fill with F type registers
|
||
|
|
if(arch::traits<ARCH>::NUM_REGS < 65){
|
||
|
|
auto reg_width=sizeof(typename arch::traits<ARCH>::reg_t);
|
||
|
|
for(size_t reg_no = 0; reg_no < 33; ++reg_no){
|
||
|
|
for(size_t j=0; j<reg_width; ++j){
|
||
|
|
data.push_back(0x0);
|
||
|
|
avail.push_back(0x00);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) {
|
||
|
|
size_t data_index=0;
|
||
|
|
auto reg_count=arch::traits<ARCH>::NUM_REGS;
|
||
|
|
std::vector<uint8_t> reg_data;
|
||
|
|
for(size_t reg_no = 0; reg_no < reg_count; ++reg_no){
|
||
|
|
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
|
||
|
|
auto reg_width=reg_bit_width/8;
|
||
|
|
vm->get_arch()->set_reg(reg_no, std::vector<uint8_t>(data.begin()+data_index, data.begin()+data_index+reg_width));
|
||
|
|
data_index+=reg_width;
|
||
|
|
}
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
|
||
|
|
if(reg_no<65){
|
||
|
|
//auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no))/8;
|
||
|
|
data.resize(0);
|
||
|
|
vm->get_arch()->get_reg(reg_no, data);
|
||
|
|
avail.resize(data.size());
|
||
|
|
std::fill(avail.begin(), avail.end(), 0xff);
|
||
|
|
} else {
|
||
|
|
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no-65);
|
||
|
|
data.resize(sizeof(typename traits<ARCH>::reg_t));
|
||
|
|
avail.resize(sizeof(typename traits<ARCH>::reg_t));
|
||
|
|
std::fill(avail.begin(), avail.end(), 0xff);
|
||
|
|
vm->get_arch()->read(a, data.size(), data.data());
|
||
|
|
}
|
||
|
|
return data.size()>0?Ok:Err;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
|
||
|
|
if(reg_no<65)
|
||
|
|
vm->get_arch()->set_reg(reg_no, data);
|
||
|
|
else {
|
||
|
|
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no-65);
|
||
|
|
vm->get_arch()->write(a, data.size(), data.data());
|
||
|
|
}
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
|
||
|
|
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
|
||
|
|
auto f = [&]()->status {
|
||
|
|
return vm->get_arch()->read(a, data.size(), data.data());
|
||
|
|
};
|
||
|
|
return srv->execute_syncronized(f);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
|
||
|
|
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
|
||
|
|
return srv->execute_syncronized(&arch_if::write, vm->get_arch(), a, data.size(), data.data());
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) {
|
||
|
|
return NotSupported;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
|
||
|
|
text=0;
|
||
|
|
data=0;
|
||
|
|
bss=0;
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) {
|
||
|
|
return NotSupported;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) {
|
||
|
|
return NotSupported;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
|
||
|
|
if(first){
|
||
|
|
std::stringstream ss;
|
||
|
|
ss<<"m"<<std::hex<<thread_idx.val;
|
||
|
|
out_buf=ss.str();
|
||
|
|
} else {
|
||
|
|
out_buf="l";
|
||
|
|
}
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
|
||
|
|
char buf[20];
|
||
|
|
memset(buf, 0, 20);
|
||
|
|
sprintf (buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
|
||
|
|
out_buf=buf;
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::packetsize_query(std::string& out_buf) {
|
||
|
|
out_buf="PacketSize=1000";
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
|
||
|
|
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
|
||
|
|
auto eaddr=map_addr({iss::CODE, iss::PHYSICAL, addr+length});
|
||
|
|
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val-saddr.val);
|
||
|
|
LOG(logging::TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
|
||
|
|
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
|
||
|
|
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
|
||
|
|
unsigned handle=target_adapter_base::bp_lut.getEntry(saddr.val);
|
||
|
|
// TODO: check length of addr range
|
||
|
|
if(handle){
|
||
|
|
LOG(logging::TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
|
||
|
|
target_adapter_base::bp_lut.removeEntry(handle);
|
||
|
|
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
||
|
|
return Ok;
|
||
|
|
}
|
||
|
|
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
||
|
|
return Err;
|
||
|
|
}
|
||
|
|
|
||
|
|
template<typename ARCH>
|
||
|
|
status target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
|
||
|
|
unsigned reg_no = arch::traits<ARCH>::PC;
|
||
|
|
std::vector<uint8_t> data(8);
|
||
|
|
*(reinterpret_cast<uint64_t*>(&data[0]))=addr;
|
||
|
|
vm->get_arch()->set_reg(reg_no, data);
|
||
|
|
return resume_from_current(step, sig);
|
||
|
|
}
|
||
|
|
} // namespace rv64ia
|
||
|
|
} // namespace iss
|