2018-11-08 13:31:28 +01:00
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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2017-09-21 13:13:01 +02:00
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#include "sysc/SiFive/uart.h"
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2017-10-04 14:30:25 +02:00
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#include "scc/report.h"
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#include "scc/utilities.h"
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2017-09-21 13:13:01 +02:00
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#include "sysc/SiFive/gen/uart_regs.h"
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2018-11-08 13:31:28 +01:00
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#include "sysc/tlm_extensions.h"
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2017-10-26 11:41:35 +02:00
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2017-11-10 22:40:24 +01:00
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using namespace std;
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2017-09-21 13:13:01 +02:00
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namespace sysc {
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2018-11-08 13:31:28 +01:00
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using namespace sc_core;
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2017-10-26 11:41:35 +02:00
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2017-09-21 13:13:01 +02:00
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uart::uart(sc_core::sc_module_name nm)
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2017-09-26 17:10:10 +02:00
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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2018-07-12 15:27:36 +02:00
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, NAMED(tx_o)
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, NAMED(rx_i)
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, NAMED(irq_o)
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2018-07-23 22:15:38 +02:00
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, NAMED(bit_true_transfer, false)
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2018-11-08 13:31:28 +01:00
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, NAMEDD(regs, uart_regs)
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2018-07-23 22:15:38 +02:00
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, NAMED(rx_fifo, 8)
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, NAMED(tx_fifo, 8) {
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2017-09-21 13:13:01 +02:00
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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2017-09-22 11:23:23 +02:00
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sensitive << clk_i;
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2017-09-21 13:13:01 +02:00
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SC_METHOD(reset_cb);
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2017-09-22 11:23:23 +02:00
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sensitive << rst_i;
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2017-10-04 10:31:11 +02:00
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dont_initialize();
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2018-07-12 15:27:36 +02:00
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SC_THREAD(transmit_data);
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2018-11-08 13:31:28 +01:00
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rx_i.register_nb_transport(
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2021-08-26 17:27:33 +02:00
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[this](tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
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2018-11-08 13:31:28 +01:00
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this->receive_data(gp, delay);
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return tlm::TLM_COMPLETED;
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});
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regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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if (!this->regs->in_reset()) {
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reg.put(data);
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2018-07-12 15:27:36 +02:00
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tx_fifo.nb_write(static_cast<uint8_t>(regs->r_txdata.data));
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2018-11-08 13:31:28 +01:00
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regs->r_txdata.full = tx_fifo.num_free() == 0;
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regs->r_ip.txwm = regs->r_txctrl.txcnt <= (7 - tx_fifo.num_free()) ? 1 : 0;
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2018-07-12 15:27:36 +02:00
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update_irq();
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}
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> ®, uint32_t &data, sc_core::sc_time d) -> bool {
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2018-07-12 15:27:36 +02:00
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if (!this->regs->in_reset()) {
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uint8_t val;
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2018-11-08 13:31:28 +01:00
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if (rx_fifo.nb_read(val)) {
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regs->r_rxdata.data = val;
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if (regs->r_rxctrl.rxcnt <= rx_fifo.num_available()) {
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regs->r_ip.rxwm = 1;
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2018-07-12 15:27:36 +02:00
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update_irq();
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}
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}
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2018-11-08 13:31:28 +01:00
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data = reg.get() & reg.rdmask;
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2017-10-04 10:31:11 +02:00
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}
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->ie.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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2018-07-12 15:27:36 +02:00
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update_irq();
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2018-11-08 13:31:28 +01:00
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->ip.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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2018-07-12 15:27:36 +02:00
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update_irq();
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2018-11-08 13:31:28 +01:00
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return true;
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2018-07-12 15:27:36 +02:00
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});
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2017-09-21 13:13:01 +02:00
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}
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2018-11-08 13:31:28 +01:00
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uart::~uart() = default;
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2017-09-21 13:13:01 +02:00
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2018-07-12 15:27:36 +02:00
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void uart::update_irq() {
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2018-11-08 13:31:28 +01:00
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irq_o = (regs->r_ip.rxwm == 1 && regs->r_ie.rxwm == 1) || (regs->r_ip.txwm == 1 && regs->r_ie.txwm == 1);
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2018-07-12 15:27:36 +02:00
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}
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2018-11-08 13:31:28 +01:00
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void uart::clock_cb() { this->clk = clk_i.read(); }
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2017-09-21 13:13:01 +02:00
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void uart::reset_cb() {
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2017-09-22 11:23:23 +02:00
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if (rst_i.read())
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2017-09-21 13:13:01 +02:00
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regs->reset_start();
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else
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regs->reset_stop();
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}
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2017-10-04 10:31:11 +02:00
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void uart::transmit_data() {
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uint8_t txdata;
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tlm::tlm_phase phase(tlm::BEGIN_REQ);
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2018-07-13 20:04:07 +02:00
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sc_core::sc_time delay(SC_ZERO_TIME);
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sc_core::sc_time bit_duration(SC_ZERO_TIME);
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2018-11-08 13:31:28 +01:00
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sc_core::sc_time start_time;
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auto set_bit = [&](bool val) {
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2021-08-26 17:27:33 +02:00
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auto *gp = tlm::scc::tlm_signal_gp<>::create();
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2018-11-08 13:31:28 +01:00
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auto *ext = new sysc::tlm_signal_uart_extension();
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ext->tx.data_bits = 8;
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ext->tx.parity = false;
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ext->start_time = start_time;
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ext->tx.baud_rate = static_cast<unsigned>(1 / bit_duration.to_seconds());
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ext->tx.stop_bits = 1 + regs->r_txctrl.nstop;
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ext->tx.data = txdata;
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gp->set_extension(ext);
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gp->set_command(tlm::TLM_WRITE_COMMAND);
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gp->set_value(val);
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gp->acquire();
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phase = tlm::BEGIN_REQ;
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delay = SC_ZERO_TIME;
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tx_o->nb_transport_fw(*gp, phase, delay);
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gp->release();
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if (delay < bit_duration) wait(bit_duration - delay);
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2018-07-13 20:04:07 +02:00
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};
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wait(delay);
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2018-11-08 13:31:28 +01:00
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while (true) {
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2018-07-13 20:04:07 +02:00
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set_bit(true);
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2018-07-12 15:27:36 +02:00
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wait(tx_fifo.data_written_event());
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2018-11-08 13:31:28 +01:00
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while (tx_fifo.nb_read(txdata)) {
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regs->r_txdata.full = tx_fifo.num_free() == 0;
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regs->r_ip.txwm = regs->r_txctrl.txcnt <= (7 - tx_fifo.num_free()) ? 1 : 0;
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bit_duration = (regs->r_div.div + 1) * clk;
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start_time = sc_core::sc_time_stamp();
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2018-07-13 20:04:07 +02:00
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set_bit(false); // start bit
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2018-11-08 13:31:28 +01:00
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if (bit_true_transfer.get_value()) {
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for (int i = 8; i > 0; --i) set_bit(txdata & (1 << (i - 1))); // 8 data bits, MSB first
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if (regs->r_txctrl.nstop) set_bit(true); // stop bit 1
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2018-07-23 22:15:38 +02:00
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} else
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2018-11-08 13:31:28 +01:00
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wait(8 * bit_duration);
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2018-07-23 22:15:38 +02:00
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set_bit(true); // stop bit 1/2
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2018-07-12 15:27:36 +02:00
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}
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}
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}
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2021-08-26 17:27:33 +02:00
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void uart::receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
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2018-11-08 13:31:28 +01:00
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sysc::tlm_signal_uart_extension *ext{nullptr};
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2018-07-12 15:27:36 +02:00
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gp.get_extension(ext);
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2018-11-08 13:31:28 +01:00
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if (ext && ext->start_time != rx_last_start) {
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2018-07-12 15:27:36 +02:00
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auto data = static_cast<uint8_t>(ext->tx.data);
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2018-11-08 13:31:28 +01:00
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if (ext->tx.parity || ext->tx.data_bits != 8) data = rand(); // random value if wrong config
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2018-07-12 15:27:36 +02:00
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rx_fifo.write(data);
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2018-11-08 13:31:28 +01:00
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if (regs->r_rxctrl.rxcnt <= rx_fifo.num_available()) {
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regs->r_ip.rxwm = 1;
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2018-07-12 15:27:36 +02:00
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update_irq();
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}
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2018-11-08 13:31:28 +01:00
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rx_last_start = ext->start_time; // omit repeated handling of signal changes
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2017-10-04 10:31:11 +02:00
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}
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2018-07-12 15:27:36 +02:00
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gp.set_response_status(tlm::TLM_OK_RESPONSE);
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2017-10-04 10:31:11 +02:00
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}
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2017-09-21 13:13:01 +02:00
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} /* namespace sysc */
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